rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL
[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3399.c
CommitLineData
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1/*
2 * (C) Copyright 2015 Google, Inc
8fa6979b 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH
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4 *
5 * SPDX-License-Identifier: GPL-2.0
6 */
7
8#include <common.h>
9#include <clk-uclass.h>
10#include <dm.h>
5ae2fd97 11#include <dt-structs.h>
b0b3c865 12#include <errno.h>
5ae2fd97 13#include <mapmem.h>
b0b3c865 14#include <syscon.h>
364fc731 15#include <bitfield.h>
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16#include <asm/io.h>
17#include <asm/arch/clock.h>
18#include <asm/arch/cru_rk3399.h>
19#include <asm/arch/hardware.h>
20#include <dm/lists.h>
21#include <dt-bindings/clock/rk3399-cru.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
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25#if CONFIG_IS_ENABLED(OF_PLATDATA)
26struct rk3399_clk_plat {
27 struct dtd_rockchip_rk3399_cru dtd;
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28};
29
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30struct rk3399_pmuclk_plat {
31 struct dtd_rockchip_rk3399_pmucru dtd;
32};
33#endif
34
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35struct pll_div {
36 u32 refdiv;
37 u32 fbdiv;
38 u32 postdiv1;
39 u32 postdiv2;
40 u32 frac;
41};
42
43#define RATE_TO_DIV(input_rate, output_rate) \
44 ((input_rate) / (output_rate) - 1);
45#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
46
47#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
48 .refdiv = _refdiv,\
49 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
50 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
51
61dff33b 52#if defined(CONFIG_SPL_BUILD)
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53static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
54static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
61dff33b 55#else
b0b3c865 56static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
61dff33b 57#endif
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58
59static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
60static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
61
62static const struct pll_div *apll_l_cfgs[] = {
63 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
64 [APLL_L_600_MHZ] = &apll_l_600_cfg,
65};
66
67enum {
68 /* PLL_CON0 */
69 PLL_FBDIV_MASK = 0xfff,
70 PLL_FBDIV_SHIFT = 0,
71
72 /* PLL_CON1 */
73 PLL_POSTDIV2_SHIFT = 12,
74 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
75 PLL_POSTDIV1_SHIFT = 8,
76 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
77 PLL_REFDIV_MASK = 0x3f,
78 PLL_REFDIV_SHIFT = 0,
79
80 /* PLL_CON2 */
81 PLL_LOCK_STATUS_SHIFT = 31,
82 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
83 PLL_FRACDIV_MASK = 0xffffff,
84 PLL_FRACDIV_SHIFT = 0,
85
86 /* PLL_CON3 */
87 PLL_MODE_SHIFT = 8,
88 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
89 PLL_MODE_SLOW = 0,
90 PLL_MODE_NORM,
91 PLL_MODE_DEEP,
92 PLL_DSMPD_SHIFT = 3,
93 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
94 PLL_INTEGER_MODE = 1,
95
96 /* PMUCRU_CLKSEL_CON0 */
97 PMU_PCLK_DIV_CON_MASK = 0x1f,
98 PMU_PCLK_DIV_CON_SHIFT = 0,
99
100 /* PMUCRU_CLKSEL_CON1 */
101 SPI3_PLL_SEL_SHIFT = 7,
102 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
103 SPI3_PLL_SEL_24M = 0,
104 SPI3_PLL_SEL_PPLL = 1,
105 SPI3_DIV_CON_SHIFT = 0x0,
106 SPI3_DIV_CON_MASK = 0x7f,
107
108 /* PMUCRU_CLKSEL_CON2 */
109 I2C_DIV_CON_MASK = 0x7f,
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110 CLK_I2C8_DIV_CON_SHIFT = 8,
111 CLK_I2C0_DIV_CON_SHIFT = 0,
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112
113 /* PMUCRU_CLKSEL_CON3 */
5e79f443 114 CLK_I2C4_DIV_CON_SHIFT = 0,
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115
116 /* CLKSEL_CON0 */
117 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
118 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
119 CLK_CORE_L_PLL_SEL_SHIFT = 6,
120 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
121 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
122 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
123 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
124 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
125 CLK_CORE_L_DIV_MASK = 0x1f,
126 CLK_CORE_L_DIV_SHIFT = 0,
127
128 /* CLKSEL_CON1 */
129 PCLK_DBG_L_DIV_SHIFT = 0x8,
130 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
131 ATCLK_CORE_L_DIV_SHIFT = 0,
132 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
133
134 /* CLKSEL_CON14 */
135 PCLK_PERIHP_DIV_CON_SHIFT = 12,
136 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
137 HCLK_PERIHP_DIV_CON_SHIFT = 8,
138 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
139 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
140 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
141 ACLK_PERIHP_PLL_SEL_CPLL = 0,
142 ACLK_PERIHP_PLL_SEL_GPLL = 1,
143 ACLK_PERIHP_DIV_CON_SHIFT = 0,
144 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
145
146 /* CLKSEL_CON21 */
147 ACLK_EMMC_PLL_SEL_SHIFT = 7,
148 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
149 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
150 ACLK_EMMC_DIV_CON_SHIFT = 0,
151 ACLK_EMMC_DIV_CON_MASK = 0x1f,
152
153 /* CLKSEL_CON22 */
154 CLK_EMMC_PLL_SHIFT = 8,
155 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
156 CLK_EMMC_PLL_SEL_GPLL = 0x1,
fd4b2dc0 157 CLK_EMMC_PLL_SEL_24M = 0x5,
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158 CLK_EMMC_DIV_CON_SHIFT = 0,
159 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
160
161 /* CLKSEL_CON23 */
162 PCLK_PERILP0_DIV_CON_SHIFT = 12,
163 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
164 HCLK_PERILP0_DIV_CON_SHIFT = 8,
165 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
166 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
167 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
168 ACLK_PERILP0_PLL_SEL_CPLL = 0,
169 ACLK_PERILP0_PLL_SEL_GPLL = 1,
170 ACLK_PERILP0_DIV_CON_SHIFT = 0,
171 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
172
173 /* CLKSEL_CON25 */
174 PCLK_PERILP1_DIV_CON_SHIFT = 8,
175 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
176 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
177 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
178 HCLK_PERILP1_PLL_SEL_CPLL = 0,
179 HCLK_PERILP1_PLL_SEL_GPLL = 1,
180 HCLK_PERILP1_DIV_CON_SHIFT = 0,
181 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
182
183 /* CLKSEL_CON26 */
184 CLK_SARADC_DIV_CON_SHIFT = 8,
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185 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
186 CLK_SARADC_DIV_CON_WIDTH = 8,
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187
188 /* CLKSEL_CON27 */
189 CLK_TSADC_SEL_X24M = 0x0,
190 CLK_TSADC_SEL_SHIFT = 15,
191 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
192 CLK_TSADC_DIV_CON_SHIFT = 0,
193 CLK_TSADC_DIV_CON_MASK = 0x3ff,
194
195 /* CLKSEL_CON47 & CLKSEL_CON48 */
196 ACLK_VOP_PLL_SEL_SHIFT = 6,
197 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
198 ACLK_VOP_PLL_SEL_CPLL = 0x1,
199 ACLK_VOP_DIV_CON_SHIFT = 0,
200 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
201
202 /* CLKSEL_CON49 & CLKSEL_CON50 */
203 DCLK_VOP_DCLK_SEL_SHIFT = 11,
204 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
205 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
206 DCLK_VOP_PLL_SEL_SHIFT = 8,
207 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
208 DCLK_VOP_PLL_SEL_VPLL = 0,
209 DCLK_VOP_DIV_CON_MASK = 0xff,
210 DCLK_VOP_DIV_CON_SHIFT = 0,
211
212 /* CLKSEL_CON58 */
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213 CLK_SPI_PLL_SEL_WIDTH = 1,
214 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
215 CLK_SPI_PLL_SEL_CPLL = 0,
216 CLK_SPI_PLL_SEL_GPLL = 1,
217 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
218 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
219
220 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
221 CLK_SPI5_PLL_SEL_SHIFT = 15,
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222
223 /* CLKSEL_CON59 */
224 CLK_SPI1_PLL_SEL_SHIFT = 15,
225 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
226 CLK_SPI0_PLL_SEL_SHIFT = 7,
227 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
228
229 /* CLKSEL_CON60 */
230 CLK_SPI4_PLL_SEL_SHIFT = 15,
231 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
232 CLK_SPI2_PLL_SEL_SHIFT = 7,
233 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
234
235 /* CLKSEL_CON61 */
236 CLK_I2C_PLL_SEL_MASK = 1,
237 CLK_I2C_PLL_SEL_CPLL = 0,
238 CLK_I2C_PLL_SEL_GPLL = 1,
239 CLK_I2C5_PLL_SEL_SHIFT = 15,
240 CLK_I2C5_DIV_CON_SHIFT = 8,
241 CLK_I2C1_PLL_SEL_SHIFT = 7,
242 CLK_I2C1_DIV_CON_SHIFT = 0,
243
244 /* CLKSEL_CON62 */
245 CLK_I2C6_PLL_SEL_SHIFT = 15,
246 CLK_I2C6_DIV_CON_SHIFT = 8,
247 CLK_I2C2_PLL_SEL_SHIFT = 7,
248 CLK_I2C2_DIV_CON_SHIFT = 0,
249
250 /* CLKSEL_CON63 */
251 CLK_I2C7_PLL_SEL_SHIFT = 15,
252 CLK_I2C7_DIV_CON_SHIFT = 8,
253 CLK_I2C3_PLL_SEL_SHIFT = 7,
254 CLK_I2C3_DIV_CON_SHIFT = 0,
255
256 /* CRU_SOFTRST_CON4 */
257 RESETN_DDR0_REQ_SHIFT = 8,
258 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
259 RESETN_DDRPHY0_REQ_SHIFT = 9,
260 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
261 RESETN_DDR1_REQ_SHIFT = 12,
262 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
263 RESETN_DDRPHY1_REQ_SHIFT = 13,
264 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
265};
266
267#define VCO_MAX_KHZ (3200 * (MHz / KHz))
268#define VCO_MIN_KHZ (800 * (MHz / KHz))
269#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
270#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
271
272/*
273 * the div restructions of pll in integer mode, these are defined in
274 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
275 */
276#define PLL_DIV_MIN 16
277#define PLL_DIV_MAX 3200
278
279/*
280 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
281 * Formulas also embedded within the Fractional PLL Verilog model:
282 * If DSMPD = 1 (DSM is disabled, "integer mode")
283 * FOUTVCO = FREF / REFDIV * FBDIV
284 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
285 * Where:
286 * FOUTVCO = Fractional PLL non-divided output frequency
287 * FOUTPOSTDIV = Fractional PLL divided output frequency
288 * (output of second post divider)
289 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
290 * REFDIV = Fractional PLL input reference clock divider
291 * FBDIV = Integer value programmed into feedback divide
292 *
293 */
294static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
295{
296 /* All 8 PLLs have same VCO and output frequency range restrictions. */
297 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
298 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
299
300 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
301 "postdiv2=%d, vco=%u khz, output=%u khz\n",
302 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
303 div->postdiv2, vco_khz, output_khz);
304 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
305 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
306 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
307
308 /*
309 * When power on or changing PLL setting,
310 * we must force PLL into slow mode to ensure output stable clock.
311 */
312 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
313 PLL_MODE_SLOW << PLL_MODE_SHIFT);
314
315 /* use integer mode */
316 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
317 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
318
319 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
320 div->fbdiv << PLL_FBDIV_SHIFT);
321 rk_clrsetreg(&pll_con[1],
322 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
323 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
324 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
325 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
326 (div->refdiv << PLL_REFDIV_SHIFT));
327
328 /* waiting for pll lock */
329 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
330 udelay(1);
331
332 /* pll enter normal mode */
333 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
334 PLL_MODE_NORM << PLL_MODE_SHIFT);
335}
336
337static int pll_para_config(u32 freq_hz, struct pll_div *div)
338{
339 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
340 u32 postdiv1, postdiv2 = 1;
341 u32 fref_khz;
342 u32 diff_khz, best_diff_khz;
343 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
344 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
345 u32 vco_khz;
346 u32 freq_khz = freq_hz / KHz;
347
348 if (!freq_hz) {
349 printf("%s: the frequency can't be 0 Hz\n", __func__);
350 return -1;
351 }
352
353 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
354 if (postdiv1 > max_postdiv1) {
355 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
356 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
357 }
358
359 vco_khz = freq_khz * postdiv1 * postdiv2;
360
361 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
362 postdiv2 > max_postdiv2) {
363 printf("%s: Cannot find out a supported VCO"
364 " for Frequency (%uHz).\n", __func__, freq_hz);
365 return -1;
366 }
367
368 div->postdiv1 = postdiv1;
369 div->postdiv2 = postdiv2;
370
371 best_diff_khz = vco_khz;
372 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
373 fref_khz = ref_khz / refdiv;
374
375 fbdiv = vco_khz / fref_khz;
376 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
377 continue;
378 diff_khz = vco_khz - fbdiv * fref_khz;
379 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
380 fbdiv++;
381 diff_khz = fref_khz - diff_khz;
382 }
383
384 if (diff_khz >= best_diff_khz)
385 continue;
386
387 best_diff_khz = diff_khz;
388 div->refdiv = refdiv;
389 div->fbdiv = fbdiv;
390 }
391
392 if (best_diff_khz > 4 * (MHz/KHz)) {
393 printf("%s: Failed to match output frequency %u, "
394 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
395 best_diff_khz * KHz);
396 return -1;
397 }
398 return 0;
399}
400
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401void rk3399_configure_cpu(struct rk3399_cru *cru,
402 enum apll_l_frequencies apll_l_freq)
403{
404 u32 aclkm_div;
405 u32 pclk_dbg_div;
406 u32 atclk_div;
407
408 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
409
410 aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1;
411 assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ &&
412 aclkm_div < 0x1f);
413
414 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1;
415 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ &&
416 pclk_dbg_div < 0x1f);
417
418 atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1;
419 assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ &&
420 atclk_div < 0x1f);
421
422 rk_clrsetreg(&cru->clksel_con[0],
423 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
424 CLK_CORE_L_DIV_MASK,
425 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
426 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
427 0 << CLK_CORE_L_DIV_SHIFT);
428
429 rk_clrsetreg(&cru->clksel_con[1],
430 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
431 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
432 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
433}
434#define I2C_CLK_REG_MASK(bus) \
435 (I2C_DIV_CON_MASK << \
436 CLK_I2C ##bus## _DIV_CON_SHIFT | \
437 CLK_I2C_PLL_SEL_MASK << \
438 CLK_I2C ##bus## _PLL_SEL_SHIFT)
439
440#define I2C_CLK_REG_VALUE(bus, clk_div) \
441 ((clk_div - 1) << \
442 CLK_I2C ##bus## _DIV_CON_SHIFT | \
443 CLK_I2C_PLL_SEL_GPLL << \
444 CLK_I2C ##bus## _PLL_SEL_SHIFT)
445
446#define I2C_CLK_DIV_VALUE(con, bus) \
447 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
448 I2C_DIV_CON_MASK;
449
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450#define I2C_PMUCLK_REG_MASK(bus) \
451 (I2C_DIV_CON_MASK << \
452 CLK_I2C ##bus## _DIV_CON_SHIFT)
453
454#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
455 ((clk_div - 1) << \
456 CLK_I2C ##bus## _DIV_CON_SHIFT)
457
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458static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
459{
460 u32 div, con;
461
462 switch (clk_id) {
463 case SCLK_I2C1:
464 con = readl(&cru->clksel_con[61]);
465 div = I2C_CLK_DIV_VALUE(con, 1);
466 break;
467 case SCLK_I2C2:
468 con = readl(&cru->clksel_con[62]);
469 div = I2C_CLK_DIV_VALUE(con, 2);
470 break;
471 case SCLK_I2C3:
472 con = readl(&cru->clksel_con[63]);
473 div = I2C_CLK_DIV_VALUE(con, 3);
474 break;
475 case SCLK_I2C5:
476 con = readl(&cru->clksel_con[61]);
477 div = I2C_CLK_DIV_VALUE(con, 5);
478 break;
479 case SCLK_I2C6:
480 con = readl(&cru->clksel_con[62]);
481 div = I2C_CLK_DIV_VALUE(con, 6);
482 break;
483 case SCLK_I2C7:
484 con = readl(&cru->clksel_con[63]);
485 div = I2C_CLK_DIV_VALUE(con, 7);
486 break;
487 default:
488 printf("do not support this i2c bus\n");
489 return -EINVAL;
490 }
491
492 return DIV_TO_RATE(GPLL_HZ, div);
493}
494
495static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
496{
497 int src_clk_div;
498
499 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
500 src_clk_div = GPLL_HZ / hz;
501 assert(src_clk_div - 1 < 127);
502
503 switch (clk_id) {
504 case SCLK_I2C1:
505 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
506 I2C_CLK_REG_VALUE(1, src_clk_div));
507 break;
508 case SCLK_I2C2:
509 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
510 I2C_CLK_REG_VALUE(2, src_clk_div));
511 break;
512 case SCLK_I2C3:
513 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
514 I2C_CLK_REG_VALUE(3, src_clk_div));
515 break;
516 case SCLK_I2C5:
517 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
518 I2C_CLK_REG_VALUE(5, src_clk_div));
519 break;
520 case SCLK_I2C6:
521 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
522 I2C_CLK_REG_VALUE(6, src_clk_div));
523 break;
524 case SCLK_I2C7:
525 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
526 I2C_CLK_REG_VALUE(7, src_clk_div));
527 break;
528 default:
529 printf("do not support this i2c bus\n");
530 return -EINVAL;
531 }
532
beb90a53 533 return rk3399_i2c_get_clk(cru, clk_id);
b0b3c865
KY
534}
535
8fa6979b
PT
536/*
537 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
538 * to select either CPLL or GPLL as the clock-parent. The location within
539 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
540 */
541
542struct spi_clkreg {
543 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
544 uint8_t div_shift;
545 uint8_t sel_shift;
546};
547
548/*
549 * The entries are numbered relative to their offset from SCLK_SPI0.
550 *
551 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
552 * logic is not supported).
553 */
554static const struct spi_clkreg spi_clkregs[] = {
555 [0] = { .reg = 59,
556 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
557 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
558 [1] = { .reg = 59,
559 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
560 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
561 [2] = { .reg = 60,
562 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
563 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
564 [3] = { .reg = 60,
565 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
566 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
567 [4] = { .reg = 58,
568 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
569 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
570};
571
8fa6979b
PT
572static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
573{
574 const struct spi_clkreg *spiclk = NULL;
575 u32 div, val;
576
577 switch (clk_id) {
578 case SCLK_SPI0 ... SCLK_SPI5:
579 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
580 break;
581
582 default:
9b643e31 583 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
8fa6979b
PT
584 return -EINVAL;
585 }
586
587 val = readl(&cru->clksel_con[spiclk->reg]);
a8ee98df
PT
588 div = bitfield_extract(val, spiclk->div_shift,
589 CLK_SPI_PLL_DIV_CON_WIDTH);
8fa6979b
PT
590
591 return DIV_TO_RATE(GPLL_HZ, div);
592}
593
594static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
595{
596 const struct spi_clkreg *spiclk = NULL;
597 int src_clk_div;
598
217273cd
KY
599 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
600 assert(src_clk_div < 128);
8fa6979b
PT
601
602 switch (clk_id) {
603 case SCLK_SPI1 ... SCLK_SPI5:
604 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
605 break;
606
607 default:
9b643e31 608 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
8fa6979b
PT
609 return -EINVAL;
610 }
611
612 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
613 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
614 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
615 ((src_clk_div << spiclk->div_shift) |
616 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
617
beb90a53 618 return rk3399_spi_get_clk(cru, clk_id);
8fa6979b
PT
619}
620
b0b3c865
KY
621static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
622{
623 struct pll_div vpll_config = {0};
624 int aclk_vop = 198*MHz;
625 void *aclkreg_addr, *dclkreg_addr;
626 u32 div;
627
628 switch (clk_id) {
629 case DCLK_VOP0:
630 aclkreg_addr = &cru->clksel_con[47];
631 dclkreg_addr = &cru->clksel_con[49];
632 break;
633 case DCLK_VOP1:
634 aclkreg_addr = &cru->clksel_con[48];
635 dclkreg_addr = &cru->clksel_con[50];
636 break;
637 default:
638 return -EINVAL;
639 }
640 /* vop aclk source clk: cpll */
641 div = CPLL_HZ / aclk_vop;
642 assert(div - 1 < 32);
643
644 rk_clrsetreg(aclkreg_addr,
645 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
646 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
647 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
648
649 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
650 if (pll_para_config(hz, &vpll_config))
651 return -1;
652
653 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
654
655 rk_clrsetreg(dclkreg_addr,
656 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK|
657 DCLK_VOP_DIV_CON_MASK,
658 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
659 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
660 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
661
662 return hz;
663}
664
665static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
666{
667 u32 div, con;
668
669 switch (clk_id) {
998c61ae 670 case HCLK_SDMMC:
b0b3c865
KY
671 case SCLK_SDMMC:
672 con = readl(&cru->clksel_con[16]);
3a94d75d
KY
673 /* dwmmc controller have internal div 2 */
674 div = 2;
b0b3c865
KY
675 break;
676 case SCLK_EMMC:
677 con = readl(&cru->clksel_con[21]);
3a94d75d 678 div = 1;
b0b3c865
KY
679 break;
680 default:
681 return -EINVAL;
682 }
b0b3c865 683
3a94d75d 684 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
fd4b2dc0
KY
685 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
686 == CLK_EMMC_PLL_SEL_24M)
3a94d75d 687 return DIV_TO_RATE(OSC_HZ, div);
fd4b2dc0
KY
688 else
689 return DIV_TO_RATE(GPLL_HZ, div);
b0b3c865
KY
690}
691
692static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
693 ulong clk_id, ulong set_rate)
694{
695 int src_clk_div;
696 int aclk_emmc = 198*MHz;
697
698 switch (clk_id) {
998c61ae 699 case HCLK_SDMMC:
b0b3c865 700 case SCLK_SDMMC:
fd4b2dc0 701 /* Select clk_sdmmc source from GPLL by default */
3a94d75d
KY
702 /* mmc clock defaulg div 2 internal, provide double in cru */
703 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
b0b3c865 704
217273cd 705 if (src_clk_div > 128) {
fd4b2dc0 706 /* use 24MHz source for 400KHz clock */
3a94d75d 707 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
217273cd 708 assert(src_clk_div - 1 < 128);
fd4b2dc0
KY
709 rk_clrsetreg(&cru->clksel_con[16],
710 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
711 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
712 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
713 } else {
714 rk_clrsetreg(&cru->clksel_con[16],
715 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
716 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
717 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
718 }
b0b3c865
KY
719 break;
720 case SCLK_EMMC:
721 /* Select aclk_emmc source from GPLL */
217273cd
KY
722 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);
723 assert(src_clk_div - 1 < 32);
b0b3c865
KY
724
725 rk_clrsetreg(&cru->clksel_con[21],
726 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
727 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
728 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
729
730 /* Select clk_emmc source from GPLL too */
217273cd
KY
731 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
732 assert(src_clk_div - 1 < 128);
b0b3c865
KY
733
734 rk_clrsetreg(&cru->clksel_con[22],
735 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
736 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
737 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
738 break;
739 default:
740 return -EINVAL;
741 }
742 return rk3399_mmc_get_clk(cru, clk_id);
743}
744
a45f17e8
PT
745static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
746{
747 ulong ret;
748
749 /*
750 * The RGMII CLK can be derived either from an external "clkin"
751 * or can be generated from internally by a divider from SCLK_MAC.
752 */
753 if (readl(&cru->clksel_con[19]) & BIT(4)) {
754 /* An external clock will always generate the right rate... */
755 ret = rate;
756 } else {
757 /*
758 * No platform uses an internal clock to date.
759 * Implement this once it becomes necessary and print an error
760 * if someone tries to use it (while it remains unimplemented).
761 */
762 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
763 ret = 0;
764 }
765
766 return ret;
767}
768
5ae2fd97
KY
769#define PMUSGRF_DDR_RGN_CON16 0xff330040
770static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
771 ulong set_rate)
772{
773 struct pll_div dpll_cfg;
774
775 /* IC ECO bug, need to set this register */
776 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
777
778 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
779 switch (set_rate) {
780 case 200*MHz:
781 dpll_cfg = (struct pll_div)
782 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
783 break;
784 case 300*MHz:
785 dpll_cfg = (struct pll_div)
786 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
787 break;
788 case 666*MHz:
789 dpll_cfg = (struct pll_div)
790 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
791 break;
792 case 800*MHz:
793 dpll_cfg = (struct pll_div)
794 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
795 break;
796 case 933*MHz:
797 dpll_cfg = (struct pll_div)
798 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
799 break;
800 default:
9b643e31 801 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
5ae2fd97
KY
802 }
803 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
804
805 return set_rate;
806}
364fc731
DW
807
808static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
809{
810 u32 div, val;
811
812 val = readl(&cru->clksel_con[26]);
813 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
814 CLK_SARADC_DIV_CON_WIDTH);
815
816 return DIV_TO_RATE(OSC_HZ, div);
817}
818
819static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
820{
821 int src_clk_div;
822
823 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
824 assert(src_clk_div < 128);
825
826 rk_clrsetreg(&cru->clksel_con[26],
827 CLK_SARADC_DIV_CON_MASK,
828 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
829
830 return rk3399_saradc_get_clk(cru);
831}
832
b0b3c865
KY
833static ulong rk3399_clk_get_rate(struct clk *clk)
834{
835 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
836 ulong rate = 0;
837
838 switch (clk->id) {
839 case 0 ... 63:
840 return 0;
998c61ae 841 case HCLK_SDMMC:
b0b3c865
KY
842 case SCLK_SDMMC:
843 case SCLK_EMMC:
844 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
845 break;
846 case SCLK_I2C1:
847 case SCLK_I2C2:
848 case SCLK_I2C3:
849 case SCLK_I2C5:
850 case SCLK_I2C6:
851 case SCLK_I2C7:
852 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
853 break;
8fa6979b
PT
854 case SCLK_SPI0...SCLK_SPI5:
855 rate = rk3399_spi_get_clk(priv->cru, clk->id);
856 break;
857 case SCLK_UART0:
858 case SCLK_UART2:
859 return 24000000;
ffc1fac5
PT
860 break;
861 case PCLK_HDMI_CTRL:
862 break;
b0b3c865
KY
863 case DCLK_VOP0:
864 case DCLK_VOP1:
865 break;
a70feb46
PT
866 case PCLK_EFUSE1024NS:
867 break;
364fc731
DW
868 case SCLK_SARADC:
869 rate = rk3399_saradc_get_clk(priv->cru);
870 break;
b0b3c865
KY
871 default:
872 return -ENOENT;
873 }
874
875 return rate;
876}
877
878static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
879{
880 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
881 ulong ret = 0;
882
883 switch (clk->id) {
884 case 0 ... 63:
885 return 0;
d2f1f1ab
PT
886
887 case ACLK_PERIHP:
888 case HCLK_PERIHP:
889 case PCLK_PERIHP:
890 return 0;
891
892 case ACLK_PERILP0:
893 case HCLK_PERILP0:
894 case PCLK_PERILP0:
895 return 0;
896
897 case ACLK_CCI:
898 return 0;
899
900 case HCLK_PERILP1:
901 case PCLK_PERILP1:
902 return 0;
903
998c61ae 904 case HCLK_SDMMC:
b0b3c865
KY
905 case SCLK_SDMMC:
906 case SCLK_EMMC:
907 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
908 break;
65d83303 909 case SCLK_MAC:
a45f17e8 910 ret = rk3399_gmac_set_clk(priv->cru, rate);
65d83303 911 break;
b0b3c865
KY
912 case SCLK_I2C1:
913 case SCLK_I2C2:
914 case SCLK_I2C3:
915 case SCLK_I2C5:
916 case SCLK_I2C6:
917 case SCLK_I2C7:
918 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
919 break;
8fa6979b
PT
920 case SCLK_SPI0...SCLK_SPI5:
921 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
922 break;
ffc1fac5
PT
923 case PCLK_HDMI_CTRL:
924 case PCLK_VIO_GRF:
925 /* the PCLK gates for video are enabled by default */
926 break;
b0b3c865
KY
927 case DCLK_VOP0:
928 case DCLK_VOP1:
5e79f443 929 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
b0b3c865 930 break;
5ae2fd97
KY
931 case SCLK_DDRCLK:
932 ret = rk3399_ddr_set_clk(priv->cru, rate);
933 break;
a70feb46
PT
934 case PCLK_EFUSE1024NS:
935 break;
364fc731
DW
936 case SCLK_SARADC:
937 ret = rk3399_saradc_set_clk(priv->cru, rate);
938 break;
b0b3c865
KY
939 default:
940 return -ENOENT;
941 }
942
943 return ret;
944}
945
75b381aa 946static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent)
a45f17e8
PT
947{
948 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
949 const char *clock_output_name;
950 int ret;
951
952 /*
953 * If the requested parent is in the same clock-controller and
954 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
955 */
956 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
957 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
958 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
959 return 0;
960 }
961
962 /*
963 * Otherwise, we need to check the clock-output-names of the
964 * requested parent to see if the requested id is "clkin_gmac".
965 */
966 ret = dev_read_string_index(parent->dev, "clock-output-names",
967 parent->id, &clock_output_name);
968 if (ret < 0)
969 return -ENODATA;
970
971 /* If this is "clkin_gmac", switch to the external clock input */
972 if (!strcmp(clock_output_name, "clkin_gmac")) {
973 debug("%s: switching RGMII to CLKIN\n", __func__);
974 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
975 return 0;
976 }
977
978 return -EINVAL;
979}
980
75b381aa 981static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent)
a45f17e8
PT
982{
983 switch (clk->id) {
984 case SCLK_RMII_SRC:
985 return rk3399_gmac_set_parent(clk, parent);
986 }
987
988 debug("%s: unsupported clk %ld\n", __func__, clk->id);
989 return -ENOENT;
990}
991
2f01a2b2
PT
992static int rk3399_clk_enable(struct clk *clk)
993{
994 switch (clk->id) {
995 case HCLK_HOST0:
996 case HCLK_HOST0_ARB:
997 case HCLK_HOST1:
998 case HCLK_HOST1_ARB:
999 return 0;
a9bdd676
PT
1000
1001 case SCLK_MAC:
1002 case SCLK_MAC_RX:
1003 case SCLK_MAC_TX:
1004 case SCLK_MACREF:
1005 case SCLK_MACREF_OUT:
1006 case ACLK_GMAC:
1007 case PCLK_GMAC:
1008 /* Required to successfully probe the Designware GMAC driver */
1009 return 0;
2f01a2b2
PT
1010 }
1011
1012 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1013 return -ENOENT;
1014}
1015
b0b3c865
KY
1016static struct clk_ops rk3399_clk_ops = {
1017 .get_rate = rk3399_clk_get_rate,
1018 .set_rate = rk3399_clk_set_rate,
75b381aa 1019#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a45f17e8 1020 .set_parent = rk3399_clk_set_parent,
75b381aa 1021#endif
2f01a2b2 1022 .enable = rk3399_clk_enable,
b0b3c865
KY
1023};
1024
9f636a24
KY
1025#ifdef CONFIG_SPL_BUILD
1026static void rkclk_init(struct rk3399_cru *cru)
1027{
1028 u32 aclk_div;
1029 u32 hclk_div;
1030 u32 pclk_div;
1031
1032 rk3399_configure_cpu(cru, APLL_L_600_MHZ);
1033 /*
1034 * some cru registers changed by bootrom, we'd better reset them to
1035 * reset/default values described in TRM to avoid confusion in kernel.
1036 * Please consider these three lines as a fix of bootrom bug.
1037 */
1038 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1039 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1040 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1041
1042 /* configure gpll cpll */
1043 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1044 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1045
1046 /* configure perihp aclk, hclk, pclk */
1047 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1048 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1049
1050 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1051 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1052 PERIHP_ACLK_HZ && (hclk_div < 0x4));
1053
1054 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1055 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1056 PERIHP_ACLK_HZ && (pclk_div < 0x7));
1057
1058 rk_clrsetreg(&cru->clksel_con[14],
1059 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1060 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1061 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1062 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1063 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1064 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1065
1066 /* configure perilp0 aclk, hclk, pclk */
1067 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1068 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1069
1070 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1071 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1072 PERILP0_ACLK_HZ && (hclk_div < 0x4));
1073
1074 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1075 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1076 PERILP0_ACLK_HZ && (pclk_div < 0x7));
1077
1078 rk_clrsetreg(&cru->clksel_con[23],
1079 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1080 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1081 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1082 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1083 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1084 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1085
1086 /* perilp1 hclk select gpll as source */
1087 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1088 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1089 GPLL_HZ && (hclk_div < 0x1f));
1090
1091 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1092 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1093 PERILP1_HCLK_HZ && (hclk_div < 0x7));
1094
1095 rk_clrsetreg(&cru->clksel_con[25],
1096 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1097 HCLK_PERILP1_PLL_SEL_MASK,
1098 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1099 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1100 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1101}
1102#endif
1103
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1104static int rk3399_clk_probe(struct udevice *dev)
1105{
5ae2fd97 1106#ifdef CONFIG_SPL_BUILD
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1107 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1108
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1109#if CONFIG_IS_ENABLED(OF_PLATDATA)
1110 struct rk3399_clk_plat *plat = dev_get_platdata(dev);
b0b3c865 1111
c20ee0ed 1112 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
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1113#endif
1114 rkclk_init(priv->cru);
1115#endif
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1116 return 0;
1117}
1118
1119static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1120{
5ae2fd97 1121#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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1122 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1123
75c78598 1124 priv->cru = dev_read_addr_ptr(dev);
5ae2fd97 1125#endif
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1126 return 0;
1127}
1128
1129static int rk3399_clk_bind(struct udevice *dev)
1130{
1131 int ret;
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1132 struct udevice *sys_child;
1133 struct sysreset_reg *priv;
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1134
1135 /* The reset driver does not have a device node, so bind it here */
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1136 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1137 &sys_child);
1138 if (ret) {
1139 debug("Warning: No sysreset driver: ret=%d\n", ret);
1140 } else {
1141 priv = malloc(sizeof(struct sysreset_reg));
1142 priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
1143 glb_srst_fst_value);
1144 priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
1145 glb_srst_snd_value);
1146 sys_child->priv = priv;
1147 }
b0b3c865 1148
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1149#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1150 ret = offsetof(struct rk3399_cru, softrst_con[0]);
1151 ret = rockchip_reset_bind(dev, ret, 21);
1152 if (ret)
1153 debug("Warning: software reset driver bind faile\n");
1154#endif
1155
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1156 return 0;
1157}
1158
1159static const struct udevice_id rk3399_clk_ids[] = {
1160 { .compatible = "rockchip,rk3399-cru" },
1161 { }
1162};
1163
1164U_BOOT_DRIVER(clk_rk3399) = {
5ae2fd97 1165 .name = "rockchip_rk3399_cru",
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1166 .id = UCLASS_CLK,
1167 .of_match = rk3399_clk_ids,
1168 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1169 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1170 .ops = &rk3399_clk_ops,
1171 .bind = rk3399_clk_bind,
1172 .probe = rk3399_clk_probe,
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1173#if CONFIG_IS_ENABLED(OF_PLATDATA)
1174 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1175#endif
b0b3c865 1176};
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1177
1178static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1179{
1180 u32 div, con;
1181
1182 switch (clk_id) {
1183 case SCLK_I2C0_PMU:
1184 con = readl(&pmucru->pmucru_clksel[2]);
1185 div = I2C_CLK_DIV_VALUE(con, 0);
1186 break;
1187 case SCLK_I2C4_PMU:
1188 con = readl(&pmucru->pmucru_clksel[3]);
1189 div = I2C_CLK_DIV_VALUE(con, 4);
1190 break;
1191 case SCLK_I2C8_PMU:
1192 con = readl(&pmucru->pmucru_clksel[2]);
1193 div = I2C_CLK_DIV_VALUE(con, 8);
1194 break;
1195 default:
1196 printf("do not support this i2c bus\n");
1197 return -EINVAL;
1198 }
1199
1200 return DIV_TO_RATE(PPLL_HZ, div);
1201}
1202
1203static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1204 uint hz)
1205{
1206 int src_clk_div;
1207
1208 src_clk_div = PPLL_HZ / hz;
1209 assert(src_clk_div - 1 < 127);
1210
1211 switch (clk_id) {
1212 case SCLK_I2C0_PMU:
1213 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1214 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1215 break;
1216 case SCLK_I2C4_PMU:
1217 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1218 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1219 break;
1220 case SCLK_I2C8_PMU:
1221 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1222 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1223 break;
1224 default:
1225 printf("do not support this i2c bus\n");
1226 return -EINVAL;
1227 }
1228
1229 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1230}
1231
1232static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1233{
1234 u32 div, con;
1235
1236 /* PWM closk rate is same as pclk_pmu */
1237 con = readl(&pmucru->pmucru_clksel[0]);
1238 div = con & PMU_PCLK_DIV_CON_MASK;
1239
1240 return DIV_TO_RATE(PPLL_HZ, div);
1241}
1242
1243static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1244{
1245 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1246 ulong rate = 0;
1247
1248 switch (clk->id) {
434d5a00
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1249 case PLL_PPLL:
1250 return PPLL_HZ;
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1251 case PCLK_RKPWM_PMU:
1252 rate = rk3399_pwm_get_clk(priv->pmucru);
1253 break;
1254 case SCLK_I2C0_PMU:
1255 case SCLK_I2C4_PMU:
1256 case SCLK_I2C8_PMU:
1257 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1258 break;
1259 default:
1260 return -ENOENT;
1261 }
1262
1263 return rate;
1264}
1265
1266static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1267{
1268 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1269 ulong ret = 0;
1270
1271 switch (clk->id) {
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1272 case PLL_PPLL:
1273 /*
1274 * This has already been set up and we don't want/need
1275 * to change it here. Accept the request though, as the
1276 * device-tree has this in an 'assigned-clocks' list.
1277 */
1278 return PPLL_HZ;
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1279 case SCLK_I2C0_PMU:
1280 case SCLK_I2C4_PMU:
1281 case SCLK_I2C8_PMU:
1282 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1283 break;
1284 default:
1285 return -ENOENT;
1286 }
1287
1288 return ret;
1289}
1290
1291static struct clk_ops rk3399_pmuclk_ops = {
1292 .get_rate = rk3399_pmuclk_get_rate,
1293 .set_rate = rk3399_pmuclk_set_rate,
1294};
1295
5ae2fd97 1296#ifndef CONFIG_SPL_BUILD
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1297static void pmuclk_init(struct rk3399_pmucru *pmucru)
1298{
1299 u32 pclk_div;
1300
1301 /* configure pmu pll(ppll) */
1302 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1303
1304 /* configure pmu pclk */
1305 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
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1306 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1307 PMU_PCLK_DIV_CON_MASK,
1308 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1309}
5ae2fd97 1310#endif
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1311
1312static int rk3399_pmuclk_probe(struct udevice *dev)
1313{
61dff33b 1314#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
5e79f443 1315 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
61dff33b 1316#endif
5e79f443 1317
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1318#if CONFIG_IS_ENABLED(OF_PLATDATA)
1319 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1320
c20ee0ed 1321 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
5ae2fd97 1322#endif
5e79f443 1323
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1324#ifndef CONFIG_SPL_BUILD
1325 pmuclk_init(priv->pmucru);
1326#endif
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1327 return 0;
1328}
1329
1330static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1331{
5ae2fd97 1332#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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1333 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1334
75c78598 1335 priv->pmucru = dev_read_addr_ptr(dev);
5ae2fd97 1336#endif
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1337 return 0;
1338}
1339
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1340static int rk3399_pmuclk_bind(struct udevice *dev)
1341{
1342#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1343 int ret;
1344
1345 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1346 ret = rockchip_reset_bind(dev, ret, 2);
1347 if (ret)
1348 debug("Warning: software reset driver bind faile\n");
1349#endif
1350 return 0;
1351}
1352
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1353static const struct udevice_id rk3399_pmuclk_ids[] = {
1354 { .compatible = "rockchip,rk3399-pmucru" },
1355 { }
1356};
1357
c8a6bc96 1358U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
5ae2fd97 1359 .name = "rockchip_rk3399_pmucru",
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1360 .id = UCLASS_CLK,
1361 .of_match = rk3399_pmuclk_ids,
1362 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1363 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1364 .ops = &rk3399_pmuclk_ops,
1365 .probe = rk3399_pmuclk_probe,
538f67c3 1366 .bind = rk3399_pmuclk_bind,
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1367#if CONFIG_IS_ENABLED(OF_PLATDATA)
1368 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1369#endif
5e79f443 1370};