]>
Commit | Line | Data |
---|---|---|
3da42859 DN |
1 | /* |
2 | * Copyright Altera Corporation (C) 2012-2015 | |
3 | * | |
4 | * SPDX-License-Identifier: BSD-3-Clause | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
9 | #include <asm/arch/sdram.h> | |
04372fb8 | 10 | #include <errno.h> |
3da42859 | 11 | #include "sequencer.h" |
9c76df51 | 12 | |
3da42859 | 13 | static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = |
139823ec MV |
14 | (struct socfpga_sdr_rw_load_manager *) |
15 | (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800); | |
3da42859 | 16 | static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs = |
139823ec MV |
17 | (struct socfpga_sdr_rw_load_jump_manager *) |
18 | (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00); | |
3da42859 | 19 | static struct socfpga_sdr_reg_file *sdr_reg_file = |
a1c654a8 | 20 | (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS; |
3da42859 | 21 | static struct socfpga_sdr_scc_mgr *sdr_scc_mgr = |
139823ec MV |
22 | (struct socfpga_sdr_scc_mgr *) |
23 | (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00); | |
3da42859 | 24 | static struct socfpga_phy_mgr_cmd *phy_mgr_cmd = |
1bc6f14a | 25 | (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS; |
3da42859 | 26 | static struct socfpga_phy_mgr_cfg *phy_mgr_cfg = |
139823ec MV |
27 | (struct socfpga_phy_mgr_cfg *) |
28 | (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40); | |
3da42859 | 29 | static struct socfpga_data_mgr *data_mgr = |
c4815f76 | 30 | (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS; |
6cb9f167 MV |
31 | static struct socfpga_sdr_ctrl *sdr_ctrl = |
32 | (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; | |
33 | ||
d718a26b | 34 | const struct socfpga_sdram_rw_mgr_config *rwcfg; |
10c14261 | 35 | const struct socfpga_sdram_io_config *iocfg; |
042ff2d0 | 36 | const struct socfpga_sdram_misc_config *misccfg; |
d718a26b | 37 | |
3da42859 | 38 | #define DELTA_D 1 |
3da42859 DN |
39 | |
40 | /* | |
41 | * In order to reduce ROM size, most of the selectable calibration steps are | |
42 | * decided at compile time based on the user's calibration mode selection, | |
43 | * as captured by the STATIC_CALIB_STEPS selection below. | |
44 | * | |
45 | * However, to support simulation-time selection of fast simulation mode, where | |
46 | * we skip everything except the bare minimum, we need a few of the steps to | |
47 | * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the | |
48 | * check, which is based on the rtl-supplied value, or we dynamically compute | |
49 | * the value to use based on the dynamically-chosen calibration mode | |
50 | */ | |
51 | ||
52 | #define DLEVEL 0 | |
53 | #define STATIC_IN_RTL_SIM 0 | |
54 | #define STATIC_SKIP_DELAY_LOOPS 0 | |
55 | ||
56 | #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \ | |
57 | STATIC_SKIP_DELAY_LOOPS) | |
58 | ||
59 | /* calibration steps requested by the rtl */ | |
5ded7320 | 60 | u16 dyn_calib_steps; |
3da42859 DN |
61 | |
62 | /* | |
63 | * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option | |
64 | * instead of static, we use boolean logic to select between | |
65 | * non-skip and skip values | |
66 | * | |
67 | * The mask is set to include all bits when not-skipping, but is | |
68 | * zero when skipping | |
69 | */ | |
70 | ||
5ded7320 | 71 | u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ |
3da42859 DN |
72 | |
73 | #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \ | |
74 | ((non_skip_value) & skip_delay_mask) | |
75 | ||
76 | struct gbl_type *gbl; | |
77 | struct param_type *param; | |
3da42859 | 78 | |
5ded7320 MV |
79 | static void set_failing_group_stage(u32 group, u32 stage, |
80 | u32 substage) | |
3da42859 DN |
81 | { |
82 | /* | |
83 | * Only set the global stage if there was not been any other | |
84 | * failing group | |
85 | */ | |
86 | if (gbl->error_stage == CAL_STAGE_NIL) { | |
87 | gbl->error_substage = substage; | |
88 | gbl->error_stage = stage; | |
89 | gbl->error_group = group; | |
90 | } | |
91 | } | |
92 | ||
2c0d2d9c | 93 | static void reg_file_set_group(u16 set_group) |
3da42859 | 94 | { |
2c0d2d9c | 95 | clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16); |
3da42859 DN |
96 | } |
97 | ||
2c0d2d9c | 98 | static void reg_file_set_stage(u8 set_stage) |
3da42859 | 99 | { |
2c0d2d9c | 100 | clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff); |
3da42859 DN |
101 | } |
102 | ||
2c0d2d9c | 103 | static void reg_file_set_sub_stage(u8 set_sub_stage) |
3da42859 | 104 | { |
2c0d2d9c MV |
105 | set_sub_stage &= 0xff; |
106 | clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8); | |
3da42859 DN |
107 | } |
108 | ||
7c89c2d9 MV |
109 | /** |
110 | * phy_mgr_initialize() - Initialize PHY Manager | |
111 | * | |
112 | * Initialize PHY Manager. | |
113 | */ | |
9fa9c90e | 114 | static void phy_mgr_initialize(void) |
3da42859 | 115 | { |
7c89c2d9 MV |
116 | u32 ratio; |
117 | ||
3da42859 | 118 | debug("%s:%d\n", __func__, __LINE__); |
7c89c2d9 | 119 | /* Calibration has control over path to memory */ |
3da42859 DN |
120 | /* |
121 | * In Hard PHY this is a 2-bit control: | |
122 | * 0: AFI Mux Select | |
123 | * 1: DDIO Mux Select | |
124 | */ | |
1273dd9e | 125 | writel(0x3, &phy_mgr_cfg->mux_sel); |
3da42859 DN |
126 | |
127 | /* USER memory clock is not stable we begin initialization */ | |
1273dd9e | 128 | writel(0, &phy_mgr_cfg->reset_mem_stbl); |
3da42859 DN |
129 | |
130 | /* USER calibration status all set to zero */ | |
1273dd9e | 131 | writel(0, &phy_mgr_cfg->cal_status); |
3da42859 | 132 | |
1273dd9e | 133 | writel(0, &phy_mgr_cfg->cal_debug_info); |
3da42859 | 134 | |
7c89c2d9 MV |
135 | /* Init params only if we do NOT skip calibration. */ |
136 | if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) | |
137 | return; | |
138 | ||
1fa0c8c4 MV |
139 | ratio = rwcfg->mem_dq_per_read_dqs / |
140 | rwcfg->mem_virtual_groups_per_read_dqs; | |
7c89c2d9 MV |
141 | param->read_correct_mask_vg = (1 << ratio) - 1; |
142 | param->write_correct_mask_vg = (1 << ratio) - 1; | |
1fa0c8c4 MV |
143 | param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1; |
144 | param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1; | |
3da42859 DN |
145 | } |
146 | ||
080bf64e MV |
147 | /** |
148 | * set_rank_and_odt_mask() - Set Rank and ODT mask | |
149 | * @rank: Rank mask | |
150 | * @odt_mode: ODT mode, OFF or READ_WRITE | |
151 | * | |
152 | * Set Rank and ODT mask (On-Die Termination). | |
153 | */ | |
b2dfd100 | 154 | static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) |
3da42859 | 155 | { |
b2dfd100 MV |
156 | u32 odt_mask_0 = 0; |
157 | u32 odt_mask_1 = 0; | |
158 | u32 cs_and_odt_mask; | |
3da42859 | 159 | |
b2dfd100 MV |
160 | if (odt_mode == RW_MGR_ODT_MODE_OFF) { |
161 | odt_mask_0 = 0x0; | |
162 | odt_mask_1 = 0x0; | |
163 | } else { /* RW_MGR_ODT_MODE_READ_WRITE */ | |
1fa0c8c4 | 164 | switch (rwcfg->mem_number_of_ranks) { |
287cdf6b MV |
165 | case 1: /* 1 Rank */ |
166 | /* Read: ODT = 0 ; Write: ODT = 1 */ | |
3da42859 DN |
167 | odt_mask_0 = 0x0; |
168 | odt_mask_1 = 0x1; | |
287cdf6b MV |
169 | break; |
170 | case 2: /* 2 Ranks */ | |
1fa0c8c4 | 171 | if (rwcfg->mem_number_of_cs_per_dimm == 1) { |
080bf64e MV |
172 | /* |
173 | * - Dual-Slot , Single-Rank (1 CS per DIMM) | |
174 | * OR | |
175 | * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM) | |
176 | * | |
177 | * Since MEM_NUMBER_OF_RANKS is 2, they | |
178 | * are both single rank with 2 CS each | |
179 | * (special for RDIMM). | |
180 | * | |
3da42859 DN |
181 | * Read: Turn on ODT on the opposite rank |
182 | * Write: Turn on ODT on all ranks | |
183 | */ | |
184 | odt_mask_0 = 0x3 & ~(1 << rank); | |
185 | odt_mask_1 = 0x3; | |
186 | } else { | |
187 | /* | |
080bf64e MV |
188 | * - Single-Slot , Dual-Rank (2 CS per DIMM) |
189 | * | |
190 | * Read: Turn on ODT off on all ranks | |
191 | * Write: Turn on ODT on active rank | |
3da42859 DN |
192 | */ |
193 | odt_mask_0 = 0x0; | |
194 | odt_mask_1 = 0x3 & (1 << rank); | |
195 | } | |
287cdf6b MV |
196 | break; |
197 | case 4: /* 4 Ranks */ | |
198 | /* Read: | |
3da42859 | 199 | * ----------+-----------------------+ |
3da42859 DN |
200 | * | ODT | |
201 | * Read From +-----------------------+ | |
202 | * Rank | 3 | 2 | 1 | 0 | | |
203 | * ----------+-----+-----+-----+-----+ | |
204 | * 0 | 0 | 1 | 0 | 0 | | |
205 | * 1 | 1 | 0 | 0 | 0 | | |
206 | * 2 | 0 | 0 | 0 | 1 | | |
207 | * 3 | 0 | 0 | 1 | 0 | | |
208 | * ----------+-----+-----+-----+-----+ | |
209 | * | |
210 | * Write: | |
211 | * ----------+-----------------------+ | |
3da42859 DN |
212 | * | ODT | |
213 | * Write To +-----------------------+ | |
214 | * Rank | 3 | 2 | 1 | 0 | | |
215 | * ----------+-----+-----+-----+-----+ | |
216 | * 0 | 0 | 1 | 0 | 1 | | |
217 | * 1 | 1 | 0 | 1 | 0 | | |
218 | * 2 | 0 | 1 | 0 | 1 | | |
219 | * 3 | 1 | 0 | 1 | 0 | | |
220 | * ----------+-----+-----+-----+-----+ | |
221 | */ | |
222 | switch (rank) { | |
223 | case 0: | |
224 | odt_mask_0 = 0x4; | |
225 | odt_mask_1 = 0x5; | |
226 | break; | |
227 | case 1: | |
228 | odt_mask_0 = 0x8; | |
229 | odt_mask_1 = 0xA; | |
230 | break; | |
231 | case 2: | |
232 | odt_mask_0 = 0x1; | |
233 | odt_mask_1 = 0x5; | |
234 | break; | |
235 | case 3: | |
236 | odt_mask_0 = 0x2; | |
237 | odt_mask_1 = 0xA; | |
238 | break; | |
239 | } | |
287cdf6b | 240 | break; |
3da42859 | 241 | } |
3da42859 DN |
242 | } |
243 | ||
b2dfd100 MV |
244 | cs_and_odt_mask = (0xFF & ~(1 << rank)) | |
245 | ((0xFF & odt_mask_0) << 8) | | |
246 | ((0xFF & odt_mask_1) << 16); | |
1273dd9e MV |
247 | writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS | |
248 | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET); | |
3da42859 DN |
249 | } |
250 | ||
c76976d9 MV |
251 | /** |
252 | * scc_mgr_set() - Set SCC Manager register | |
253 | * @off: Base offset in SCC Manager space | |
254 | * @grp: Read/Write group | |
255 | * @val: Value to be set | |
256 | * | |
257 | * This function sets the SCC Manager (Scan Chain Control Manager) register. | |
258 | */ | |
259 | static void scc_mgr_set(u32 off, u32 grp, u32 val) | |
3da42859 | 260 | { |
c76976d9 MV |
261 | writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2)); |
262 | } | |
3da42859 | 263 | |
e893f4dc MV |
264 | /** |
265 | * scc_mgr_initialize() - Initialize SCC Manager registers | |
266 | * | |
267 | * Initialize SCC Manager registers. | |
268 | */ | |
c76976d9 MV |
269 | static void scc_mgr_initialize(void) |
270 | { | |
3da42859 | 271 | /* |
e893f4dc MV |
272 | * Clear register file for HPS. 16 (2^4) is the size of the |
273 | * full register file in the scc mgr: | |
274 | * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS + | |
275 | * MEM_IF_READ_DQS_WIDTH - 1); | |
3da42859 | 276 | */ |
c76976d9 | 277 | int i; |
e893f4dc | 278 | |
3da42859 | 279 | for (i = 0; i < 16; i++) { |
7ac40d25 | 280 | debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n", |
3da42859 | 281 | __func__, __LINE__, i); |
8e9e62c9 | 282 | scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0); |
3da42859 DN |
283 | } |
284 | } | |
285 | ||
5ded7320 | 286 | static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase) |
5ff825b8 | 287 | { |
c76976d9 | 288 | scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase); |
5ff825b8 MV |
289 | } |
290 | ||
5ded7320 | 291 | static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay) |
3da42859 | 292 | { |
c76976d9 | 293 | scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay); |
3da42859 DN |
294 | } |
295 | ||
5ded7320 | 296 | static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase) |
5ff825b8 | 297 | { |
c76976d9 | 298 | scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase); |
5ff825b8 MV |
299 | } |
300 | ||
5ded7320 | 301 | static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay) |
5ff825b8 | 302 | { |
c76976d9 | 303 | scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay); |
5ff825b8 MV |
304 | } |
305 | ||
70ed80af MV |
306 | static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay) |
307 | { | |
308 | scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay); | |
309 | } | |
310 | ||
5ded7320 | 311 | static void scc_mgr_set_dqs_io_in_delay(u32 delay) |
3da42859 | 312 | { |
1fa0c8c4 | 313 | scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, |
c76976d9 | 314 | delay); |
3da42859 DN |
315 | } |
316 | ||
70ed80af | 317 | static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay) |
3da42859 | 318 | { |
70ed80af MV |
319 | scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, |
320 | rwcfg->mem_dq_per_write_dqs + 1 + dm, | |
321 | delay); | |
5ff825b8 MV |
322 | } |
323 | ||
5ded7320 | 324 | static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay) |
5ff825b8 | 325 | { |
c76976d9 | 326 | scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay); |
5ff825b8 MV |
327 | } |
328 | ||
5ded7320 | 329 | static void scc_mgr_set_dqs_out1_delay(u32 delay) |
5ff825b8 | 330 | { |
1fa0c8c4 | 331 | scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, |
c76976d9 | 332 | delay); |
5ff825b8 MV |
333 | } |
334 | ||
5ded7320 | 335 | static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay) |
5ff825b8 | 336 | { |
c76976d9 | 337 | scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, |
1fa0c8c4 | 338 | rwcfg->mem_dq_per_write_dqs + 1 + dm, |
c76976d9 | 339 | delay); |
5ff825b8 MV |
340 | } |
341 | ||
342 | /* load up dqs config settings */ | |
5ded7320 | 343 | static void scc_mgr_load_dqs(u32 dqs) |
5ff825b8 MV |
344 | { |
345 | writel(dqs, &sdr_scc_mgr->dqs_ena); | |
346 | } | |
347 | ||
348 | /* load up dqs io config settings */ | |
349 | static void scc_mgr_load_dqs_io(void) | |
350 | { | |
351 | writel(0, &sdr_scc_mgr->dqs_io_ena); | |
352 | } | |
353 | ||
354 | /* load up dq config settings */ | |
5ded7320 | 355 | static void scc_mgr_load_dq(u32 dq_in_group) |
5ff825b8 MV |
356 | { |
357 | writel(dq_in_group, &sdr_scc_mgr->dq_ena); | |
358 | } | |
359 | ||
360 | /* load up dm config settings */ | |
5ded7320 | 361 | static void scc_mgr_load_dm(u32 dm) |
5ff825b8 MV |
362 | { |
363 | writel(dm, &sdr_scc_mgr->dm_ena); | |
3da42859 DN |
364 | } |
365 | ||
0b69b807 MV |
366 | /** |
367 | * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks | |
368 | * @off: Base offset in SCC Manager space | |
369 | * @grp: Read/Write group | |
370 | * @val: Value to be set | |
371 | * @update: If non-zero, trigger SCC Manager update for all ranks | |
372 | * | |
373 | * This function sets the SCC Manager (Scan Chain Control Manager) register | |
374 | * and optionally triggers the SCC update for all ranks. | |
375 | */ | |
376 | static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val, | |
377 | const int update) | |
3da42859 | 378 | { |
0b69b807 | 379 | u32 r; |
3da42859 | 380 | |
1fa0c8c4 | 381 | for (r = 0; r < rwcfg->mem_number_of_ranks; |
3da42859 | 382 | r += NUM_RANKS_PER_SHADOW_REG) { |
0b69b807 MV |
383 | scc_mgr_set(off, grp, val); |
384 | ||
385 | if (update || (r == 0)) { | |
386 | writel(grp, &sdr_scc_mgr->dqs_ena); | |
1273dd9e | 387 | writel(0, &sdr_scc_mgr->update); |
3da42859 DN |
388 | } |
389 | } | |
390 | } | |
391 | ||
0b69b807 MV |
392 | static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) |
393 | { | |
394 | /* | |
395 | * USER although the h/w doesn't support different phases per | |
396 | * shadow register, for simplicity our scc manager modeling | |
397 | * keeps different phase settings per shadow reg, and it's | |
398 | * important for us to keep them in sync to match h/w. | |
399 | * for efficiency, the scan chain update should occur only | |
400 | * once to sr0. | |
401 | */ | |
402 | scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET, | |
403 | read_group, phase, 0); | |
404 | } | |
405 | ||
5ded7320 MV |
406 | static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group, |
407 | u32 phase) | |
3da42859 | 408 | { |
0b69b807 MV |
409 | /* |
410 | * USER although the h/w doesn't support different phases per | |
411 | * shadow register, for simplicity our scc manager modeling | |
412 | * keeps different phase settings per shadow reg, and it's | |
413 | * important for us to keep them in sync to match h/w. | |
414 | * for efficiency, the scan chain update should occur only | |
415 | * once to sr0. | |
416 | */ | |
417 | scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, | |
418 | write_group, phase, 0); | |
3da42859 DN |
419 | } |
420 | ||
5ded7320 MV |
421 | static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, |
422 | u32 delay) | |
3da42859 | 423 | { |
3da42859 DN |
424 | /* |
425 | * In shadow register mode, the T11 settings are stored in | |
426 | * registers in the core, which are updated by the DQS_ENA | |
427 | * signals. Not issuing the SCC_MGR_UPD command allows us to | |
428 | * save lots of rank switching overhead, by calling | |
429 | * select_shadow_regs_for_update with update_scan_chains | |
430 | * set to 0. | |
431 | */ | |
0b69b807 MV |
432 | scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET, |
433 | read_group, delay, 1); | |
3da42859 DN |
434 | } |
435 | ||
5be355c1 MV |
436 | /** |
437 | * scc_mgr_set_oct_out1_delay() - Set OCT output delay | |
438 | * @write_group: Write group | |
439 | * @delay: Delay value | |
440 | * | |
441 | * This function sets the OCT output delay in SCC manager. | |
442 | */ | |
443 | static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay) | |
3da42859 | 444 | { |
1fa0c8c4 MV |
445 | const int ratio = rwcfg->mem_if_read_dqs_width / |
446 | rwcfg->mem_if_write_dqs_width; | |
5be355c1 MV |
447 | const int base = write_group * ratio; |
448 | int i; | |
3da42859 DN |
449 | /* |
450 | * Load the setting in the SCC manager | |
451 | * Although OCT affects only write data, the OCT delay is controlled | |
452 | * by the DQS logic block which is instantiated once per read group. | |
453 | * For protocols where a write group consists of multiple read groups, | |
454 | * the setting must be set multiple times. | |
455 | */ | |
5be355c1 MV |
456 | for (i = 0; i < ratio; i++) |
457 | scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay); | |
3da42859 DN |
458 | } |
459 | ||
37a37ca7 MV |
460 | /** |
461 | * scc_mgr_set_hhp_extras() - Set HHP extras. | |
462 | * | |
463 | * Load the fixed setting in the SCC manager HHP extras. | |
464 | */ | |
3da42859 DN |
465 | static void scc_mgr_set_hhp_extras(void) |
466 | { | |
467 | /* | |
468 | * Load the fixed setting in the SCC manager | |
37a37ca7 MV |
469 | * bits: 0:0 = 1'b1 - DQS bypass |
470 | * bits: 1:1 = 1'b1 - DQ bypass | |
471 | * bits: 4:2 = 3'b001 - rfifo_mode | |
472 | * bits: 6:5 = 2'b01 - rfifo clock_select | |
473 | * bits: 7:7 = 1'b0 - separate gating from ungating setting | |
474 | * bits: 8:8 = 1'b0 - separate OE from Output delay setting | |
3da42859 | 475 | */ |
37a37ca7 MV |
476 | const u32 value = (0 << 8) | (0 << 7) | (1 << 5) | |
477 | (1 << 2) | (1 << 1) | (1 << 0); | |
478 | const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | | |
479 | SCC_MGR_HHP_GLOBALS_OFFSET | | |
480 | SCC_MGR_HHP_EXTRAS_OFFSET; | |
481 | ||
482 | debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", | |
483 | __func__, __LINE__); | |
484 | writel(value, addr); | |
485 | debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n", | |
486 | __func__, __LINE__); | |
3da42859 DN |
487 | } |
488 | ||
f42af35b MV |
489 | /** |
490 | * scc_mgr_zero_all() - Zero all DQS config | |
491 | * | |
492 | * Zero all DQS config. | |
3da42859 DN |
493 | */ |
494 | static void scc_mgr_zero_all(void) | |
495 | { | |
f42af35b | 496 | int i, r; |
3da42859 DN |
497 | |
498 | /* | |
499 | * USER Zero all DQS config settings, across all groups and all | |
500 | * shadow registers | |
501 | */ | |
1fa0c8c4 | 502 | for (r = 0; r < rwcfg->mem_number_of_ranks; |
f42af35b | 503 | r += NUM_RANKS_PER_SHADOW_REG) { |
1fa0c8c4 | 504 | for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { |
3da42859 DN |
505 | /* |
506 | * The phases actually don't exist on a per-rank basis, | |
507 | * but there's no harm updating them several times, so | |
508 | * let's keep the code simple. | |
509 | */ | |
160695d8 | 510 | scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve); |
3da42859 DN |
511 | scc_mgr_set_dqs_en_phase(i, 0); |
512 | scc_mgr_set_dqs_en_delay(i, 0); | |
513 | } | |
514 | ||
1fa0c8c4 | 515 | for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { |
3da42859 | 516 | scc_mgr_set_dqdqs_output_phase(i, 0); |
f42af35b | 517 | /* Arria V/Cyclone V don't have out2. */ |
160695d8 | 518 | scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve); |
3da42859 DN |
519 | } |
520 | } | |
521 | ||
f42af35b | 522 | /* Multicast to all DQS group enables. */ |
1273dd9e MV |
523 | writel(0xff, &sdr_scc_mgr->dqs_ena); |
524 | writel(0, &sdr_scc_mgr->update); | |
3da42859 DN |
525 | } |
526 | ||
c5c5f537 MV |
527 | /** |
528 | * scc_set_bypass_mode() - Set bypass mode and trigger SCC update | |
529 | * @write_group: Write group | |
530 | * | |
531 | * Set bypass mode and trigger SCC update. | |
532 | */ | |
533 | static void scc_set_bypass_mode(const u32 write_group) | |
3da42859 | 534 | { |
c5c5f537 | 535 | /* Multicast to all DQ enables. */ |
1273dd9e MV |
536 | writel(0xff, &sdr_scc_mgr->dq_ena); |
537 | writel(0xff, &sdr_scc_mgr->dm_ena); | |
3da42859 | 538 | |
c5c5f537 | 539 | /* Update current DQS IO enable. */ |
1273dd9e | 540 | writel(0, &sdr_scc_mgr->dqs_io_ena); |
3da42859 | 541 | |
c5c5f537 | 542 | /* Update the DQS logic. */ |
1273dd9e | 543 | writel(write_group, &sdr_scc_mgr->dqs_ena); |
3da42859 | 544 | |
c5c5f537 | 545 | /* Hit update. */ |
1273dd9e | 546 | writel(0, &sdr_scc_mgr->update); |
3da42859 DN |
547 | } |
548 | ||
5e837896 MV |
549 | /** |
550 | * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group | |
551 | * @write_group: Write group | |
552 | * | |
553 | * Load DQS settings for Write Group, do not trigger SCC update. | |
554 | */ | |
555 | static void scc_mgr_load_dqs_for_write_group(const u32 write_group) | |
5ff825b8 | 556 | { |
1fa0c8c4 MV |
557 | const int ratio = rwcfg->mem_if_read_dqs_width / |
558 | rwcfg->mem_if_write_dqs_width; | |
5e837896 MV |
559 | const int base = write_group * ratio; |
560 | int i; | |
5ff825b8 | 561 | /* |
5e837896 | 562 | * Load the setting in the SCC manager |
5ff825b8 MV |
563 | * Although OCT affects only write data, the OCT delay is controlled |
564 | * by the DQS logic block which is instantiated once per read group. | |
565 | * For protocols where a write group consists of multiple read groups, | |
5e837896 | 566 | * the setting must be set multiple times. |
5ff825b8 | 567 | */ |
5e837896 MV |
568 | for (i = 0; i < ratio; i++) |
569 | writel(base + i, &sdr_scc_mgr->dqs_ena); | |
5ff825b8 MV |
570 | } |
571 | ||
d41ea93a MV |
572 | /** |
573 | * scc_mgr_zero_group() - Zero all configs for a group | |
574 | * | |
575 | * Zero DQ, DM, DQS and OCT configs for a group. | |
576 | */ | |
577 | static void scc_mgr_zero_group(const u32 write_group, const int out_only) | |
3da42859 | 578 | { |
d41ea93a | 579 | int i, r; |
3da42859 | 580 | |
1fa0c8c4 | 581 | for (r = 0; r < rwcfg->mem_number_of_ranks; |
d41ea93a MV |
582 | r += NUM_RANKS_PER_SHADOW_REG) { |
583 | /* Zero all DQ config settings. */ | |
1fa0c8c4 | 584 | for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { |
07aee5bd | 585 | scc_mgr_set_dq_out1_delay(i, 0); |
3da42859 | 586 | if (!out_only) |
07aee5bd | 587 | scc_mgr_set_dq_in_delay(i, 0); |
3da42859 DN |
588 | } |
589 | ||
d41ea93a | 590 | /* Multicast to all DQ enables. */ |
1273dd9e | 591 | writel(0xff, &sdr_scc_mgr->dq_ena); |
3da42859 | 592 | |
d41ea93a | 593 | /* Zero all DM config settings. */ |
70ed80af MV |
594 | for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { |
595 | if (!out_only) | |
596 | scc_mgr_set_dm_in_delay(i, 0); | |
07aee5bd | 597 | scc_mgr_set_dm_out1_delay(i, 0); |
70ed80af | 598 | } |
3da42859 | 599 | |
d41ea93a | 600 | /* Multicast to all DM enables. */ |
1273dd9e | 601 | writel(0xff, &sdr_scc_mgr->dm_ena); |
3da42859 | 602 | |
d41ea93a | 603 | /* Zero all DQS IO settings. */ |
3da42859 | 604 | if (!out_only) |
32675249 | 605 | scc_mgr_set_dqs_io_in_delay(0); |
d41ea93a MV |
606 | |
607 | /* Arria V/Cyclone V don't have out2. */ | |
160695d8 MV |
608 | scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve); |
609 | scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve); | |
3da42859 DN |
610 | scc_mgr_load_dqs_for_write_group(write_group); |
611 | ||
d41ea93a | 612 | /* Multicast to all DQS IO enables (only 1 in total). */ |
1273dd9e | 613 | writel(0, &sdr_scc_mgr->dqs_io_ena); |
3da42859 | 614 | |
d41ea93a | 615 | /* Hit update to zero everything. */ |
1273dd9e | 616 | writel(0, &sdr_scc_mgr->update); |
3da42859 DN |
617 | } |
618 | } | |
619 | ||
3da42859 DN |
620 | /* |
621 | * apply and load a particular input delay for the DQ pins in a group | |
622 | * group_bgn is the index of the first dq pin (in the write group) | |
623 | */ | |
5ded7320 | 624 | static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay) |
3da42859 | 625 | { |
5ded7320 | 626 | u32 i, p; |
3da42859 | 627 | |
1fa0c8c4 | 628 | for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) { |
07aee5bd | 629 | scc_mgr_set_dq_in_delay(p, delay); |
3da42859 DN |
630 | scc_mgr_load_dq(p); |
631 | } | |
632 | } | |
633 | ||
300c2e62 MV |
634 | /** |
635 | * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group | |
636 | * @delay: Delay value | |
637 | * | |
638 | * Apply and load a particular output delay for the DQ pins in a group. | |
639 | */ | |
640 | static void scc_mgr_apply_group_dq_out1_delay(const u32 delay) | |
3da42859 | 641 | { |
300c2e62 | 642 | int i; |
3da42859 | 643 | |
1fa0c8c4 | 644 | for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { |
300c2e62 | 645 | scc_mgr_set_dq_out1_delay(i, delay); |
3da42859 DN |
646 | scc_mgr_load_dq(i); |
647 | } | |
648 | } | |
649 | ||
650 | /* apply and load a particular output delay for the DM pins in a group */ | |
5ded7320 | 651 | static void scc_mgr_apply_group_dm_out1_delay(u32 delay1) |
3da42859 | 652 | { |
5ded7320 | 653 | u32 i; |
3da42859 DN |
654 | |
655 | for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { | |
07aee5bd | 656 | scc_mgr_set_dm_out1_delay(i, delay1); |
3da42859 DN |
657 | scc_mgr_load_dm(i); |
658 | } | |
659 | } | |
660 | ||
661 | ||
662 | /* apply and load delay on both DQS and OCT out1 */ | |
5ded7320 MV |
663 | static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group, |
664 | u32 delay) | |
3da42859 | 665 | { |
32675249 | 666 | scc_mgr_set_dqs_out1_delay(delay); |
3da42859 DN |
667 | scc_mgr_load_dqs_io(); |
668 | ||
669 | scc_mgr_set_oct_out1_delay(write_group, delay); | |
670 | scc_mgr_load_dqs_for_write_group(write_group); | |
671 | } | |
672 | ||
5cb1b508 MV |
673 | /** |
674 | * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT | |
675 | * @write_group: Write group | |
676 | * @delay: Delay value | |
677 | * | |
678 | * Apply a delay to the entire output side: DQ, DM, DQS, OCT. | |
679 | */ | |
8eccde3e | 680 | static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group, |
8eccde3e MV |
681 | const u32 delay) |
682 | { | |
683 | u32 i, new_delay; | |
3da42859 | 684 | |
8eccde3e | 685 | /* DQ shift */ |
1fa0c8c4 | 686 | for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) |
3da42859 | 687 | scc_mgr_load_dq(i); |
3da42859 | 688 | |
8eccde3e MV |
689 | /* DM shift */ |
690 | for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) | |
3da42859 | 691 | scc_mgr_load_dm(i); |
3da42859 | 692 | |
5cb1b508 MV |
693 | /* DQS shift */ |
694 | new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay; | |
160695d8 | 695 | if (new_delay > iocfg->io_out2_delay_max) { |
5cb1b508 MV |
696 | debug_cond(DLEVEL == 1, |
697 | "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n", | |
698 | __func__, __LINE__, write_group, delay, new_delay, | |
160695d8 MV |
699 | iocfg->io_out2_delay_max, |
700 | new_delay - iocfg->io_out2_delay_max); | |
701 | new_delay -= iocfg->io_out2_delay_max; | |
5cb1b508 | 702 | scc_mgr_set_dqs_out1_delay(new_delay); |
3da42859 DN |
703 | } |
704 | ||
705 | scc_mgr_load_dqs_io(); | |
706 | ||
5cb1b508 MV |
707 | /* OCT shift */ |
708 | new_delay = READ_SCC_OCT_OUT2_DELAY + delay; | |
160695d8 | 709 | if (new_delay > iocfg->io_out2_delay_max) { |
5cb1b508 MV |
710 | debug_cond(DLEVEL == 1, |
711 | "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n", | |
712 | __func__, __LINE__, write_group, delay, | |
160695d8 MV |
713 | new_delay, iocfg->io_out2_delay_max, |
714 | new_delay - iocfg->io_out2_delay_max); | |
715 | new_delay -= iocfg->io_out2_delay_max; | |
5cb1b508 | 716 | scc_mgr_set_oct_out1_delay(write_group, new_delay); |
3da42859 DN |
717 | } |
718 | ||
719 | scc_mgr_load_dqs_for_write_group(write_group); | |
720 | } | |
721 | ||
f51a7d35 MV |
722 | /** |
723 | * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks | |
724 | * @write_group: Write group | |
725 | * @delay: Delay value | |
726 | * | |
727 | * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks. | |
3da42859 | 728 | */ |
f51a7d35 MV |
729 | static void |
730 | scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group, | |
731 | const u32 delay) | |
3da42859 | 732 | { |
f51a7d35 | 733 | int r; |
3da42859 | 734 | |
1fa0c8c4 | 735 | for (r = 0; r < rwcfg->mem_number_of_ranks; |
f51a7d35 | 736 | r += NUM_RANKS_PER_SHADOW_REG) { |
5cb1b508 | 737 | scc_mgr_apply_group_all_out_delay_add(write_group, delay); |
1273dd9e | 738 | writel(0, &sdr_scc_mgr->update); |
3da42859 DN |
739 | } |
740 | } | |
741 | ||
f936f94f MV |
742 | /** |
743 | * set_jump_as_return() - Return instruction optimization | |
744 | * | |
745 | * Optimization used to recover some slots in ddr3 inst_rom could be | |
746 | * applied to other protocols if we wanted to | |
747 | */ | |
3da42859 DN |
748 | static void set_jump_as_return(void) |
749 | { | |
3da42859 | 750 | /* |
f936f94f | 751 | * To save space, we replace return with jump to special shared |
3da42859 | 752 | * RETURN instruction so we set the counter to large value so that |
f936f94f | 753 | * we always jump. |
3da42859 | 754 | */ |
1273dd9e | 755 | writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0); |
1fa0c8c4 | 756 | writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0); |
3da42859 DN |
757 | } |
758 | ||
3de9622e MV |
759 | /** |
760 | * delay_for_n_mem_clocks() - Delay for N memory clocks | |
761 | * @clocks: Length of the delay | |
762 | * | |
763 | * Delay for N memory clocks. | |
3da42859 | 764 | */ |
90a584b7 | 765 | static void delay_for_n_mem_clocks(const u32 clocks) |
3da42859 | 766 | { |
90a584b7 | 767 | u32 afi_clocks; |
6a39be6c MV |
768 | u16 c_loop; |
769 | u8 inner; | |
770 | u8 outer; | |
3da42859 DN |
771 | |
772 | debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks); | |
773 | ||
cbcaf460 | 774 | /* Scale (rounding up) to get afi clocks. */ |
96fd4362 | 775 | afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio); |
cbcaf460 MV |
776 | if (afi_clocks) /* Temporary underflow protection */ |
777 | afi_clocks--; | |
3da42859 DN |
778 | |
779 | /* | |
90a584b7 MV |
780 | * Note, we don't bother accounting for being off a little |
781 | * bit because of a few extra instructions in outer loops. | |
782 | * Note, the loops have a test at the end, and do the test | |
783 | * before the decrement, and so always perform the loop | |
3da42859 DN |
784 | * 1 time more than the counter value |
785 | */ | |
6a39be6c MV |
786 | c_loop = afi_clocks >> 16; |
787 | outer = c_loop ? 0xff : (afi_clocks >> 8); | |
788 | inner = outer ? 0xff : afi_clocks; | |
3da42859 DN |
789 | |
790 | /* | |
791 | * rom instructions are structured as follows: | |
792 | * | |
793 | * IDLE_LOOP2: jnz cntr0, TARGET_A | |
794 | * IDLE_LOOP1: jnz cntr1, TARGET_B | |
795 | * return | |
796 | * | |
797 | * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and | |
798 | * TARGET_B is set to IDLE_LOOP2 as well | |
799 | * | |
800 | * if we have no outer loop, though, then we can use IDLE_LOOP1 only, | |
801 | * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely | |
802 | * | |
803 | * a little confusing, but it helps save precious space in the inst_rom | |
804 | * and sequencer rom and keeps the delays more accurate and reduces | |
805 | * overhead | |
806 | */ | |
cbcaf460 | 807 | if (afi_clocks < 0x100) { |
1273dd9e | 808 | writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), |
139823ec | 809 | &sdr_rw_load_mgr_regs->load_cntr1); |
3da42859 | 810 | |
1fa0c8c4 | 811 | writel(rwcfg->idle_loop1, |
139823ec | 812 | &sdr_rw_load_jump_mgr_regs->load_jump_add1); |
3da42859 | 813 | |
1fa0c8c4 | 814 | writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | |
1273dd9e | 815 | RW_MGR_RUN_SINGLE_GROUP_OFFSET); |
3da42859 | 816 | } else { |
1273dd9e | 817 | writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), |
139823ec | 818 | &sdr_rw_load_mgr_regs->load_cntr0); |
3da42859 | 819 | |
1273dd9e | 820 | writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), |
139823ec | 821 | &sdr_rw_load_mgr_regs->load_cntr1); |
3da42859 | 822 | |
1fa0c8c4 | 823 | writel(rwcfg->idle_loop2, |
139823ec | 824 | &sdr_rw_load_jump_mgr_regs->load_jump_add0); |
3da42859 | 825 | |
1fa0c8c4 | 826 | writel(rwcfg->idle_loop2, |
139823ec | 827 | &sdr_rw_load_jump_mgr_regs->load_jump_add1); |
3da42859 | 828 | |
0c1b81bd | 829 | do { |
1fa0c8c4 | 830 | writel(rwcfg->idle_loop2, |
139823ec MV |
831 | SDR_PHYGRP_RWMGRGRP_ADDRESS | |
832 | RW_MGR_RUN_SINGLE_GROUP_OFFSET); | |
0c1b81bd | 833 | } while (c_loop-- != 0); |
3da42859 DN |
834 | } |
835 | debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks); | |
836 | } | |
837 | ||
944fe719 MV |
838 | /** |
839 | * rw_mgr_mem_init_load_regs() - Load instruction registers | |
840 | * @cntr0: Counter 0 value | |
841 | * @cntr1: Counter 1 value | |
842 | * @cntr2: Counter 2 value | |
843 | * @jump: Jump instruction value | |
844 | * | |
845 | * Load instruction registers. | |
846 | */ | |
847 | static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) | |
848 | { | |
5ded7320 | 849 | u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | |
944fe719 MV |
850 | RW_MGR_RUN_SINGLE_GROUP_OFFSET; |
851 | ||
852 | /* Load counters */ | |
853 | writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0), | |
854 | &sdr_rw_load_mgr_regs->load_cntr0); | |
855 | writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1), | |
856 | &sdr_rw_load_mgr_regs->load_cntr1); | |
857 | writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2), | |
858 | &sdr_rw_load_mgr_regs->load_cntr2); | |
859 | ||
860 | /* Load jump address */ | |
861 | writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0); | |
862 | writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1); | |
863 | writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2); | |
864 | ||
865 | /* Execute count instruction */ | |
866 | writel(jump, grpaddr); | |
867 | } | |
868 | ||
ecd2334a MV |
869 | /** |
870 | * rw_mgr_mem_load_user() - Load user calibration values | |
871 | * @fin1: Final instruction 1 | |
872 | * @fin2: Final instruction 2 | |
873 | * @precharge: If 1, precharge the banks at the end | |
874 | * | |
875 | * Load user calibration values and optionally precharge the banks. | |
876 | */ | |
877 | static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2, | |
878 | const int precharge) | |
3da42859 | 879 | { |
ecd2334a MV |
880 | u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | |
881 | RW_MGR_RUN_SINGLE_GROUP_OFFSET; | |
882 | u32 r; | |
883 | ||
1fa0c8c4 | 884 | for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { |
ecd2334a MV |
885 | /* set rank */ |
886 | set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); | |
887 | ||
888 | /* precharge all banks ... */ | |
889 | if (precharge) | |
1fa0c8c4 | 890 | writel(rwcfg->precharge_all, grpaddr); |
3da42859 | 891 | |
ecd2334a MV |
892 | /* |
893 | * USER Use Mirror-ed commands for odd ranks if address | |
894 | * mirrorring is on | |
895 | */ | |
1fa0c8c4 | 896 | if ((rwcfg->mem_address_mirroring >> r) & 0x1) { |
ecd2334a | 897 | set_jump_as_return(); |
1fa0c8c4 | 898 | writel(rwcfg->mrs2_mirr, grpaddr); |
ecd2334a MV |
899 | delay_for_n_mem_clocks(4); |
900 | set_jump_as_return(); | |
1fa0c8c4 | 901 | writel(rwcfg->mrs3_mirr, grpaddr); |
ecd2334a MV |
902 | delay_for_n_mem_clocks(4); |
903 | set_jump_as_return(); | |
1fa0c8c4 | 904 | writel(rwcfg->mrs1_mirr, grpaddr); |
ecd2334a MV |
905 | delay_for_n_mem_clocks(4); |
906 | set_jump_as_return(); | |
907 | writel(fin1, grpaddr); | |
908 | } else { | |
909 | set_jump_as_return(); | |
1fa0c8c4 | 910 | writel(rwcfg->mrs2, grpaddr); |
ecd2334a MV |
911 | delay_for_n_mem_clocks(4); |
912 | set_jump_as_return(); | |
1fa0c8c4 | 913 | writel(rwcfg->mrs3, grpaddr); |
ecd2334a MV |
914 | delay_for_n_mem_clocks(4); |
915 | set_jump_as_return(); | |
1fa0c8c4 | 916 | writel(rwcfg->mrs1, grpaddr); |
ecd2334a MV |
917 | set_jump_as_return(); |
918 | writel(fin2, grpaddr); | |
919 | } | |
920 | ||
921 | if (precharge) | |
922 | continue; | |
923 | ||
924 | set_jump_as_return(); | |
1fa0c8c4 | 925 | writel(rwcfg->zqcl, grpaddr); |
ecd2334a MV |
926 | |
927 | /* tZQinit = tDLLK = 512 ck cycles */ | |
928 | delay_for_n_mem_clocks(512); | |
929 | } | |
930 | } | |
931 | ||
8e9d7d04 MV |
932 | /** |
933 | * rw_mgr_mem_initialize() - Initialize RW Manager | |
934 | * | |
935 | * Initialize RW Manager. | |
936 | */ | |
ecd2334a MV |
937 | static void rw_mgr_mem_initialize(void) |
938 | { | |
3da42859 DN |
939 | debug("%s:%d\n", __func__, __LINE__); |
940 | ||
941 | /* The reset / cke part of initialization is broadcasted to all ranks */ | |
1273dd9e MV |
942 | writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS | |
943 | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET); | |
3da42859 DN |
944 | |
945 | /* | |
946 | * Here's how you load register for a loop | |
947 | * Counters are located @ 0x800 | |
948 | * Jump address are located @ 0xC00 | |
949 | * For both, registers 0 to 3 are selected using bits 3 and 2, like | |
950 | * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C | |
951 | * I know this ain't pretty, but Avalon bus throws away the 2 least | |
952 | * significant bits | |
953 | */ | |
954 | ||
8e9d7d04 | 955 | /* Start with memory RESET activated */ |
3da42859 DN |
956 | |
957 | /* tINIT = 200us */ | |
958 | ||
959 | /* | |
960 | * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles | |
961 | * If a and b are the number of iteration in 2 nested loops | |
962 | * it takes the following number of cycles to complete the operation: | |
963 | * number_of_cycles = ((2 + n) * a + 2) * b | |
964 | * where n is the number of instruction in the inner loop | |
965 | * One possible solution is n = 0 , a = 256 , b = 106 => a = FF, | |
966 | * b = 6A | |
967 | */ | |
139823ec MV |
968 | rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, |
969 | misccfg->tinit_cntr1_val, | |
96fd4362 | 970 | misccfg->tinit_cntr2_val, |
1fa0c8c4 | 971 | rwcfg->init_reset_0_cke_0); |
3da42859 | 972 | |
8e9d7d04 | 973 | /* Indicate that memory is stable. */ |
1273dd9e | 974 | writel(1, &phy_mgr_cfg->reset_mem_stbl); |
3da42859 DN |
975 | |
976 | /* | |
977 | * transition the RESET to high | |
978 | * Wait for 500us | |
979 | */ | |
980 | ||
981 | /* | |
982 | * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles | |
983 | * If a and b are the number of iteration in 2 nested loops | |
984 | * it takes the following number of cycles to complete the operation | |
985 | * number_of_cycles = ((2 + n) * a + 2) * b | |
986 | * where n is the number of instruction in the inner loop | |
987 | * One possible solution is n = 2 , a = 131 , b = 256 => a = 83, | |
988 | * b = FF | |
989 | */ | |
139823ec MV |
990 | rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, |
991 | misccfg->treset_cntr1_val, | |
96fd4362 | 992 | misccfg->treset_cntr2_val, |
1fa0c8c4 | 993 | rwcfg->init_reset_1_cke_0); |
3da42859 | 994 | |
8e9d7d04 | 995 | /* Bring up clock enable. */ |
3da42859 DN |
996 | |
997 | /* tXRP < 250 ck cycles */ | |
998 | delay_for_n_mem_clocks(250); | |
999 | ||
1fa0c8c4 | 1000 | rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset, |
ecd2334a | 1001 | 0); |
3da42859 DN |
1002 | } |
1003 | ||
f1f22f72 MV |
1004 | /** |
1005 | * rw_mgr_mem_handoff() - Hand off the memory to user | |
1006 | * | |
1007 | * At the end of calibration we have to program the user settings in | |
1008 | * and hand off the memory to the user. | |
3da42859 DN |
1009 | */ |
1010 | static void rw_mgr_mem_handoff(void) | |
1011 | { | |
1fa0c8c4 | 1012 | rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1); |
ecd2334a | 1013 | /* |
f1f22f72 MV |
1014 | * Need to wait tMOD (12CK or 15ns) time before issuing other |
1015 | * commands, but we will have plenty of NIOS cycles before actual | |
1016 | * handoff so its okay. | |
ecd2334a | 1017 | */ |
3da42859 DN |
1018 | } |
1019 | ||
8371c2ee MV |
1020 | /** |
1021 | * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command | |
1022 | * @group: Write Group | |
1023 | * @use_dm: Use DM | |
1024 | * | |
1025 | * Issue write test command. Two variants are provided, one that just tests | |
1026 | * a write pattern and another that tests datamask functionality. | |
ad64769c | 1027 | */ |
8371c2ee MV |
1028 | static void rw_mgr_mem_calibrate_write_test_issue(u32 group, |
1029 | u32 test_dm) | |
ad64769c | 1030 | { |
8371c2ee MV |
1031 | const u32 quick_write_mode = |
1032 | (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) && | |
96fd4362 | 1033 | misccfg->enable_super_quick_calibration; |
8371c2ee MV |
1034 | u32 mcc_instruction; |
1035 | u32 rw_wl_nop_cycles; | |
ad64769c MV |
1036 | |
1037 | /* | |
1038 | * Set counter and jump addresses for the right | |
1039 | * number of NOP cycles. | |
1040 | * The number of supported NOP cycles can range from -1 to infinity | |
1041 | * Three different cases are handled: | |
1042 | * | |
1043 | * 1. For a number of NOP cycles greater than 0, the RW Mgr looping | |
1044 | * mechanism will be used to insert the right number of NOPs | |
1045 | * | |
1046 | * 2. For a number of NOP cycles equals to 0, the micro-instruction | |
1047 | * issuing the write command will jump straight to the | |
1048 | * micro-instruction that turns on DQS (for DDRx), or outputs write | |
1049 | * data (for RLD), skipping | |
1050 | * the NOP micro-instruction all together | |
1051 | * | |
1052 | * 3. A number of NOP cycles equal to -1 indicates that DQS must be | |
1053 | * turned on in the same micro-instruction that issues the write | |
1054 | * command. Then we need | |
1055 | * to directly jump to the micro-instruction that sends out the data | |
1056 | * | |
1057 | * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters | |
1058 | * (2 and 3). One jump-counter (0) is used to perform multiple | |
1059 | * write-read operations. | |
1060 | * one counter left to issue this command in "multiple-group" mode | |
1061 | */ | |
1062 | ||
1063 | rw_wl_nop_cycles = gbl->rw_wl_nop_cycles; | |
1064 | ||
1065 | if (rw_wl_nop_cycles == -1) { | |
1066 | /* | |
1067 | * CNTR 2 - We want to execute the special write operation that | |
1068 | * turns on DQS right away and then skip directly to the | |
1069 | * instruction that sends out the data. We set the counter to a | |
1070 | * large number so that the jump is always taken. | |
1071 | */ | |
1072 | writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2); | |
1073 | ||
1074 | /* CNTR 3 - Not used */ | |
1075 | if (test_dm) { | |
1fa0c8c4 MV |
1076 | mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; |
1077 | writel(rwcfg->lfsr_wr_rd_dm_bank_0_data, | |
ad64769c | 1078 | &sdr_rw_load_jump_mgr_regs->load_jump_add2); |
1fa0c8c4 | 1079 | writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, |
ad64769c MV |
1080 | &sdr_rw_load_jump_mgr_regs->load_jump_add3); |
1081 | } else { | |
1fa0c8c4 MV |
1082 | mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1; |
1083 | writel(rwcfg->lfsr_wr_rd_bank_0_data, | |
139823ec | 1084 | &sdr_rw_load_jump_mgr_regs->load_jump_add2); |
1fa0c8c4 | 1085 | writel(rwcfg->lfsr_wr_rd_bank_0_nop, |
139823ec | 1086 | &sdr_rw_load_jump_mgr_regs->load_jump_add3); |
ad64769c MV |
1087 | } |
1088 | } else if (rw_wl_nop_cycles == 0) { | |
1089 | /* | |
1090 | * CNTR 2 - We want to skip the NOP operation and go straight | |
1091 | * to the DQS enable instruction. We set the counter to a large | |
1092 | * number so that the jump is always taken. | |
1093 | */ | |
1094 | writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2); | |
1095 | ||
1096 | /* CNTR 3 - Not used */ | |
1097 | if (test_dm) { | |
1fa0c8c4 MV |
1098 | mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; |
1099 | writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs, | |
ad64769c MV |
1100 | &sdr_rw_load_jump_mgr_regs->load_jump_add2); |
1101 | } else { | |
1fa0c8c4 MV |
1102 | mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; |
1103 | writel(rwcfg->lfsr_wr_rd_bank_0_dqs, | |
139823ec | 1104 | &sdr_rw_load_jump_mgr_regs->load_jump_add2); |
ad64769c MV |
1105 | } |
1106 | } else { | |
1107 | /* | |
1108 | * CNTR 2 - In this case we want to execute the next instruction | |
1109 | * and NOT take the jump. So we set the counter to 0. The jump | |
1110 | * address doesn't count. | |
1111 | */ | |
1112 | writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2); | |
1113 | writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2); | |
1114 | ||
1115 | /* | |
1116 | * CNTR 3 - Set the nop counter to the number of cycles we | |
1117 | * need to loop for, minus 1. | |
1118 | */ | |
1119 | writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3); | |
1120 | if (test_dm) { | |
1fa0c8c4 MV |
1121 | mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; |
1122 | writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, | |
139823ec | 1123 | &sdr_rw_load_jump_mgr_regs->load_jump_add3); |
ad64769c | 1124 | } else { |
1fa0c8c4 MV |
1125 | mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; |
1126 | writel(rwcfg->lfsr_wr_rd_bank_0_nop, | |
139823ec | 1127 | &sdr_rw_load_jump_mgr_regs->load_jump_add3); |
ad64769c MV |
1128 | } |
1129 | } | |
1130 | ||
1131 | writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | | |
1132 | RW_MGR_RESET_READ_DATAPATH_OFFSET); | |
1133 | ||
1134 | if (quick_write_mode) | |
1135 | writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0); | |
1136 | else | |
1137 | writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0); | |
1138 | ||
1139 | writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0); | |
1140 | ||
1141 | /* | |
1142 | * CNTR 1 - This is used to ensure enough time elapses | |
1143 | * for read data to come back. | |
1144 | */ | |
1145 | writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1); | |
1146 | ||
1147 | if (test_dm) { | |
1fa0c8c4 | 1148 | writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait, |
139823ec | 1149 | &sdr_rw_load_jump_mgr_regs->load_jump_add1); |
ad64769c | 1150 | } else { |
1fa0c8c4 | 1151 | writel(rwcfg->lfsr_wr_rd_bank_0_wait, |
139823ec | 1152 | &sdr_rw_load_jump_mgr_regs->load_jump_add1); |
ad64769c MV |
1153 | } |
1154 | ||
8371c2ee MV |
1155 | writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS | |
1156 | RW_MGR_RUN_SINGLE_GROUP_OFFSET) + | |
1157 | (group << 2)); | |
ad64769c MV |
1158 | } |
1159 | ||
4a82854b MV |
1160 | /** |
1161 | * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass | |
1162 | * @rank_bgn: Rank number | |
1163 | * @write_group: Write Group | |
1164 | * @use_dm: Use DM | |
1165 | * @all_correct: All bits must be correct in the mask | |
1166 | * @bit_chk: Resulting bit mask after the test | |
1167 | * @all_ranks: Test all ranks | |
1168 | * | |
1169 | * Test writes, can check for a single bit pass or multiple bit pass. | |
1170 | */ | |
b9452ea0 MV |
1171 | static int |
1172 | rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group, | |
1173 | const u32 use_dm, const u32 all_correct, | |
1174 | u32 *bit_chk, const u32 all_ranks) | |
ad64769c | 1175 | { |
b9452ea0 | 1176 | const u32 rank_end = all_ranks ? |
1fa0c8c4 | 1177 | rwcfg->mem_number_of_ranks : |
b9452ea0 | 1178 | (rank_bgn + NUM_RANKS_PER_SHADOW_REG); |
1fa0c8c4 MV |
1179 | const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs / |
1180 | rwcfg->mem_virtual_groups_per_write_dqs; | |
b9452ea0 MV |
1181 | const u32 correct_mask_vg = param->write_correct_mask_vg; |
1182 | ||
1183 | u32 tmp_bit_chk, base_rw_mgr; | |
1184 | int vg, r; | |
ad64769c MV |
1185 | |
1186 | *bit_chk = param->write_correct_mask; | |
ad64769c MV |
1187 | |
1188 | for (r = rank_bgn; r < rank_end; r++) { | |
b9452ea0 | 1189 | /* Set rank */ |
ad64769c MV |
1190 | set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); |
1191 | ||
1192 | tmp_bit_chk = 0; | |
1fa0c8c4 | 1193 | for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1; |
b9452ea0 MV |
1194 | vg >= 0; vg--) { |
1195 | /* Reset the FIFOs to get pointers to known state. */ | |
ad64769c MV |
1196 | writel(0, &phy_mgr_cmd->fifo_reset); |
1197 | ||
b9452ea0 MV |
1198 | rw_mgr_mem_calibrate_write_test_issue( |
1199 | write_group * | |
1fa0c8c4 | 1200 | rwcfg->mem_virtual_groups_per_write_dqs + vg, |
ad64769c MV |
1201 | use_dm); |
1202 | ||
b9452ea0 MV |
1203 | base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); |
1204 | tmp_bit_chk <<= shift_ratio; | |
1205 | tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr)); | |
ad64769c | 1206 | } |
b9452ea0 | 1207 | |
ad64769c MV |
1208 | *bit_chk &= tmp_bit_chk; |
1209 | } | |
1210 | ||
b9452ea0 | 1211 | set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); |
ad64769c | 1212 | if (all_correct) { |
b9452ea0 MV |
1213 | debug_cond(DLEVEL == 2, |
1214 | "write_test(%u,%u,ALL) : %u == %u => %i\n", | |
1215 | write_group, use_dm, *bit_chk, | |
1216 | param->write_correct_mask, | |
1217 | *bit_chk == param->write_correct_mask); | |
ad64769c MV |
1218 | return *bit_chk == param->write_correct_mask; |
1219 | } else { | |
b9452ea0 MV |
1220 | debug_cond(DLEVEL == 2, |
1221 | "write_test(%u,%u,ONE) : %u != %i => %i\n", | |
1222 | write_group, use_dm, *bit_chk, 0, *bit_chk != 0); | |
ad64769c MV |
1223 | return *bit_chk != 0x00; |
1224 | } | |
1225 | } | |
1226 | ||
d844c7d4 MV |
1227 | /** |
1228 | * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns | |
1229 | * @rank_bgn: Rank number | |
1230 | * @group: Read/Write Group | |
1231 | * @all_ranks: Test all ranks | |
1232 | * | |
1233 | * Performs a guaranteed read on the patterns we are going to use during a | |
1234 | * read test to ensure memory works. | |
3da42859 | 1235 | */ |
d844c7d4 MV |
1236 | static int |
1237 | rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group, | |
1238 | const u32 all_ranks) | |
3da42859 | 1239 | { |
d844c7d4 MV |
1240 | const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | |
1241 | RW_MGR_RUN_SINGLE_GROUP_OFFSET; | |
1242 | const u32 addr_offset = | |
1fa0c8c4 | 1243 | (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2; |
d844c7d4 | 1244 | const u32 rank_end = all_ranks ? |
1fa0c8c4 | 1245 | rwcfg->mem_number_of_ranks : |
d844c7d4 | 1246 | (rank_bgn + NUM_RANKS_PER_SHADOW_REG); |
1fa0c8c4 MV |
1247 | const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs / |
1248 | rwcfg->mem_virtual_groups_per_read_dqs; | |
d844c7d4 | 1249 | const u32 correct_mask_vg = param->read_correct_mask_vg; |
3da42859 | 1250 | |
d844c7d4 MV |
1251 | u32 tmp_bit_chk, base_rw_mgr, bit_chk; |
1252 | int vg, r; | |
1253 | int ret = 0; | |
1254 | ||
1255 | bit_chk = param->read_correct_mask; | |
3da42859 DN |
1256 | |
1257 | for (r = rank_bgn; r < rank_end; r++) { | |
d844c7d4 | 1258 | /* Set rank */ |
3da42859 DN |
1259 | set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); |
1260 | ||
1261 | /* Load up a constant bursts of read commands */ | |
1273dd9e | 1262 | writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); |
1fa0c8c4 | 1263 | writel(rwcfg->guaranteed_read, |
139823ec | 1264 | &sdr_rw_load_jump_mgr_regs->load_jump_add0); |
3da42859 | 1265 | |
1273dd9e | 1266 | writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); |
1fa0c8c4 | 1267 | writel(rwcfg->guaranteed_read_cont, |
139823ec | 1268 | &sdr_rw_load_jump_mgr_regs->load_jump_add1); |
3da42859 DN |
1269 | |
1270 | tmp_bit_chk = 0; | |
1fa0c8c4 | 1271 | for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; |
d844c7d4 MV |
1272 | vg >= 0; vg--) { |
1273 | /* Reset the FIFOs to get pointers to known state. */ | |
1273dd9e MV |
1274 | writel(0, &phy_mgr_cmd->fifo_reset); |
1275 | writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | | |
1276 | RW_MGR_RESET_READ_DATAPATH_OFFSET); | |
1fa0c8c4 | 1277 | writel(rwcfg->guaranteed_read, |
d844c7d4 | 1278 | addr + addr_offset + (vg << 2)); |
3da42859 | 1279 | |
1273dd9e | 1280 | base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); |
d844c7d4 MV |
1281 | tmp_bit_chk <<= shift_ratio; |
1282 | tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr; | |
3da42859 | 1283 | } |
d844c7d4 MV |
1284 | |
1285 | bit_chk &= tmp_bit_chk; | |
3da42859 DN |
1286 | } |
1287 | ||
1fa0c8c4 | 1288 | writel(rwcfg->clear_dqs_enable, addr + (group << 2)); |
3da42859 DN |
1289 | |
1290 | set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); | |
d844c7d4 MV |
1291 | |
1292 | if (bit_chk != param->read_correct_mask) | |
1293 | ret = -EIO; | |
1294 | ||
1295 | debug_cond(DLEVEL == 1, | |
1296 | "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n", | |
1297 | __func__, __LINE__, group, bit_chk, | |
1298 | param->read_correct_mask, ret); | |
1299 | ||
1300 | return ret; | |
3da42859 DN |
1301 | } |
1302 | ||
b6cb7f9e MV |
1303 | /** |
1304 | * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test | |
1305 | * @rank_bgn: Rank number | |
1306 | * @all_ranks: Test all ranks | |
1307 | * | |
1308 | * Load up the patterns we are going to use during a read test. | |
1309 | */ | |
1310 | static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, | |
1311 | const int all_ranks) | |
3da42859 | 1312 | { |
b6cb7f9e | 1313 | const u32 rank_end = all_ranks ? |
1fa0c8c4 | 1314 | rwcfg->mem_number_of_ranks : |
b6cb7f9e MV |
1315 | (rank_bgn + NUM_RANKS_PER_SHADOW_REG); |
1316 | u32 r; | |
3da42859 DN |
1317 | |
1318 | debug("%s:%d\n", __func__, __LINE__); | |
b6cb7f9e | 1319 | |
3da42859 | 1320 | for (r = rank_bgn; r < rank_end; r++) { |
3da42859 DN |
1321 | /* set rank */ |
1322 | set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); | |
1323 | ||
1324 | /* Load up a constant bursts */ | |
1273dd9e | 1325 | writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); |
3da42859 | 1326 | |
1fa0c8c4 | 1327 | writel(rwcfg->guaranteed_write_wait0, |
139823ec | 1328 | &sdr_rw_load_jump_mgr_regs->load_jump_add0); |
3da42859 | 1329 | |
1273dd9e | 1330 | writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); |
3da42859 | 1331 | |
1fa0c8c4 | 1332 | writel(rwcfg->guaranteed_write_wait1, |
139823ec | 1333 | &sdr_rw_load_jump_mgr_regs->load_jump_add1); |
3da42859 | 1334 | |
1273dd9e | 1335 | writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2); |
3da42859 | 1336 | |
1fa0c8c4 | 1337 | writel(rwcfg->guaranteed_write_wait2, |
139823ec | 1338 | &sdr_rw_load_jump_mgr_regs->load_jump_add2); |
3da42859 | 1339 | |
1273dd9e | 1340 | writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3); |
3da42859 | 1341 | |
1fa0c8c4 | 1342 | writel(rwcfg->guaranteed_write_wait3, |
139823ec | 1343 | &sdr_rw_load_jump_mgr_regs->load_jump_add3); |
3da42859 | 1344 | |
1fa0c8c4 | 1345 | writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS | |
1273dd9e | 1346 | RW_MGR_RUN_SINGLE_GROUP_OFFSET); |
3da42859 DN |
1347 | } |
1348 | ||
1349 | set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); | |
1350 | } | |
1351 | ||
783fcf59 MV |
1352 | /** |
1353 | * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank | |
1354 | * @rank_bgn: Rank number | |
1355 | * @group: Read/Write group | |
1356 | * @num_tries: Number of retries of the test | |
1357 | * @all_correct: All bits must be correct in the mask | |
1358 | * @bit_chk: Resulting bit mask after the test | |
1359 | * @all_groups: Test all R/W groups | |
1360 | * @all_ranks: Test all ranks | |
1361 | * | |
1362 | * Try a read and see if it returns correct data back. Test has dummy reads | |
1363 | * inserted into the mix used to align DQS enable. Test has more thorough | |
1364 | * checks than the regular read test. | |
3da42859 | 1365 | */ |
3cb8bf3f MV |
1366 | static int |
1367 | rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, | |
1368 | const u32 num_tries, const u32 all_correct, | |
1369 | u32 *bit_chk, | |
1370 | const u32 all_groups, const u32 all_ranks) | |
3da42859 | 1371 | { |
1fa0c8c4 | 1372 | const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks : |
3da42859 | 1373 | (rank_bgn + NUM_RANKS_PER_SHADOW_REG); |
3cb8bf3f MV |
1374 | const u32 quick_read_mode = |
1375 | ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) && | |
96fd4362 | 1376 | misccfg->enable_super_quick_calibration); |
3cb8bf3f MV |
1377 | u32 correct_mask_vg = param->read_correct_mask_vg; |
1378 | u32 tmp_bit_chk; | |
1379 | u32 base_rw_mgr; | |
1380 | u32 addr; | |
3da42859 | 1381 | |
3cb8bf3f | 1382 | int r, vg, ret; |
3853d65e | 1383 | |
3cb8bf3f | 1384 | *bit_chk = param->read_correct_mask; |
3da42859 DN |
1385 | |
1386 | for (r = rank_bgn; r < rank_end; r++) { | |
3da42859 DN |
1387 | /* set rank */ |
1388 | set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); | |
1389 | ||
1273dd9e | 1390 | writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1); |
3da42859 | 1391 | |
1fa0c8c4 | 1392 | writel(rwcfg->read_b2b_wait1, |
139823ec | 1393 | &sdr_rw_load_jump_mgr_regs->load_jump_add1); |
3da42859 | 1394 | |
1273dd9e | 1395 | writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2); |
1fa0c8c4 | 1396 | writel(rwcfg->read_b2b_wait2, |
139823ec | 1397 | &sdr_rw_load_jump_mgr_regs->load_jump_add2); |
3da42859 | 1398 | |
3da42859 | 1399 | if (quick_read_mode) |
1273dd9e | 1400 | writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0); |
3da42859 DN |
1401 | /* need at least two (1+1) reads to capture failures */ |
1402 | else if (all_groups) | |
1273dd9e | 1403 | writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0); |
3da42859 | 1404 | else |
1273dd9e | 1405 | writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0); |
3da42859 | 1406 | |
1fa0c8c4 | 1407 | writel(rwcfg->read_b2b, |
139823ec | 1408 | &sdr_rw_load_jump_mgr_regs->load_jump_add0); |
3da42859 | 1409 | if (all_groups) |
1fa0c8c4 MV |
1410 | writel(rwcfg->mem_if_read_dqs_width * |
1411 | rwcfg->mem_virtual_groups_per_read_dqs - 1, | |
1273dd9e | 1412 | &sdr_rw_load_mgr_regs->load_cntr3); |
3da42859 | 1413 | else |
1273dd9e | 1414 | writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3); |
3da42859 | 1415 | |
1fa0c8c4 | 1416 | writel(rwcfg->read_b2b, |
139823ec | 1417 | &sdr_rw_load_jump_mgr_regs->load_jump_add3); |
3da42859 DN |
1418 | |
1419 | tmp_bit_chk = 0; | |
1fa0c8c4 | 1420 | for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; |
7ce23bb6 | 1421 | vg--) { |
ba522c76 | 1422 | /* Reset the FIFOs to get pointers to known state. */ |
1273dd9e MV |
1423 | writel(0, &phy_mgr_cmd->fifo_reset); |
1424 | writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | | |
1425 | RW_MGR_RESET_READ_DATAPATH_OFFSET); | |
3da42859 | 1426 | |
ba522c76 MV |
1427 | if (all_groups) { |
1428 | addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | | |
1429 | RW_MGR_RUN_ALL_GROUPS_OFFSET; | |
1430 | } else { | |
1431 | addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | | |
1432 | RW_MGR_RUN_SINGLE_GROUP_OFFSET; | |
1433 | } | |
c4815f76 | 1434 | |
1fa0c8c4 | 1435 | writel(rwcfg->read_b2b, addr + |
139823ec MV |
1436 | ((group * |
1437 | rwcfg->mem_virtual_groups_per_read_dqs + | |
1438 | vg) << 2)); | |
3da42859 | 1439 | |
1273dd9e | 1440 | base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); |
1fa0c8c4 MV |
1441 | tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs / |
1442 | rwcfg->mem_virtual_groups_per_read_dqs; | |
ba522c76 | 1443 | tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr); |
3da42859 | 1444 | } |
7ce23bb6 | 1445 | |
3da42859 DN |
1446 | *bit_chk &= tmp_bit_chk; |
1447 | } | |
1448 | ||
c4815f76 | 1449 | addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; |
1fa0c8c4 | 1450 | writel(rwcfg->clear_dqs_enable, addr + (group << 2)); |
3da42859 | 1451 | |
3853d65e MV |
1452 | set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); |
1453 | ||
3da42859 | 1454 | if (all_correct) { |
3853d65e MV |
1455 | ret = (*bit_chk == param->read_correct_mask); |
1456 | debug_cond(DLEVEL == 2, | |
1457 | "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n", | |
1458 | __func__, __LINE__, group, all_groups, *bit_chk, | |
1459 | param->read_correct_mask, ret); | |
3da42859 | 1460 | } else { |
3853d65e MV |
1461 | ret = (*bit_chk != 0x00); |
1462 | debug_cond(DLEVEL == 2, | |
1463 | "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n", | |
1464 | __func__, __LINE__, group, all_groups, *bit_chk, | |
1465 | 0, ret); | |
3da42859 | 1466 | } |
3853d65e MV |
1467 | |
1468 | return ret; | |
3da42859 DN |
1469 | } |
1470 | ||
96df6036 MV |
1471 | /** |
1472 | * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks | |
1473 | * @grp: Read/Write group | |
1474 | * @num_tries: Number of retries of the test | |
1475 | * @all_correct: All bits must be correct in the mask | |
1476 | * @all_groups: Test all R/W groups | |
1477 | * | |
1478 | * Perform a READ test across all memory ranks. | |
1479 | */ | |
1480 | static int | |
1481 | rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries, | |
1482 | const u32 all_correct, | |
1483 | const u32 all_groups) | |
3da42859 | 1484 | { |
96df6036 MV |
1485 | u32 bit_chk; |
1486 | return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct, | |
1487 | &bit_chk, all_groups, 1); | |
3da42859 DN |
1488 | } |
1489 | ||
60bb8a8a MV |
1490 | /** |
1491 | * rw_mgr_incr_vfifo() - Increase VFIFO value | |
1492 | * @grp: Read/Write group | |
60bb8a8a MV |
1493 | * |
1494 | * Increase VFIFO value. | |
1495 | */ | |
8c887b6e | 1496 | static void rw_mgr_incr_vfifo(const u32 grp) |
3da42859 | 1497 | { |
1273dd9e | 1498 | writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy); |
3da42859 DN |
1499 | } |
1500 | ||
60bb8a8a MV |
1501 | /** |
1502 | * rw_mgr_decr_vfifo() - Decrease VFIFO value | |
1503 | * @grp: Read/Write group | |
60bb8a8a MV |
1504 | * |
1505 | * Decrease VFIFO value. | |
1506 | */ | |
8c887b6e | 1507 | static void rw_mgr_decr_vfifo(const u32 grp) |
3da42859 | 1508 | { |
60bb8a8a | 1509 | u32 i; |
3da42859 | 1510 | |
96fd4362 | 1511 | for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++) |
8c887b6e | 1512 | rw_mgr_incr_vfifo(grp); |
3da42859 DN |
1513 | } |
1514 | ||
d145ca9f MV |
1515 | /** |
1516 | * find_vfifo_failing_read() - Push VFIFO to get a failing read | |
1517 | * @grp: Read/Write group | |
1518 | * | |
1519 | * Push VFIFO until a failing read happens. | |
1520 | */ | |
1521 | static int find_vfifo_failing_read(const u32 grp) | |
3da42859 | 1522 | { |
96df6036 | 1523 | u32 v, ret, fail_cnt = 0; |
3da42859 | 1524 | |
96fd4362 | 1525 | for (v = 0; v < misccfg->read_valid_fifo_size; v++) { |
d145ca9f | 1526 | debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n", |
3da42859 | 1527 | __func__, __LINE__, v); |
d145ca9f | 1528 | ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, |
96df6036 | 1529 | PASS_ONE_BIT, 0); |
d145ca9f | 1530 | if (!ret) { |
3da42859 DN |
1531 | fail_cnt++; |
1532 | ||
1533 | if (fail_cnt == 2) | |
d145ca9f | 1534 | return v; |
3da42859 DN |
1535 | } |
1536 | ||
d145ca9f | 1537 | /* Fiddle with FIFO. */ |
8c887b6e | 1538 | rw_mgr_incr_vfifo(grp); |
3da42859 DN |
1539 | } |
1540 | ||
d145ca9f MV |
1541 | /* No failing read found! Something must have gone wrong. */ |
1542 | debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__); | |
1543 | return 0; | |
3da42859 DN |
1544 | } |
1545 | ||
52e8f217 MV |
1546 | /** |
1547 | * sdr_find_phase_delay() - Find DQS enable phase or delay | |
1548 | * @working: If 1, look for working phase/delay, if 0, look for non-working | |
1549 | * @delay: If 1, look for delay, if 0, look for phase | |
1550 | * @grp: Read/Write group | |
1551 | * @work: Working window position | |
1552 | * @work_inc: Working window increment | |
1553 | * @pd: DQS Phase/Delay Iterator | |
1554 | * | |
1555 | * Find working or non-working DQS enable phase setting. | |
1556 | */ | |
1557 | static int sdr_find_phase_delay(int working, int delay, const u32 grp, | |
1558 | u32 *work, const u32 work_inc, u32 *pd) | |
1559 | { | |
139823ec MV |
1560 | const u32 max = delay ? iocfg->dqs_en_delay_max : |
1561 | iocfg->dqs_en_phase_max; | |
96df6036 | 1562 | u32 ret; |
52e8f217 MV |
1563 | |
1564 | for (; *pd <= max; (*pd)++) { | |
1565 | if (delay) | |
1566 | scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd); | |
1567 | else | |
1568 | scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd); | |
1569 | ||
1570 | ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, | |
96df6036 | 1571 | PASS_ONE_BIT, 0); |
52e8f217 MV |
1572 | if (!working) |
1573 | ret = !ret; | |
1574 | ||
1575 | if (ret) | |
1576 | return 0; | |
1577 | ||
1578 | if (work) | |
1579 | *work += work_inc; | |
1580 | } | |
1581 | ||
1582 | return -EINVAL; | |
1583 | } | |
192d6f9f MV |
1584 | /** |
1585 | * sdr_find_phase() - Find DQS enable phase | |
1586 | * @working: If 1, look for working phase, if 0, look for non-working phase | |
1587 | * @grp: Read/Write group | |
192d6f9f MV |
1588 | * @work: Working window position |
1589 | * @i: Iterator | |
1590 | * @p: DQS Phase Iterator | |
192d6f9f MV |
1591 | * |
1592 | * Find working or non-working DQS enable phase setting. | |
1593 | */ | |
8c887b6e | 1594 | static int sdr_find_phase(int working, const u32 grp, u32 *work, |
86a39dc7 | 1595 | u32 *i, u32 *p) |
3da42859 | 1596 | { |
96fd4362 | 1597 | const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1); |
52e8f217 | 1598 | int ret; |
3da42859 | 1599 | |
192d6f9f MV |
1600 | for (; *i < end; (*i)++) { |
1601 | if (working) | |
1602 | *p = 0; | |
1603 | ||
52e8f217 | 1604 | ret = sdr_find_phase_delay(working, 0, grp, work, |
160695d8 | 1605 | iocfg->delay_per_opa_tap, p); |
52e8f217 MV |
1606 | if (!ret) |
1607 | return 0; | |
192d6f9f | 1608 | |
160695d8 | 1609 | if (*p > iocfg->dqs_en_phase_max) { |
192d6f9f | 1610 | /* Fiddle with FIFO. */ |
8c887b6e | 1611 | rw_mgr_incr_vfifo(grp); |
192d6f9f MV |
1612 | if (!working) |
1613 | *p = 0; | |
3da42859 | 1614 | } |
3da42859 DN |
1615 | } |
1616 | ||
192d6f9f MV |
1617 | return -EINVAL; |
1618 | } | |
1619 | ||
4c5e584b MV |
1620 | /** |
1621 | * sdr_working_phase() - Find working DQS enable phase | |
1622 | * @grp: Read/Write group | |
1623 | * @work_bgn: Working window start position | |
4c5e584b MV |
1624 | * @d: dtaps output value |
1625 | * @p: DQS Phase Iterator | |
1626 | * @i: Iterator | |
1627 | * | |
1628 | * Find working DQS enable phase setting. | |
1629 | */ | |
8c887b6e | 1630 | static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d, |
4c5e584b | 1631 | u32 *p, u32 *i) |
192d6f9f | 1632 | { |
160695d8 MV |
1633 | const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap / |
1634 | iocfg->delay_per_dqs_en_dchain_tap; | |
192d6f9f MV |
1635 | int ret; |
1636 | ||
1637 | *work_bgn = 0; | |
1638 | ||
1639 | for (*d = 0; *d <= dtaps_per_ptap; (*d)++) { | |
1640 | *i = 0; | |
1641 | scc_mgr_set_dqs_en_delay_all_ranks(grp, *d); | |
8c887b6e | 1642 | ret = sdr_find_phase(1, grp, work_bgn, i, p); |
192d6f9f MV |
1643 | if (!ret) |
1644 | return 0; | |
160695d8 | 1645 | *work_bgn += iocfg->delay_per_dqs_en_dchain_tap; |
192d6f9f MV |
1646 | } |
1647 | ||
38ed6922 | 1648 | /* Cannot find working solution */ |
192d6f9f MV |
1649 | debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n", |
1650 | __func__, __LINE__); | |
1651 | return -EINVAL; | |
3da42859 DN |
1652 | } |
1653 | ||
4c5e584b MV |
1654 | /** |
1655 | * sdr_backup_phase() - Find DQS enable backup phase | |
1656 | * @grp: Read/Write group | |
1657 | * @work_bgn: Working window start position | |
4c5e584b MV |
1658 | * @p: DQS Phase Iterator |
1659 | * | |
1660 | * Find DQS enable backup phase setting. | |
1661 | */ | |
8c887b6e | 1662 | static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p) |
3da42859 | 1663 | { |
96df6036 | 1664 | u32 tmp_delay, d; |
4c5e584b | 1665 | int ret; |
3da42859 DN |
1666 | |
1667 | /* Special case code for backing up a phase */ | |
1668 | if (*p == 0) { | |
160695d8 | 1669 | *p = iocfg->dqs_en_phase_max; |
8c887b6e | 1670 | rw_mgr_decr_vfifo(grp); |
3da42859 DN |
1671 | } else { |
1672 | (*p)--; | |
1673 | } | |
160695d8 | 1674 | tmp_delay = *work_bgn - iocfg->delay_per_opa_tap; |
521fe39c | 1675 | scc_mgr_set_dqs_en_phase_all_ranks(grp, *p); |
3da42859 | 1676 | |
139823ec MV |
1677 | for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; |
1678 | d++) { | |
49891df6 | 1679 | scc_mgr_set_dqs_en_delay_all_ranks(grp, d); |
3da42859 | 1680 | |
4c5e584b | 1681 | ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, |
96df6036 | 1682 | PASS_ONE_BIT, 0); |
4c5e584b | 1683 | if (ret) { |
3da42859 DN |
1684 | *work_bgn = tmp_delay; |
1685 | break; | |
1686 | } | |
49891df6 | 1687 | |
160695d8 | 1688 | tmp_delay += iocfg->delay_per_dqs_en_dchain_tap; |
3da42859 DN |
1689 | } |
1690 | ||
4c5e584b | 1691 | /* Restore VFIFO to old state before we decremented it (if needed). */ |
3da42859 | 1692 | (*p)++; |
160695d8 | 1693 | if (*p > iocfg->dqs_en_phase_max) { |
3da42859 | 1694 | *p = 0; |
8c887b6e | 1695 | rw_mgr_incr_vfifo(grp); |
3da42859 DN |
1696 | } |
1697 | ||
521fe39c | 1698 | scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); |
3da42859 DN |
1699 | } |
1700 | ||
4c5e584b MV |
1701 | /** |
1702 | * sdr_nonworking_phase() - Find non-working DQS enable phase | |
1703 | * @grp: Read/Write group | |
1704 | * @work_end: Working window end position | |
4c5e584b MV |
1705 | * @p: DQS Phase Iterator |
1706 | * @i: Iterator | |
1707 | * | |
1708 | * Find non-working DQS enable phase setting. | |
1709 | */ | |
8c887b6e | 1710 | static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i) |
3da42859 | 1711 | { |
192d6f9f | 1712 | int ret; |
3da42859 DN |
1713 | |
1714 | (*p)++; | |
160695d8 MV |
1715 | *work_end += iocfg->delay_per_opa_tap; |
1716 | if (*p > iocfg->dqs_en_phase_max) { | |
192d6f9f | 1717 | /* Fiddle with FIFO. */ |
3da42859 | 1718 | *p = 0; |
8c887b6e | 1719 | rw_mgr_incr_vfifo(grp); |
3da42859 DN |
1720 | } |
1721 | ||
8c887b6e | 1722 | ret = sdr_find_phase(0, grp, work_end, i, p); |
192d6f9f MV |
1723 | if (ret) { |
1724 | /* Cannot see edge of failing read. */ | |
1725 | debug_cond(DLEVEL == 2, "%s:%d: end: failed\n", | |
1726 | __func__, __LINE__); | |
3da42859 DN |
1727 | } |
1728 | ||
192d6f9f | 1729 | return ret; |
3da42859 DN |
1730 | } |
1731 | ||
0a13a0fb MV |
1732 | /** |
1733 | * sdr_find_window_center() - Find center of the working DQS window. | |
1734 | * @grp: Read/Write group | |
1735 | * @work_bgn: First working settings | |
1736 | * @work_end: Last working settings | |
0a13a0fb MV |
1737 | * |
1738 | * Find center of the working DQS enable window. | |
1739 | */ | |
1740 | static int sdr_find_window_center(const u32 grp, const u32 work_bgn, | |
8c887b6e | 1741 | const u32 work_end) |
3da42859 | 1742 | { |
96df6036 | 1743 | u32 work_mid; |
3da42859 | 1744 | int tmp_delay = 0; |
28fd242a | 1745 | int i, p, d; |
3da42859 | 1746 | |
28fd242a | 1747 | work_mid = (work_bgn + work_end) / 2; |
3da42859 DN |
1748 | |
1749 | debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n", | |
28fd242a | 1750 | work_bgn, work_end, work_mid); |
3da42859 | 1751 | /* Get the middle delay to be less than a VFIFO delay */ |
160695d8 | 1752 | tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap; |
28fd242a | 1753 | |
3da42859 | 1754 | debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay); |
cbb0b7e0 | 1755 | work_mid %= tmp_delay; |
28fd242a | 1756 | debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid); |
3da42859 | 1757 | |
160695d8 MV |
1758 | tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap); |
1759 | if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap) | |
1760 | tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap; | |
1761 | p = tmp_delay / iocfg->delay_per_opa_tap; | |
cbb0b7e0 MV |
1762 | |
1763 | debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay); | |
1764 | ||
139823ec MV |
1765 | d = DIV_ROUND_UP(work_mid - tmp_delay, |
1766 | iocfg->delay_per_dqs_en_dchain_tap); | |
160695d8 MV |
1767 | if (d > iocfg->dqs_en_delay_max) |
1768 | d = iocfg->dqs_en_delay_max; | |
1769 | tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap; | |
28fd242a | 1770 | |
28fd242a | 1771 | debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay); |
3da42859 | 1772 | |
cbb0b7e0 | 1773 | scc_mgr_set_dqs_en_phase_all_ranks(grp, p); |
28fd242a | 1774 | scc_mgr_set_dqs_en_delay_all_ranks(grp, d); |
3da42859 DN |
1775 | |
1776 | /* | |
1777 | * push vfifo until we can successfully calibrate. We can do this | |
1778 | * because the largest possible margin in 1 VFIFO cycle. | |
1779 | */ | |
96fd4362 | 1780 | for (i = 0; i < misccfg->read_valid_fifo_size; i++) { |
8c887b6e | 1781 | debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n"); |
28fd242a | 1782 | if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, |
3da42859 | 1783 | PASS_ONE_BIT, |
96df6036 | 1784 | 0)) { |
0a13a0fb | 1785 | debug_cond(DLEVEL == 2, |
8c887b6e MV |
1786 | "%s:%d center: found: ptap=%u dtap=%u\n", |
1787 | __func__, __LINE__, p, d); | |
0a13a0fb | 1788 | return 0; |
3da42859 DN |
1789 | } |
1790 | ||
0a13a0fb | 1791 | /* Fiddle with FIFO. */ |
8c887b6e | 1792 | rw_mgr_incr_vfifo(grp); |
3da42859 DN |
1793 | } |
1794 | ||
0a13a0fb MV |
1795 | debug_cond(DLEVEL == 2, "%s:%d center: failed.\n", |
1796 | __func__, __LINE__); | |
1797 | return -EINVAL; | |
3da42859 DN |
1798 | } |
1799 | ||
33756893 MV |
1800 | /** |
1801 | * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use | |
1802 | * @grp: Read/Write Group | |
1803 | * | |
1804 | * Find a good DQS enable to use. | |
1805 | */ | |
914546e7 | 1806 | static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) |
3da42859 | 1807 | { |
5735540f MV |
1808 | u32 d, p, i; |
1809 | u32 dtaps_per_ptap; | |
1810 | u32 work_bgn, work_end; | |
35e47b71 | 1811 | u32 found_passing_read, found_failing_read = 0, initial_failing_dtap; |
5735540f | 1812 | int ret; |
3da42859 DN |
1813 | |
1814 | debug("%s:%d %u\n", __func__, __LINE__, grp); | |
1815 | ||
1816 | reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); | |
1817 | ||
1818 | scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); | |
1819 | scc_mgr_set_dqs_en_phase_all_ranks(grp, 0); | |
1820 | ||
2f3589ca | 1821 | /* Step 0: Determine number of delay taps for each phase tap. */ |
139823ec MV |
1822 | dtaps_per_ptap = iocfg->delay_per_opa_tap / |
1823 | iocfg->delay_per_dqs_en_dchain_tap; | |
3da42859 | 1824 | |
2f3589ca | 1825 | /* Step 1: First push vfifo until we get a failing read. */ |
d145ca9f | 1826 | find_vfifo_failing_read(grp); |
3da42859 | 1827 | |
2f3589ca | 1828 | /* Step 2: Find first working phase, increment in ptaps. */ |
3da42859 | 1829 | work_bgn = 0; |
914546e7 MV |
1830 | ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i); |
1831 | if (ret) | |
1832 | return ret; | |
3da42859 DN |
1833 | |
1834 | work_end = work_bgn; | |
1835 | ||
1836 | /* | |
2f3589ca MV |
1837 | * If d is 0 then the working window covers a phase tap and we can |
1838 | * follow the old procedure. Otherwise, we've found the beginning | |
3da42859 DN |
1839 | * and we need to increment the dtaps until we find the end. |
1840 | */ | |
1841 | if (d == 0) { | |
2f3589ca MV |
1842 | /* |
1843 | * Step 3a: If we have room, back off by one and | |
1844 | * increment in dtaps. | |
1845 | */ | |
8c887b6e | 1846 | sdr_backup_phase(grp, &work_bgn, &p); |
3da42859 | 1847 | |
2f3589ca MV |
1848 | /* |
1849 | * Step 4a: go forward from working phase to non working | |
1850 | * phase, increment in ptaps. | |
1851 | */ | |
914546e7 MV |
1852 | ret = sdr_nonworking_phase(grp, &work_end, &p, &i); |
1853 | if (ret) | |
1854 | return ret; | |
3da42859 | 1855 | |
2f3589ca | 1856 | /* Step 5a: Back off one from last, increment in dtaps. */ |
3da42859 DN |
1857 | |
1858 | /* Special case code for backing up a phase */ | |
1859 | if (p == 0) { | |
160695d8 | 1860 | p = iocfg->dqs_en_phase_max; |
8c887b6e | 1861 | rw_mgr_decr_vfifo(grp); |
3da42859 DN |
1862 | } else { |
1863 | p = p - 1; | |
1864 | } | |
1865 | ||
160695d8 | 1866 | work_end -= iocfg->delay_per_opa_tap; |
3da42859 DN |
1867 | scc_mgr_set_dqs_en_phase_all_ranks(grp, p); |
1868 | ||
3da42859 DN |
1869 | d = 0; |
1870 | ||
2f3589ca MV |
1871 | debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n", |
1872 | __func__, __LINE__, p); | |
3da42859 DN |
1873 | } |
1874 | ||
2f3589ca | 1875 | /* The dtap increment to find the failing edge is done here. */ |
52e8f217 | 1876 | sdr_find_phase_delay(0, 1, grp, &work_end, |
160695d8 | 1877 | iocfg->delay_per_dqs_en_dchain_tap, &d); |
3da42859 DN |
1878 | |
1879 | /* Go back to working dtap */ | |
1880 | if (d != 0) | |
160695d8 | 1881 | work_end -= iocfg->delay_per_dqs_en_dchain_tap; |
3da42859 | 1882 | |
2f3589ca MV |
1883 | debug_cond(DLEVEL == 2, |
1884 | "%s:%d p/d: ptap=%u dtap=%u end=%u\n", | |
1885 | __func__, __LINE__, p, d - 1, work_end); | |
3da42859 DN |
1886 | |
1887 | if (work_end < work_bgn) { | |
1888 | /* nil range */ | |
2f3589ca MV |
1889 | debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n", |
1890 | __func__, __LINE__); | |
914546e7 | 1891 | return -EINVAL; |
3da42859 DN |
1892 | } |
1893 | ||
2f3589ca | 1894 | debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n", |
3da42859 DN |
1895 | __func__, __LINE__, work_bgn, work_end); |
1896 | ||
3da42859 | 1897 | /* |
2f3589ca MV |
1898 | * We need to calculate the number of dtaps that equal a ptap. |
1899 | * To do that we'll back up a ptap and re-find the edge of the | |
1900 | * window using dtaps | |
3da42859 | 1901 | */ |
2f3589ca MV |
1902 | debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n", |
1903 | __func__, __LINE__); | |
3da42859 DN |
1904 | |
1905 | /* Special case code for backing up a phase */ | |
1906 | if (p == 0) { | |
160695d8 | 1907 | p = iocfg->dqs_en_phase_max; |
8c887b6e | 1908 | rw_mgr_decr_vfifo(grp); |
2f3589ca MV |
1909 | debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n", |
1910 | __func__, __LINE__, p); | |
3da42859 DN |
1911 | } else { |
1912 | p = p - 1; | |
2f3589ca MV |
1913 | debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u", |
1914 | __func__, __LINE__, p); | |
3da42859 DN |
1915 | } |
1916 | ||
1917 | scc_mgr_set_dqs_en_phase_all_ranks(grp, p); | |
1918 | ||
1919 | /* | |
1920 | * Increase dtap until we first see a passing read (in case the | |
2f3589ca MV |
1921 | * window is smaller than a ptap), and then a failing read to |
1922 | * mark the edge of the window again. | |
3da42859 DN |
1923 | */ |
1924 | ||
2f3589ca MV |
1925 | /* Find a passing read. */ |
1926 | debug_cond(DLEVEL == 2, "%s:%d find passing read\n", | |
3da42859 | 1927 | __func__, __LINE__); |
3da42859 | 1928 | |
52e8f217 | 1929 | initial_failing_dtap = d; |
3da42859 | 1930 | |
52e8f217 | 1931 | found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d); |
3da42859 | 1932 | if (found_passing_read) { |
2f3589ca MV |
1933 | /* Find a failing read. */ |
1934 | debug_cond(DLEVEL == 2, "%s:%d find failing read\n", | |
1935 | __func__, __LINE__); | |
52e8f217 MV |
1936 | d++; |
1937 | found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0, | |
1938 | &d); | |
3da42859 | 1939 | } else { |
2f3589ca MV |
1940 | debug_cond(DLEVEL == 1, |
1941 | "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n", | |
1942 | __func__, __LINE__); | |
3da42859 DN |
1943 | } |
1944 | ||
1945 | /* | |
1946 | * The dynamically calculated dtaps_per_ptap is only valid if we | |
1947 | * found a passing/failing read. If we didn't, it means d hit the max | |
160695d8 | 1948 | * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its |
3da42859 DN |
1949 | * statically calculated value. |
1950 | */ | |
1951 | if (found_passing_read && found_failing_read) | |
1952 | dtaps_per_ptap = d - initial_failing_dtap; | |
1953 | ||
1273dd9e | 1954 | writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap); |
2f3589ca MV |
1955 | debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u", |
1956 | __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap); | |
3da42859 | 1957 | |
2f3589ca | 1958 | /* Step 6: Find the centre of the window. */ |
914546e7 | 1959 | ret = sdr_find_window_center(grp, work_bgn, work_end); |
3da42859 | 1960 | |
914546e7 | 1961 | return ret; |
3da42859 DN |
1962 | } |
1963 | ||
901dc36e MV |
1964 | /** |
1965 | * search_stop_check() - Check if the detected edge is valid | |
1966 | * @write: Perform read (Stage 2) or write (Stage 3) calibration | |
1967 | * @d: DQS delay | |
1968 | * @rank_bgn: Rank number | |
1969 | * @write_group: Write Group | |
1970 | * @read_group: Read Group | |
1971 | * @bit_chk: Resulting bit mask after the test | |
1972 | * @sticky_bit_chk: Resulting sticky bit mask after the test | |
1973 | * @use_read_test: Perform read test | |
1974 | * | |
1975 | * Test if the found edge is valid. | |
1976 | */ | |
1977 | static u32 search_stop_check(const int write, const int d, const int rank_bgn, | |
1978 | const u32 write_group, const u32 read_group, | |
1979 | u32 *bit_chk, u32 *sticky_bit_chk, | |
1980 | const u32 use_read_test) | |
1981 | { | |
1fa0c8c4 MV |
1982 | const u32 ratio = rwcfg->mem_if_read_dqs_width / |
1983 | rwcfg->mem_if_write_dqs_width; | |
901dc36e MV |
1984 | const u32 correct_mask = write ? param->write_correct_mask : |
1985 | param->read_correct_mask; | |
1fa0c8c4 MV |
1986 | const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : |
1987 | rwcfg->mem_dq_per_read_dqs; | |
901dc36e MV |
1988 | u32 ret; |
1989 | /* | |
1990 | * Stop searching when the read test doesn't pass AND when | |
1991 | * we've seen a passing read on every bit. | |
1992 | */ | |
1993 | if (write) { /* WRITE-ONLY */ | |
1994 | ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, | |
1995 | 0, PASS_ONE_BIT, | |
1996 | bit_chk, 0); | |
1997 | } else if (use_read_test) { /* READ-ONLY */ | |
1998 | ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group, | |
1999 | NUM_READ_PB_TESTS, | |
2000 | PASS_ONE_BIT, bit_chk, | |
2001 | 0, 0); | |
2002 | } else { /* READ-ONLY */ | |
2003 | rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, | |
2004 | PASS_ONE_BIT, bit_chk, 0); | |
2005 | *bit_chk = *bit_chk >> (per_dqs * | |
2006 | (read_group - (write_group * ratio))); | |
2007 | ret = (*bit_chk == 0); | |
2008 | } | |
2009 | *sticky_bit_chk = *sticky_bit_chk | *bit_chk; | |
2010 | ret = ret && (*sticky_bit_chk == correct_mask); | |
2011 | debug_cond(DLEVEL == 2, | |
2012 | "%s:%d center(left): dtap=%u => %u == %u && %u", | |
2013 | __func__, __LINE__, d, | |
2014 | *sticky_bit_chk, correct_mask, ret); | |
2015 | return ret; | |
2016 | } | |
2017 | ||
71120773 MV |
2018 | /** |
2019 | * search_left_edge() - Find left edge of DQ/DQS working phase | |
2020 | * @write: Perform read (Stage 2) or write (Stage 3) calibration | |
2021 | * @rank_bgn: Rank number | |
2022 | * @write_group: Write Group | |
2023 | * @read_group: Read Group | |
2024 | * @test_bgn: Rank number to begin the test | |
71120773 MV |
2025 | * @sticky_bit_chk: Resulting sticky bit mask after the test |
2026 | * @left_edge: Left edge of the DQ/DQS phase | |
2027 | * @right_edge: Right edge of the DQ/DQS phase | |
2028 | * @use_read_test: Perform read test | |
2029 | * | |
2030 | * Find left edge of DQ/DQS working phase. | |
2031 | */ | |
2032 | static void search_left_edge(const int write, const int rank_bgn, | |
2033 | const u32 write_group, const u32 read_group, const u32 test_bgn, | |
0c4be198 | 2034 | u32 *sticky_bit_chk, |
71120773 MV |
2035 | int *left_edge, int *right_edge, const u32 use_read_test) |
2036 | { | |
139823ec MV |
2037 | const u32 delay_max = write ? iocfg->io_out1_delay_max : |
2038 | iocfg->io_in_delay_max; | |
2039 | const u32 dqs_max = write ? iocfg->io_out1_delay_max : | |
2040 | iocfg->dqs_in_delay_max; | |
1fa0c8c4 MV |
2041 | const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : |
2042 | rwcfg->mem_dq_per_read_dqs; | |
0c4be198 | 2043 | u32 stop, bit_chk; |
71120773 MV |
2044 | int i, d; |
2045 | ||
2046 | for (d = 0; d <= dqs_max; d++) { | |
2047 | if (write) | |
2048 | scc_mgr_apply_group_dq_out1_delay(d); | |
2049 | else | |
2050 | scc_mgr_apply_group_dq_in_delay(test_bgn, d); | |
2051 | ||
2052 | writel(0, &sdr_scc_mgr->update); | |
2053 | ||
901dc36e | 2054 | stop = search_stop_check(write, d, rank_bgn, write_group, |
0c4be198 | 2055 | read_group, &bit_chk, sticky_bit_chk, |
901dc36e | 2056 | use_read_test); |
71120773 MV |
2057 | if (stop == 1) |
2058 | break; | |
2059 | ||
2060 | /* stop != 1 */ | |
2061 | for (i = 0; i < per_dqs; i++) { | |
0c4be198 | 2062 | if (bit_chk & 1) { |
71120773 MV |
2063 | /* |
2064 | * Remember a passing test as | |
2065 | * the left_edge. | |
2066 | */ | |
2067 | left_edge[i] = d; | |
2068 | } else { | |
2069 | /* | |
2070 | * If a left edge has not been seen | |
2071 | * yet, then a future passing test | |
2072 | * will mark this edge as the right | |
2073 | * edge. | |
2074 | */ | |
2075 | if (left_edge[i] == delay_max + 1) | |
2076 | right_edge[i] = -(d + 1); | |
2077 | } | |
0c4be198 | 2078 | bit_chk >>= 1; |
71120773 MV |
2079 | } |
2080 | } | |
2081 | ||
2082 | /* Reset DQ delay chains to 0 */ | |
2083 | if (write) | |
2084 | scc_mgr_apply_group_dq_out1_delay(0); | |
2085 | else | |
2086 | scc_mgr_apply_group_dq_in_delay(test_bgn, 0); | |
2087 | ||
2088 | *sticky_bit_chk = 0; | |
2089 | for (i = per_dqs - 1; i >= 0; i--) { | |
2090 | debug_cond(DLEVEL == 2, | |
2091 | "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n", | |
2092 | __func__, __LINE__, i, left_edge[i], | |
2093 | i, right_edge[i]); | |
2094 | ||
2095 | /* | |
2096 | * Check for cases where we haven't found the left edge, | |
2097 | * which makes our assignment of the the right edge invalid. | |
2098 | * Reset it to the illegal value. | |
2099 | */ | |
2100 | if ((left_edge[i] == delay_max + 1) && | |
2101 | (right_edge[i] != delay_max + 1)) { | |
2102 | right_edge[i] = delay_max + 1; | |
2103 | debug_cond(DLEVEL == 2, | |
2104 | "%s:%d vfifo_center: reset right_edge[%u]: %d\n", | |
2105 | __func__, __LINE__, i, right_edge[i]); | |
2106 | } | |
2107 | ||
2108 | /* | |
2109 | * Reset sticky bit | |
2110 | * READ: except for bits where we have seen both | |
2111 | * the left and right edge. | |
2112 | * WRITE: except for bits where we have seen the | |
2113 | * left edge. | |
2114 | */ | |
2115 | *sticky_bit_chk <<= 1; | |
2116 | if (write) { | |
2117 | if (left_edge[i] != delay_max + 1) | |
2118 | *sticky_bit_chk |= 1; | |
2119 | } else { | |
2120 | if ((left_edge[i] != delay_max + 1) && | |
2121 | (right_edge[i] != delay_max + 1)) | |
2122 | *sticky_bit_chk |= 1; | |
2123 | } | |
2124 | } | |
71120773 MV |
2125 | } |
2126 | ||
c4907898 MV |
2127 | /** |
2128 | * search_right_edge() - Find right edge of DQ/DQS working phase | |
2129 | * @write: Perform read (Stage 2) or write (Stage 3) calibration | |
2130 | * @rank_bgn: Rank number | |
2131 | * @write_group: Write Group | |
2132 | * @read_group: Read Group | |
2133 | * @start_dqs: DQS start phase | |
2134 | * @start_dqs_en: DQS enable start phase | |
c4907898 MV |
2135 | * @sticky_bit_chk: Resulting sticky bit mask after the test |
2136 | * @left_edge: Left edge of the DQ/DQS phase | |
2137 | * @right_edge: Right edge of the DQ/DQS phase | |
2138 | * @use_read_test: Perform read test | |
2139 | * | |
2140 | * Find right edge of DQ/DQS working phase. | |
2141 | */ | |
2142 | static int search_right_edge(const int write, const int rank_bgn, | |
2143 | const u32 write_group, const u32 read_group, | |
2144 | const int start_dqs, const int start_dqs_en, | |
0c4be198 | 2145 | u32 *sticky_bit_chk, |
c4907898 MV |
2146 | int *left_edge, int *right_edge, const u32 use_read_test) |
2147 | { | |
139823ec MV |
2148 | const u32 delay_max = write ? iocfg->io_out1_delay_max : |
2149 | iocfg->io_in_delay_max; | |
2150 | const u32 dqs_max = write ? iocfg->io_out1_delay_max : | |
2151 | iocfg->dqs_in_delay_max; | |
1fa0c8c4 MV |
2152 | const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : |
2153 | rwcfg->mem_dq_per_read_dqs; | |
0c4be198 | 2154 | u32 stop, bit_chk; |
c4907898 MV |
2155 | int i, d; |
2156 | ||
2157 | for (d = 0; d <= dqs_max - start_dqs; d++) { | |
2158 | if (write) { /* WRITE-ONLY */ | |
2159 | scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, | |
2160 | d + start_dqs); | |
2161 | } else { /* READ-ONLY */ | |
2162 | scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs); | |
160695d8 | 2163 | if (iocfg->shift_dqs_en_when_shift_dqs) { |
5ded7320 | 2164 | u32 delay = d + start_dqs_en; |
160695d8 MV |
2165 | if (delay > iocfg->dqs_en_delay_max) |
2166 | delay = iocfg->dqs_en_delay_max; | |
c4907898 MV |
2167 | scc_mgr_set_dqs_en_delay(read_group, delay); |
2168 | } | |
2169 | scc_mgr_load_dqs(read_group); | |
2170 | } | |
2171 | ||
2172 | writel(0, &sdr_scc_mgr->update); | |
2173 | ||
901dc36e | 2174 | stop = search_stop_check(write, d, rank_bgn, write_group, |
0c4be198 | 2175 | read_group, &bit_chk, sticky_bit_chk, |
901dc36e | 2176 | use_read_test); |
c4907898 MV |
2177 | if (stop == 1) { |
2178 | if (write && (d == 0)) { /* WRITE-ONLY */ | |
139823ec MV |
2179 | for (i = 0; i < rwcfg->mem_dq_per_write_dqs; |
2180 | i++) { | |
c4907898 MV |
2181 | /* |
2182 | * d = 0 failed, but it passed when | |
2183 | * testing the left edge, so it must be | |
2184 | * marginal, set it to -1 | |
2185 | */ | |
2186 | if (right_edge[i] == delay_max + 1 && | |
2187 | left_edge[i] != delay_max + 1) | |
2188 | right_edge[i] = -1; | |
2189 | } | |
2190 | } | |
2191 | break; | |
2192 | } | |
2193 | ||
2194 | /* stop != 1 */ | |
2195 | for (i = 0; i < per_dqs; i++) { | |
0c4be198 | 2196 | if (bit_chk & 1) { |
c4907898 MV |
2197 | /* |
2198 | * Remember a passing test as | |
2199 | * the right_edge. | |
2200 | */ | |
2201 | right_edge[i] = d; | |
2202 | } else { | |
2203 | if (d != 0) { | |
2204 | /* | |
2205 | * If a right edge has not | |
2206 | * been seen yet, then a future | |
2207 | * passing test will mark this | |
2208 | * edge as the left edge. | |
2209 | */ | |
2210 | if (right_edge[i] == delay_max + 1) | |
2211 | left_edge[i] = -(d + 1); | |
2212 | } else { | |
2213 | /* | |
2214 | * d = 0 failed, but it passed | |
2215 | * when testing the left edge, | |
2216 | * so it must be marginal, set | |
2217 | * it to -1 | |
2218 | */ | |
2219 | if (right_edge[i] == delay_max + 1 && | |
2220 | left_edge[i] != delay_max + 1) | |
2221 | right_edge[i] = -1; | |
2222 | /* | |
2223 | * If a right edge has not been | |
2224 | * seen yet, then a future | |
2225 | * passing test will mark this | |
2226 | * edge as the left edge. | |
2227 | */ | |
2228 | else if (right_edge[i] == delay_max + 1) | |
2229 | left_edge[i] = -(d + 1); | |
2230 | } | |
2231 | } | |
2232 | ||
2233 | debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ", | |
2234 | __func__, __LINE__, d); | |
2235 | debug_cond(DLEVEL == 2, | |
2236 | "bit_chk_test=%i left_edge[%u]: %d ", | |
0c4be198 | 2237 | bit_chk & 1, i, left_edge[i]); |
c4907898 MV |
2238 | debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i, |
2239 | right_edge[i]); | |
0c4be198 | 2240 | bit_chk >>= 1; |
c4907898 MV |
2241 | } |
2242 | } | |
2243 | ||
2244 | /* Check that all bits have a window */ | |
2245 | for (i = 0; i < per_dqs; i++) { | |
2246 | debug_cond(DLEVEL == 2, | |
2247 | "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d", | |
2248 | __func__, __LINE__, i, left_edge[i], | |
2249 | i, right_edge[i]); | |
2250 | if ((left_edge[i] == dqs_max + 1) || | |
2251 | (right_edge[i] == dqs_max + 1)) | |
2252 | return i + 1; /* FIXME: If we fail, retval > 0 */ | |
2253 | } | |
2254 | ||
2255 | return 0; | |
2256 | } | |
2257 | ||
afb3eb84 MV |
2258 | /** |
2259 | * get_window_mid_index() - Find the best middle setting of DQ/DQS phase | |
2260 | * @write: Perform read (Stage 2) or write (Stage 3) calibration | |
2261 | * @left_edge: Left edge of the DQ/DQS phase | |
2262 | * @right_edge: Right edge of the DQ/DQS phase | |
2263 | * @mid_min: Best DQ/DQS phase middle setting | |
2264 | * | |
2265 | * Find index and value of the middle of the DQ/DQS working phase. | |
2266 | */ | |
2267 | static int get_window_mid_index(const int write, int *left_edge, | |
2268 | int *right_edge, int *mid_min) | |
2269 | { | |
1fa0c8c4 MV |
2270 | const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : |
2271 | rwcfg->mem_dq_per_read_dqs; | |
afb3eb84 MV |
2272 | int i, mid, min_index; |
2273 | ||
2274 | /* Find middle of window for each DQ bit */ | |
2275 | *mid_min = left_edge[0] - right_edge[0]; | |
2276 | min_index = 0; | |
2277 | for (i = 1; i < per_dqs; i++) { | |
2278 | mid = left_edge[i] - right_edge[i]; | |
2279 | if (mid < *mid_min) { | |
2280 | *mid_min = mid; | |
2281 | min_index = i; | |
2282 | } | |
2283 | } | |
2284 | ||
2285 | /* | |
2286 | * -mid_min/2 represents the amount that we need to move DQS. | |
2287 | * If mid_min is odd and positive we'll need to add one to make | |
2288 | * sure the rounding in further calculations is correct (always | |
2289 | * bias to the right), so just add 1 for all positive values. | |
2290 | */ | |
2291 | if (*mid_min > 0) | |
2292 | (*mid_min)++; | |
2293 | *mid_min = *mid_min / 2; | |
2294 | ||
2295 | debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n", | |
2296 | __func__, __LINE__, *mid_min, min_index); | |
2297 | return min_index; | |
2298 | } | |
2299 | ||
ffb8b66e MV |
2300 | /** |
2301 | * center_dq_windows() - Center the DQ/DQS windows | |
2302 | * @write: Perform read (Stage 2) or write (Stage 3) calibration | |
2303 | * @left_edge: Left edge of the DQ/DQS phase | |
2304 | * @right_edge: Right edge of the DQ/DQS phase | |
2305 | * @mid_min: Adjusted DQ/DQS phase middle setting | |
2306 | * @orig_mid_min: Original DQ/DQS phase middle setting | |
2307 | * @min_index: DQ/DQS phase middle setting index | |
2308 | * @test_bgn: Rank number to begin the test | |
2309 | * @dq_margin: Amount of shift for the DQ | |
2310 | * @dqs_margin: Amount of shift for the DQS | |
2311 | * | |
2312 | * Align the DQ/DQS windows in each group. | |
2313 | */ | |
2314 | static void center_dq_windows(const int write, int *left_edge, int *right_edge, | |
2315 | const int mid_min, const int orig_mid_min, | |
2316 | const int min_index, const int test_bgn, | |
2317 | int *dq_margin, int *dqs_margin) | |
2318 | { | |
139823ec MV |
2319 | const u32 delay_max = write ? iocfg->io_out1_delay_max : |
2320 | iocfg->io_in_delay_max; | |
1fa0c8c4 MV |
2321 | const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : |
2322 | rwcfg->mem_dq_per_read_dqs; | |
ffb8b66e MV |
2323 | const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET : |
2324 | SCC_MGR_IO_IN_DELAY_OFFSET; | |
2325 | const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off; | |
2326 | ||
2327 | u32 temp_dq_io_delay1, temp_dq_io_delay2; | |
2328 | int shift_dq, i, p; | |
2329 | ||
2330 | /* Initialize data for export structures */ | |
2331 | *dqs_margin = delay_max + 1; | |
2332 | *dq_margin = delay_max + 1; | |
2333 | ||
2334 | /* add delay to bring centre of all DQ windows to the same "level" */ | |
2335 | for (i = 0, p = test_bgn; i < per_dqs; i++, p++) { | |
2336 | /* Use values before divide by 2 to reduce round off error */ | |
2337 | shift_dq = (left_edge[i] - right_edge[i] - | |
2338 | (left_edge[min_index] - right_edge[min_index]))/2 + | |
2339 | (orig_mid_min - mid_min); | |
2340 | ||
2341 | debug_cond(DLEVEL == 2, | |
2342 | "vfifo_center: before: shift_dq[%u]=%d\n", | |
2343 | i, shift_dq); | |
2344 | ||
2345 | temp_dq_io_delay1 = readl(addr + (p << 2)); | |
2346 | temp_dq_io_delay2 = readl(addr + (i << 2)); | |
2347 | ||
2348 | if (shift_dq + temp_dq_io_delay1 > delay_max) | |
2349 | shift_dq = delay_max - temp_dq_io_delay2; | |
2350 | else if (shift_dq + temp_dq_io_delay1 < 0) | |
2351 | shift_dq = -temp_dq_io_delay1; | |
2352 | ||
2353 | debug_cond(DLEVEL == 2, | |
2354 | "vfifo_center: after: shift_dq[%u]=%d\n", | |
2355 | i, shift_dq); | |
2356 | ||
2357 | if (write) | |
139823ec MV |
2358 | scc_mgr_set_dq_out1_delay(i, |
2359 | temp_dq_io_delay1 + shift_dq); | |
ffb8b66e | 2360 | else |
139823ec MV |
2361 | scc_mgr_set_dq_in_delay(p, |
2362 | temp_dq_io_delay1 + shift_dq); | |
ffb8b66e MV |
2363 | |
2364 | scc_mgr_load_dq(p); | |
2365 | ||
2366 | debug_cond(DLEVEL == 2, | |
2367 | "vfifo_center: margin[%u]=[%d,%d]\n", i, | |
2368 | left_edge[i] - shift_dq + (-mid_min), | |
2369 | right_edge[i] + shift_dq - (-mid_min)); | |
2370 | ||
2371 | /* To determine values for export structures */ | |
2372 | if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin) | |
2373 | *dq_margin = left_edge[i] - shift_dq + (-mid_min); | |
2374 | ||
2375 | if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin) | |
2376 | *dqs_margin = right_edge[i] + shift_dq - (-mid_min); | |
2377 | } | |
ffb8b66e MV |
2378 | } |
2379 | ||
ac63b9ad MV |
2380 | /** |
2381 | * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering | |
2382 | * @rank_bgn: Rank number | |
2383 | * @rw_group: Read/Write Group | |
2384 | * @test_bgn: Rank at which the test begins | |
2385 | * @use_read_test: Perform a read test | |
2386 | * @update_fom: Update FOM | |
2387 | * | |
2388 | * Per-bit deskew DQ and centering. | |
2389 | */ | |
0113c3e1 MV |
2390 | static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, |
2391 | const u32 rw_group, const u32 test_bgn, | |
2392 | const int use_read_test, const int update_fom) | |
3da42859 | 2393 | { |
5d6db444 MV |
2394 | const u32 addr = |
2395 | SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET + | |
0113c3e1 | 2396 | (rw_group << 2); |
3da42859 DN |
2397 | /* |
2398 | * Store these as signed since there are comparisons with | |
2399 | * signed numbers. | |
2400 | */ | |
5ded7320 | 2401 | u32 sticky_bit_chk; |
1fa0c8c4 MV |
2402 | int32_t left_edge[rwcfg->mem_dq_per_read_dqs]; |
2403 | int32_t right_edge[rwcfg->mem_dq_per_read_dqs]; | |
3da42859 | 2404 | int32_t orig_mid_min, mid_min; |
160695d8 | 2405 | int32_t new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en; |
3da42859 | 2406 | int32_t dq_margin, dqs_margin; |
5d6db444 | 2407 | int i, min_index; |
c4907898 | 2408 | int ret; |
3da42859 | 2409 | |
0113c3e1 | 2410 | debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn); |
3da42859 | 2411 | |
5d6db444 | 2412 | start_dqs = readl(addr); |
160695d8 MV |
2413 | if (iocfg->shift_dqs_en_when_shift_dqs) |
2414 | start_dqs_en = readl(addr - iocfg->dqs_en_delay_offset); | |
3da42859 DN |
2415 | |
2416 | /* set the left and right edge of each bit to an illegal value */ | |
160695d8 | 2417 | /* use (iocfg->io_in_delay_max + 1) as an illegal value */ |
3da42859 | 2418 | sticky_bit_chk = 0; |
1fa0c8c4 | 2419 | for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) { |
160695d8 MV |
2420 | left_edge[i] = iocfg->io_in_delay_max + 1; |
2421 | right_edge[i] = iocfg->io_in_delay_max + 1; | |
3da42859 DN |
2422 | } |
2423 | ||
3da42859 | 2424 | /* Search for the left edge of the window for each bit */ |
0113c3e1 | 2425 | search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn, |
0c4be198 | 2426 | &sticky_bit_chk, |
71120773 | 2427 | left_edge, right_edge, use_read_test); |
3da42859 | 2428 | |
f0712c35 | 2429 | |
3da42859 | 2430 | /* Search for the right edge of the window for each bit */ |
0113c3e1 | 2431 | ret = search_right_edge(0, rank_bgn, rw_group, rw_group, |
c4907898 | 2432 | start_dqs, start_dqs_en, |
0c4be198 | 2433 | &sticky_bit_chk, |
c4907898 MV |
2434 | left_edge, right_edge, use_read_test); |
2435 | if (ret) { | |
3da42859 | 2436 | /* |
c4907898 MV |
2437 | * Restore delay chain settings before letting the loop |
2438 | * in rw_mgr_mem_calibrate_vfifo to retry different | |
2439 | * dqs/ck relationships. | |
3da42859 | 2440 | */ |
0113c3e1 | 2441 | scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs); |
160695d8 | 2442 | if (iocfg->shift_dqs_en_when_shift_dqs) |
0113c3e1 | 2443 | scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en); |
3da42859 | 2444 | |
0113c3e1 | 2445 | scc_mgr_load_dqs(rw_group); |
c4907898 | 2446 | writel(0, &sdr_scc_mgr->update); |
3da42859 | 2447 | |
c4907898 MV |
2448 | debug_cond(DLEVEL == 1, |
2449 | "%s:%d vfifo_center: failed to find edge [%u]: %d %d", | |
2450 | __func__, __LINE__, i, left_edge[i], right_edge[i]); | |
2451 | if (use_read_test) { | |
0113c3e1 | 2452 | set_failing_group_stage(rw_group * |
1fa0c8c4 | 2453 | rwcfg->mem_dq_per_read_dqs + i, |
c4907898 MV |
2454 | CAL_STAGE_VFIFO, |
2455 | CAL_SUBSTAGE_VFIFO_CENTER); | |
3da42859 | 2456 | } else { |
0113c3e1 | 2457 | set_failing_group_stage(rw_group * |
1fa0c8c4 | 2458 | rwcfg->mem_dq_per_read_dqs + i, |
c4907898 MV |
2459 | CAL_STAGE_VFIFO_AFTER_WRITES, |
2460 | CAL_SUBSTAGE_VFIFO_CENTER); | |
3da42859 | 2461 | } |
98668247 | 2462 | return -EIO; |
3da42859 DN |
2463 | } |
2464 | ||
afb3eb84 | 2465 | min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min); |
3da42859 DN |
2466 | |
2467 | /* Determine the amount we can change DQS (which is -mid_min) */ | |
2468 | orig_mid_min = mid_min; | |
2469 | new_dqs = start_dqs - mid_min; | |
160695d8 MV |
2470 | if (new_dqs > iocfg->dqs_in_delay_max) |
2471 | new_dqs = iocfg->dqs_in_delay_max; | |
3da42859 DN |
2472 | else if (new_dqs < 0) |
2473 | new_dqs = 0; | |
2474 | ||
2475 | mid_min = start_dqs - new_dqs; | |
2476 | debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n", | |
2477 | mid_min, new_dqs); | |
2478 | ||
160695d8 MV |
2479 | if (iocfg->shift_dqs_en_when_shift_dqs) { |
2480 | if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max) | |
139823ec MV |
2481 | mid_min += start_dqs_en - mid_min - |
2482 | iocfg->dqs_en_delay_max; | |
3da42859 DN |
2483 | else if (start_dqs_en - mid_min < 0) |
2484 | mid_min += start_dqs_en - mid_min; | |
2485 | } | |
2486 | new_dqs = start_dqs - mid_min; | |
2487 | ||
f0712c35 MV |
2488 | debug_cond(DLEVEL == 1, |
2489 | "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n", | |
2490 | start_dqs, | |
160695d8 | 2491 | iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1, |
3da42859 DN |
2492 | new_dqs, mid_min); |
2493 | ||
ffb8b66e MV |
2494 | /* Add delay to bring centre of all DQ windows to the same "level". */ |
2495 | center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min, | |
2496 | min_index, test_bgn, &dq_margin, &dqs_margin); | |
3da42859 | 2497 | |
3da42859 | 2498 | /* Move DQS-en */ |
160695d8 | 2499 | if (iocfg->shift_dqs_en_when_shift_dqs) { |
5d6db444 | 2500 | final_dqs_en = start_dqs_en - mid_min; |
0113c3e1 MV |
2501 | scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en); |
2502 | scc_mgr_load_dqs(rw_group); | |
3da42859 DN |
2503 | } |
2504 | ||
2505 | /* Move DQS */ | |
0113c3e1 MV |
2506 | scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs); |
2507 | scc_mgr_load_dqs(rw_group); | |
f0712c35 MV |
2508 | debug_cond(DLEVEL == 2, |
2509 | "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d", | |
2510 | __func__, __LINE__, dq_margin, dqs_margin); | |
3da42859 DN |
2511 | |
2512 | /* | |
2513 | * Do not remove this line as it makes sure all of our decisions | |
2514 | * have been applied. Apply the update bit. | |
2515 | */ | |
1273dd9e | 2516 | writel(0, &sdr_scc_mgr->update); |
3da42859 | 2517 | |
98668247 MV |
2518 | if ((dq_margin < 0) || (dqs_margin < 0)) |
2519 | return -EINVAL; | |
2520 | ||
2521 | return 0; | |
3da42859 DN |
2522 | } |
2523 | ||
04372fb8 MV |
2524 | /** |
2525 | * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device | |
2526 | * @rw_group: Read/Write Group | |
2527 | * @phase: DQ/DQS phase | |
2528 | * | |
2529 | * Because initially no communication ca be reliably performed with the memory | |
2530 | * device, the sequencer uses a guaranteed write mechanism to write data into | |
2531 | * the memory device. | |
2532 | */ | |
2533 | static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, | |
2534 | const u32 phase) | |
2535 | { | |
04372fb8 MV |
2536 | int ret; |
2537 | ||
2538 | /* Set a particular DQ/DQS phase. */ | |
2539 | scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase); | |
2540 | ||
2541 | debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n", | |
2542 | __func__, __LINE__, rw_group, phase); | |
2543 | ||
2544 | /* | |
2545 | * Altera EMI_RM 2015.05.04 :: Figure 1-25 | |
2546 | * Load up the patterns used by read calibration using the | |
2547 | * current DQDQS phase. | |
2548 | */ | |
2549 | rw_mgr_mem_calibrate_read_load_patterns(0, 1); | |
2550 | ||
2551 | if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ) | |
2552 | return 0; | |
2553 | ||
2554 | /* | |
2555 | * Altera EMI_RM 2015.05.04 :: Figure 1-26 | |
2556 | * Back-to-Back reads of the patterns used for calibration. | |
2557 | */ | |
d844c7d4 MV |
2558 | ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1); |
2559 | if (ret) | |
04372fb8 MV |
2560 | debug_cond(DLEVEL == 1, |
2561 | "%s:%d Guaranteed read test failed: g=%u p=%u\n", | |
2562 | __func__, __LINE__, rw_group, phase); | |
d844c7d4 | 2563 | return ret; |
04372fb8 MV |
2564 | } |
2565 | ||
f09da11e MV |
2566 | /** |
2567 | * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration | |
2568 | * @rw_group: Read/Write Group | |
2569 | * @test_bgn: Rank at which the test begins | |
2570 | * | |
2571 | * DQS enable calibration ensures reliable capture of the DQ signal without | |
2572 | * glitches on the DQS line. | |
2573 | */ | |
2574 | static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, | |
2575 | const u32 test_bgn) | |
2576 | { | |
f09da11e MV |
2577 | /* |
2578 | * Altera EMI_RM 2015.05.04 :: Figure 1-27 | |
2579 | * DQS and DQS Eanble Signal Relationships. | |
2580 | */ | |
28ea827d MV |
2581 | |
2582 | /* We start at zero, so have one less dq to devide among */ | |
160695d8 | 2583 | const u32 delay_step = iocfg->io_in_delay_max / |
1fa0c8c4 | 2584 | (rwcfg->mem_dq_per_read_dqs - 1); |
914546e7 | 2585 | int ret; |
28ea827d MV |
2586 | u32 i, p, d, r; |
2587 | ||
2588 | debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn); | |
2589 | ||
2590 | /* Try different dq_in_delays since the DQ path is shorter than DQS. */ | |
1fa0c8c4 | 2591 | for (r = 0; r < rwcfg->mem_number_of_ranks; |
28ea827d MV |
2592 | r += NUM_RANKS_PER_SHADOW_REG) { |
2593 | for (i = 0, p = test_bgn, d = 0; | |
1fa0c8c4 | 2594 | i < rwcfg->mem_dq_per_read_dqs; |
28ea827d MV |
2595 | i++, p++, d += delay_step) { |
2596 | debug_cond(DLEVEL == 1, | |
2597 | "%s:%d: g=%u r=%u i=%u p=%u d=%u\n", | |
2598 | __func__, __LINE__, rw_group, r, i, p, d); | |
2599 | ||
2600 | scc_mgr_set_dq_in_delay(p, d); | |
2601 | scc_mgr_load_dq(p); | |
2602 | } | |
2603 | ||
2604 | writel(0, &sdr_scc_mgr->update); | |
2605 | } | |
2606 | ||
2607 | /* | |
2608 | * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different | |
2609 | * dq_in_delay values | |
2610 | */ | |
914546e7 | 2611 | ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group); |
28ea827d MV |
2612 | |
2613 | debug_cond(DLEVEL == 1, | |
2614 | "%s:%d: g=%u found=%u; Reseting delay chain to zero\n", | |
914546e7 | 2615 | __func__, __LINE__, rw_group, !ret); |
28ea827d | 2616 | |
1fa0c8c4 | 2617 | for (r = 0; r < rwcfg->mem_number_of_ranks; |
28ea827d MV |
2618 | r += NUM_RANKS_PER_SHADOW_REG) { |
2619 | scc_mgr_apply_group_dq_in_delay(test_bgn, 0); | |
2620 | writel(0, &sdr_scc_mgr->update); | |
2621 | } | |
2622 | ||
914546e7 | 2623 | return ret; |
f09da11e MV |
2624 | } |
2625 | ||
16cfc4b9 MV |
2626 | /** |
2627 | * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS | |
2628 | * @rw_group: Read/Write Group | |
2629 | * @test_bgn: Rank at which the test begins | |
2630 | * @use_read_test: Perform a read test | |
2631 | * @update_fom: Update FOM | |
2632 | * | |
2633 | * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads | |
2634 | * within a group. | |
2635 | */ | |
2636 | static int | |
2637 | rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, | |
2638 | const int use_read_test, | |
2639 | const int update_fom) | |
2640 | ||
2641 | { | |
2642 | int ret, grp_calibrated; | |
2643 | u32 rank_bgn, sr; | |
2644 | ||
2645 | /* | |
2646 | * Altera EMI_RM 2015.05.04 :: Figure 1-28 | |
2647 | * Read per-bit deskew can be done on a per shadow register basis. | |
2648 | */ | |
2649 | grp_calibrated = 1; | |
2650 | for (rank_bgn = 0, sr = 0; | |
1fa0c8c4 | 2651 | rank_bgn < rwcfg->mem_number_of_ranks; |
16cfc4b9 | 2652 | rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) { |
16cfc4b9 | 2653 | ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group, |
0113c3e1 | 2654 | test_bgn, |
16cfc4b9 MV |
2655 | use_read_test, |
2656 | update_fom); | |
98668247 | 2657 | if (!ret) |
16cfc4b9 MV |
2658 | continue; |
2659 | ||
2660 | grp_calibrated = 0; | |
2661 | } | |
2662 | ||
2663 | if (!grp_calibrated) | |
2664 | return -EIO; | |
2665 | ||
2666 | return 0; | |
2667 | } | |
2668 | ||
bce24efa MV |
2669 | /** |
2670 | * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO | |
2671 | * @rw_group: Read/Write Group | |
2672 | * @test_bgn: Rank at which the test begins | |
2673 | * | |
2674 | * Stage 1: Calibrate the read valid prediction FIFO. | |
2675 | * | |
2676 | * This function implements UniPHY calibration Stage 1, as explained in | |
2677 | * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". | |
3da42859 | 2678 | * |
bce24efa MV |
2679 | * - read valid prediction will consist of finding: |
2680 | * - DQS enable phase and DQS enable delay (DQS Enable Calibration) | |
2681 | * - DQS input phase and DQS input delay (DQ/DQS Centering) | |
3da42859 DN |
2682 | * - we also do a per-bit deskew on the DQ lines. |
2683 | */ | |
c336ca3e | 2684 | static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) |
3da42859 | 2685 | { |
5ded7320 MV |
2686 | u32 p, d; |
2687 | u32 dtaps_per_ptap; | |
2688 | u32 failed_substage; | |
3da42859 | 2689 | |
04372fb8 MV |
2690 | int ret; |
2691 | ||
c336ca3e | 2692 | debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn); |
3da42859 | 2693 | |
7c0a9df3 MV |
2694 | /* Update info for sims */ |
2695 | reg_file_set_group(rw_group); | |
3da42859 | 2696 | reg_file_set_stage(CAL_STAGE_VFIFO); |
7c0a9df3 | 2697 | reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ); |
3da42859 | 2698 | |
7c0a9df3 MV |
2699 | failed_substage = CAL_SUBSTAGE_GUARANTEED_READ; |
2700 | ||
2701 | /* USER Determine number of delay taps for each phase tap. */ | |
160695d8 MV |
2702 | dtaps_per_ptap = DIV_ROUND_UP(iocfg->delay_per_opa_tap, |
2703 | iocfg->delay_per_dqs_en_dchain_tap) - 1; | |
3da42859 | 2704 | |
fe2d0a2d | 2705 | for (d = 0; d <= dtaps_per_ptap; d += 2) { |
3da42859 DN |
2706 | /* |
2707 | * In RLDRAMX we may be messing the delay of pins in | |
c336ca3e MV |
2708 | * the same write rw_group but outside of the current read |
2709 | * the rw_group, but that's ok because we haven't calibrated | |
ac70d2f3 | 2710 | * output side yet. |
3da42859 DN |
2711 | */ |
2712 | if (d > 0) { | |
f51a7d35 | 2713 | scc_mgr_apply_group_all_out_delay_add_all_ranks( |
c336ca3e | 2714 | rw_group, d); |
3da42859 DN |
2715 | } |
2716 | ||
160695d8 | 2717 | for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) { |
04372fb8 MV |
2718 | /* 1) Guaranteed Write */ |
2719 | ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p); | |
2720 | if (ret) | |
2721 | break; | |
3da42859 | 2722 | |
f09da11e MV |
2723 | /* 2) DQS Enable Calibration */ |
2724 | ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group, | |
2725 | test_bgn); | |
2726 | if (ret) { | |
3da42859 | 2727 | failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE; |
fe2d0a2d MV |
2728 | continue; |
2729 | } | |
2730 | ||
16cfc4b9 | 2731 | /* 3) Centering DQ/DQS */ |
fe2d0a2d | 2732 | /* |
16cfc4b9 MV |
2733 | * If doing read after write calibration, do not update |
2734 | * FOM now. Do it then. | |
fe2d0a2d | 2735 | */ |
16cfc4b9 MV |
2736 | ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, |
2737 | test_bgn, 1, 0); | |
2738 | if (ret) { | |
fe2d0a2d | 2739 | failed_substage = CAL_SUBSTAGE_VFIFO_CENTER; |
16cfc4b9 | 2740 | continue; |
3da42859 | 2741 | } |
fe2d0a2d | 2742 | |
16cfc4b9 MV |
2743 | /* All done. */ |
2744 | goto cal_done_ok; | |
3da42859 DN |
2745 | } |
2746 | } | |
2747 | ||
fe2d0a2d | 2748 | /* Calibration Stage 1 failed. */ |
c336ca3e | 2749 | set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage); |
fe2d0a2d | 2750 | return 0; |
3da42859 | 2751 | |
fe2d0a2d MV |
2752 | /* Calibration Stage 1 completed OK. */ |
2753 | cal_done_ok: | |
3da42859 DN |
2754 | /* |
2755 | * Reset the delay chains back to zero if they have moved > 1 | |
2756 | * (check for > 1 because loop will increase d even when pass in | |
2757 | * first case). | |
2758 | */ | |
2759 | if (d > 2) | |
c336ca3e | 2760 | scc_mgr_zero_group(rw_group, 1); |
3da42859 DN |
2761 | |
2762 | return 1; | |
2763 | } | |
2764 | ||
78cdd7d0 MV |
2765 | /** |
2766 | * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering. | |
2767 | * @rw_group: Read/Write Group | |
2768 | * @test_bgn: Rank at which the test begins | |
2769 | * | |
2770 | * Stage 3: DQ/DQS Centering. | |
2771 | * | |
2772 | * This function implements UniPHY calibration Stage 3, as explained in | |
2773 | * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". | |
2774 | */ | |
2775 | static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, | |
2776 | const u32 test_bgn) | |
3da42859 | 2777 | { |
78cdd7d0 | 2778 | int ret; |
3da42859 | 2779 | |
78cdd7d0 | 2780 | debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn); |
3da42859 | 2781 | |
78cdd7d0 MV |
2782 | /* Update info for sims. */ |
2783 | reg_file_set_group(rw_group); | |
3da42859 DN |
2784 | reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES); |
2785 | reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); | |
2786 | ||
78cdd7d0 MV |
2787 | ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1); |
2788 | if (ret) | |
2789 | set_failing_group_stage(rw_group, | |
3da42859 DN |
2790 | CAL_STAGE_VFIFO_AFTER_WRITES, |
2791 | CAL_SUBSTAGE_VFIFO_CENTER); | |
78cdd7d0 | 2792 | return ret; |
3da42859 DN |
2793 | } |
2794 | ||
c984278a MV |
2795 | /** |
2796 | * rw_mgr_mem_calibrate_lfifo() - Minimize latency | |
2797 | * | |
2798 | * Stage 4: Minimize latency. | |
2799 | * | |
2800 | * This function implements UniPHY calibration Stage 4, as explained in | |
2801 | * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". | |
2802 | * Calibrate LFIFO to find smallest read latency. | |
2803 | */ | |
5ded7320 | 2804 | static u32 rw_mgr_mem_calibrate_lfifo(void) |
3da42859 | 2805 | { |
c984278a | 2806 | int found_one = 0; |
3da42859 DN |
2807 | |
2808 | debug("%s:%d\n", __func__, __LINE__); | |
2809 | ||
c984278a | 2810 | /* Update info for sims. */ |
3da42859 DN |
2811 | reg_file_set_stage(CAL_STAGE_LFIFO); |
2812 | reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY); | |
2813 | ||
2814 | /* Load up the patterns used by read calibration for all ranks */ | |
2815 | rw_mgr_mem_calibrate_read_load_patterns(0, 1); | |
3da42859 | 2816 | |
3da42859 | 2817 | do { |
1273dd9e | 2818 | writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); |
3da42859 DN |
2819 | debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u", |
2820 | __func__, __LINE__, gbl->curr_read_lat); | |
2821 | ||
c984278a MV |
2822 | if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS, |
2823 | PASS_ALL_BITS, 1)) | |
3da42859 | 2824 | break; |
3da42859 DN |
2825 | |
2826 | found_one = 1; | |
c984278a MV |
2827 | /* |
2828 | * Reduce read latency and see if things are | |
2829 | * working correctly. | |
2830 | */ | |
3da42859 DN |
2831 | gbl->curr_read_lat--; |
2832 | } while (gbl->curr_read_lat > 0); | |
2833 | ||
c984278a | 2834 | /* Reset the fifos to get pointers to known state. */ |
1273dd9e | 2835 | writel(0, &phy_mgr_cmd->fifo_reset); |
3da42859 DN |
2836 | |
2837 | if (found_one) { | |
c984278a | 2838 | /* Add a fudge factor to the read latency that was determined */ |
3da42859 | 2839 | gbl->curr_read_lat += 2; |
1273dd9e | 2840 | writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); |
c984278a MV |
2841 | debug_cond(DLEVEL == 2, |
2842 | "%s:%d lfifo: success: using read_lat=%u\n", | |
2843 | __func__, __LINE__, gbl->curr_read_lat); | |
3da42859 DN |
2844 | } else { |
2845 | set_failing_group_stage(0xff, CAL_STAGE_LFIFO, | |
2846 | CAL_SUBSTAGE_READ_LATENCY); | |
2847 | ||
c984278a MV |
2848 | debug_cond(DLEVEL == 2, |
2849 | "%s:%d lfifo: failed at initial read_lat=%u\n", | |
2850 | __func__, __LINE__, gbl->curr_read_lat); | |
3da42859 | 2851 | } |
c984278a MV |
2852 | |
2853 | return found_one; | |
3da42859 DN |
2854 | } |
2855 | ||
c8570afa MV |
2856 | /** |
2857 | * search_window() - Search for the/part of the window with DM/DQS shift | |
2858 | * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift | |
2859 | * @rank_bgn: Rank number | |
2860 | * @write_group: Write Group | |
2861 | * @bgn_curr: Current window begin | |
2862 | * @end_curr: Current window end | |
2863 | * @bgn_best: Current best window begin | |
2864 | * @end_best: Current best window end | |
2865 | * @win_best: Size of the best window | |
2866 | * @new_dqs: New DQS value (only applicable if search_dm = 0). | |
2867 | * | |
2868 | * Search for the/part of the window with DM/DQS shift. | |
2869 | */ | |
2870 | static void search_window(const int search_dm, | |
2871 | const u32 rank_bgn, const u32 write_group, | |
2872 | int *bgn_curr, int *end_curr, int *bgn_best, | |
2873 | int *end_best, int *win_best, int new_dqs) | |
2874 | { | |
2875 | u32 bit_chk; | |
160695d8 | 2876 | const int max = iocfg->io_out1_delay_max - new_dqs; |
c8570afa MV |
2877 | int d, di; |
2878 | ||
2879 | /* Search for the/part of the window with DM/DQS shift. */ | |
2880 | for (di = max; di >= 0; di -= DELTA_D) { | |
2881 | if (search_dm) { | |
2882 | d = di; | |
2883 | scc_mgr_apply_group_dm_out1_delay(d); | |
2884 | } else { | |
2885 | /* For DQS, we go from 0...max */ | |
2886 | d = max - di; | |
2887 | /* | |
139823ec MV |
2888 | * Note: This only shifts DQS, so are we limiting |
2889 | * ourselves to width of DQ unnecessarily. | |
c8570afa MV |
2890 | */ |
2891 | scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, | |
2892 | d + new_dqs); | |
2893 | } | |
2894 | ||
2895 | writel(0, &sdr_scc_mgr->update); | |
2896 | ||
2897 | if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1, | |
2898 | PASS_ALL_BITS, &bit_chk, | |
2899 | 0)) { | |
2900 | /* Set current end of the window. */ | |
2901 | *end_curr = search_dm ? -d : d; | |
2902 | ||
2903 | /* | |
2904 | * If a starting edge of our window has not been seen | |
2905 | * this is our current start of the DM window. | |
2906 | */ | |
160695d8 | 2907 | if (*bgn_curr == iocfg->io_out1_delay_max + 1) |
c8570afa MV |
2908 | *bgn_curr = search_dm ? -d : d; |
2909 | ||
2910 | /* | |
2911 | * If current window is bigger than best seen. | |
2912 | * Set best seen to be current window. | |
2913 | */ | |
2914 | if ((*end_curr - *bgn_curr + 1) > *win_best) { | |
2915 | *win_best = *end_curr - *bgn_curr + 1; | |
2916 | *bgn_best = *bgn_curr; | |
2917 | *end_best = *end_curr; | |
2918 | } | |
2919 | } else { | |
2920 | /* We just saw a failing test. Reset temp edge. */ | |
160695d8 MV |
2921 | *bgn_curr = iocfg->io_out1_delay_max + 1; |
2922 | *end_curr = iocfg->io_out1_delay_max + 1; | |
c8570afa MV |
2923 | |
2924 | /* Early exit is only applicable to DQS. */ | |
2925 | if (search_dm) | |
2926 | continue; | |
2927 | ||
2928 | /* | |
2929 | * Early exit optimization: if the remaining delay | |
2930 | * chain space is less than already seen largest | |
2931 | * window we can exit. | |
2932 | */ | |
160695d8 | 2933 | if (*win_best - 1 > iocfg->io_out1_delay_max - new_dqs - d) |
c8570afa MV |
2934 | break; |
2935 | } | |
2936 | } | |
2937 | } | |
2938 | ||
3da42859 | 2939 | /* |
a386a50e MV |
2940 | * rw_mgr_mem_calibrate_writes_center() - Center all windows |
2941 | * @rank_bgn: Rank number | |
2942 | * @write_group: Write group | |
2943 | * @test_bgn: Rank at which the test begins | |
2944 | * | |
2945 | * Center all windows. Do per-bit-deskew to possibly increase size of | |
3da42859 DN |
2946 | * certain windows. |
2947 | */ | |
3b44f55c MV |
2948 | static int |
2949 | rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, | |
2950 | const u32 test_bgn) | |
3da42859 | 2951 | { |
c8570afa | 2952 | int i; |
3b44f55c MV |
2953 | u32 sticky_bit_chk; |
2954 | u32 min_index; | |
1fa0c8c4 MV |
2955 | int left_edge[rwcfg->mem_dq_per_write_dqs]; |
2956 | int right_edge[rwcfg->mem_dq_per_write_dqs]; | |
3b44f55c MV |
2957 | int mid; |
2958 | int mid_min, orig_mid_min; | |
2959 | int new_dqs, start_dqs; | |
2960 | int dq_margin, dqs_margin, dm_margin; | |
160695d8 MV |
2961 | int bgn_curr = iocfg->io_out1_delay_max + 1; |
2962 | int end_curr = iocfg->io_out1_delay_max + 1; | |
2963 | int bgn_best = iocfg->io_out1_delay_max + 1; | |
2964 | int end_best = iocfg->io_out1_delay_max + 1; | |
3b44f55c | 2965 | int win_best = 0; |
3da42859 | 2966 | |
c4907898 MV |
2967 | int ret; |
2968 | ||
3da42859 DN |
2969 | debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn); |
2970 | ||
2971 | dm_margin = 0; | |
2972 | ||
c6540872 MV |
2973 | start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS | |
2974 | SCC_MGR_IO_OUT1_DELAY_OFFSET) + | |
1fa0c8c4 | 2975 | (rwcfg->mem_dq_per_write_dqs << 2)); |
3da42859 | 2976 | |
3b44f55c | 2977 | /* Per-bit deskew. */ |
3da42859 DN |
2978 | |
2979 | /* | |
3b44f55c | 2980 | * Set the left and right edge of each bit to an illegal value. |
160695d8 | 2981 | * Use (iocfg->io_out1_delay_max + 1) as an illegal value. |
3da42859 DN |
2982 | */ |
2983 | sticky_bit_chk = 0; | |
1fa0c8c4 | 2984 | for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { |
160695d8 MV |
2985 | left_edge[i] = iocfg->io_out1_delay_max + 1; |
2986 | right_edge[i] = iocfg->io_out1_delay_max + 1; | |
3da42859 DN |
2987 | } |
2988 | ||
3b44f55c | 2989 | /* Search for the left edge of the window for each bit. */ |
71120773 | 2990 | search_left_edge(1, rank_bgn, write_group, 0, test_bgn, |
0c4be198 | 2991 | &sticky_bit_chk, |
71120773 | 2992 | left_edge, right_edge, 0); |
3da42859 | 2993 | |
3b44f55c | 2994 | /* Search for the right edge of the window for each bit. */ |
c4907898 MV |
2995 | ret = search_right_edge(1, rank_bgn, write_group, 0, |
2996 | start_dqs, 0, | |
0c4be198 | 2997 | &sticky_bit_chk, |
c4907898 MV |
2998 | left_edge, right_edge, 0); |
2999 | if (ret) { | |
3000 | set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES, | |
3001 | CAL_SUBSTAGE_WRITES_CENTER); | |
d043ee5b | 3002 | return -EINVAL; |
3da42859 DN |
3003 | } |
3004 | ||
afb3eb84 | 3005 | min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min); |
3da42859 | 3006 | |
3b44f55c | 3007 | /* Determine the amount we can change DQS (which is -mid_min). */ |
3da42859 DN |
3008 | orig_mid_min = mid_min; |
3009 | new_dqs = start_dqs; | |
3010 | mid_min = 0; | |
3b44f55c MV |
3011 | debug_cond(DLEVEL == 1, |
3012 | "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n", | |
3013 | __func__, __LINE__, start_dqs, new_dqs, mid_min); | |
3da42859 | 3014 | |
ffb8b66e MV |
3015 | /* Add delay to bring centre of all DQ windows to the same "level". */ |
3016 | center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min, | |
3017 | min_index, 0, &dq_margin, &dqs_margin); | |
3da42859 DN |
3018 | |
3019 | /* Move DQS */ | |
3020 | scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs); | |
1273dd9e | 3021 | writel(0, &sdr_scc_mgr->update); |
3da42859 DN |
3022 | |
3023 | /* Centre DM */ | |
3024 | debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__); | |
3025 | ||
3026 | /* | |
3b44f55c | 3027 | * Set the left and right edge of each bit to an illegal value. |
160695d8 | 3028 | * Use (iocfg->io_out1_delay_max + 1) as an illegal value. |
3da42859 | 3029 | */ |
160695d8 MV |
3030 | left_edge[0] = iocfg->io_out1_delay_max + 1; |
3031 | right_edge[0] = iocfg->io_out1_delay_max + 1; | |
3da42859 | 3032 | |
3b44f55c | 3033 | /* Search for the/part of the window with DM shift. */ |
c8570afa MV |
3034 | search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr, |
3035 | &bgn_best, &end_best, &win_best, 0); | |
3da42859 | 3036 | |
3b44f55c | 3037 | /* Reset DM delay chains to 0. */ |
32675249 | 3038 | scc_mgr_apply_group_dm_out1_delay(0); |
3da42859 DN |
3039 | |
3040 | /* | |
3041 | * Check to see if the current window nudges up aganist 0 delay. | |
3042 | * If so we need to continue the search by shifting DQS otherwise DQS | |
3b44f55c MV |
3043 | * search begins as a new search. |
3044 | */ | |
3da42859 | 3045 | if (end_curr != 0) { |
160695d8 MV |
3046 | bgn_curr = iocfg->io_out1_delay_max + 1; |
3047 | end_curr = iocfg->io_out1_delay_max + 1; | |
3da42859 DN |
3048 | } |
3049 | ||
3b44f55c | 3050 | /* Search for the/part of the window with DQS shifts. */ |
c8570afa MV |
3051 | search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr, |
3052 | &bgn_best, &end_best, &win_best, new_dqs); | |
3da42859 | 3053 | |
3b44f55c MV |
3054 | /* Assign left and right edge for cal and reporting. */ |
3055 | left_edge[0] = -1 * bgn_best; | |
3da42859 DN |
3056 | right_edge[0] = end_best; |
3057 | ||
3b44f55c MV |
3058 | debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", |
3059 | __func__, __LINE__, left_edge[0], right_edge[0]); | |
3da42859 | 3060 | |
3b44f55c | 3061 | /* Move DQS (back to orig). */ |
3da42859 DN |
3062 | scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs); |
3063 | ||
3064 | /* Move DM */ | |
3065 | ||
3b44f55c | 3066 | /* Find middle of window for the DM bit. */ |
3da42859 DN |
3067 | mid = (left_edge[0] - right_edge[0]) / 2; |
3068 | ||
3b44f55c | 3069 | /* Only move right, since we are not moving DQS/DQ. */ |
3da42859 DN |
3070 | if (mid < 0) |
3071 | mid = 0; | |
3072 | ||
3b44f55c | 3073 | /* dm_marign should fail if we never find a window. */ |
3da42859 DN |
3074 | if (win_best == 0) |
3075 | dm_margin = -1; | |
3076 | else | |
3077 | dm_margin = left_edge[0] - mid; | |
3078 | ||
32675249 | 3079 | scc_mgr_apply_group_dm_out1_delay(mid); |
1273dd9e | 3080 | writel(0, &sdr_scc_mgr->update); |
3da42859 | 3081 | |
3b44f55c MV |
3082 | debug_cond(DLEVEL == 2, |
3083 | "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n", | |
3084 | __func__, __LINE__, left_edge[0], right_edge[0], | |
3085 | mid, dm_margin); | |
3086 | /* Export values. */ | |
3da42859 DN |
3087 | gbl->fom_out += dq_margin + dqs_margin; |
3088 | ||
3b44f55c MV |
3089 | debug_cond(DLEVEL == 2, |
3090 | "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n", | |
3091 | __func__, __LINE__, dq_margin, dqs_margin, dm_margin); | |
3da42859 DN |
3092 | |
3093 | /* | |
3094 | * Do not remove this line as it makes sure all of our | |
3095 | * decisions have been applied. | |
3096 | */ | |
1273dd9e | 3097 | writel(0, &sdr_scc_mgr->update); |
3b44f55c | 3098 | |
d043ee5b MV |
3099 | if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0)) |
3100 | return -EINVAL; | |
3101 | ||
3102 | return 0; | |
3da42859 DN |
3103 | } |
3104 | ||
db3a6061 MV |
3105 | /** |
3106 | * rw_mgr_mem_calibrate_writes() - Write Calibration Part One | |
3107 | * @rank_bgn: Rank number | |
3108 | * @group: Read/Write Group | |
3109 | * @test_bgn: Rank at which the test begins | |
3110 | * | |
3111 | * Stage 2: Write Calibration Part One. | |
3112 | * | |
3113 | * This function implements UniPHY calibration Stage 2, as explained in | |
3114 | * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". | |
3115 | */ | |
3116 | static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group, | |
3117 | const u32 test_bgn) | |
3da42859 | 3118 | { |
db3a6061 MV |
3119 | int ret; |
3120 | ||
3121 | /* Update info for sims */ | |
3122 | debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn); | |
3da42859 | 3123 | |
db3a6061 | 3124 | reg_file_set_group(group); |
3da42859 DN |
3125 | reg_file_set_stage(CAL_STAGE_WRITES); |
3126 | reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER); | |
3127 | ||
db3a6061 | 3128 | ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn); |
d043ee5b | 3129 | if (ret) |
db3a6061 | 3130 | set_failing_group_stage(group, CAL_STAGE_WRITES, |
3da42859 | 3131 | CAL_SUBSTAGE_WRITES_CENTER); |
3da42859 | 3132 | |
d043ee5b | 3133 | return ret; |
3da42859 DN |
3134 | } |
3135 | ||
4b0ac26a MV |
3136 | /** |
3137 | * mem_precharge_and_activate() - Precharge all banks and activate | |
3138 | * | |
3139 | * Precharge all banks and activate row 0 in bank "000..." and bank "111...". | |
3140 | */ | |
3da42859 DN |
3141 | static void mem_precharge_and_activate(void) |
3142 | { | |
4b0ac26a | 3143 | int r; |
3da42859 | 3144 | |
1fa0c8c4 | 3145 | for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { |
4b0ac26a | 3146 | /* Set rank. */ |
3da42859 DN |
3147 | set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); |
3148 | ||
4b0ac26a | 3149 | /* Precharge all banks. */ |
1fa0c8c4 | 3150 | writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS | |
1273dd9e | 3151 | RW_MGR_RUN_SINGLE_GROUP_OFFSET); |
3da42859 | 3152 | |
1273dd9e | 3153 | writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0); |
1fa0c8c4 | 3154 | writel(rwcfg->activate_0_and_1_wait1, |
139823ec | 3155 | &sdr_rw_load_jump_mgr_regs->load_jump_add0); |
3da42859 | 3156 | |
1273dd9e | 3157 | writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1); |
1fa0c8c4 | 3158 | writel(rwcfg->activate_0_and_1_wait2, |
139823ec | 3159 | &sdr_rw_load_jump_mgr_regs->load_jump_add1); |
3da42859 | 3160 | |
4b0ac26a | 3161 | /* Activate rows. */ |
1fa0c8c4 | 3162 | writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS | |
1273dd9e | 3163 | RW_MGR_RUN_SINGLE_GROUP_OFFSET); |
3da42859 DN |
3164 | } |
3165 | } | |
3166 | ||
16502a0b MV |
3167 | /** |
3168 | * mem_init_latency() - Configure memory RLAT and WLAT settings | |
3169 | * | |
3170 | * Configure memory RLAT and WLAT parameters. | |
3171 | */ | |
3172 | static void mem_init_latency(void) | |
3da42859 | 3173 | { |
3da42859 | 3174 | /* |
16502a0b MV |
3175 | * For AV/CV, LFIFO is hardened and always runs at full rate |
3176 | * so max latency in AFI clocks, used here, is correspondingly | |
3177 | * smaller. | |
3da42859 | 3178 | */ |
96fd4362 | 3179 | const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1; |
16502a0b | 3180 | u32 rlat, wlat; |
3da42859 | 3181 | |
16502a0b | 3182 | debug("%s:%d\n", __func__, __LINE__); |
3da42859 DN |
3183 | |
3184 | /* | |
16502a0b MV |
3185 | * Read in write latency. |
3186 | * WL for Hard PHY does not include additive latency. | |
3da42859 | 3187 | */ |
16502a0b MV |
3188 | wlat = readl(&data_mgr->t_wl_add); |
3189 | wlat += readl(&data_mgr->mem_t_add); | |
3da42859 | 3190 | |
16502a0b | 3191 | gbl->rw_wl_nop_cycles = wlat - 1; |
3da42859 | 3192 | |
16502a0b MV |
3193 | /* Read in readl latency. */ |
3194 | rlat = readl(&data_mgr->t_rl_add); | |
3da42859 | 3195 | |
16502a0b MV |
3196 | /* Set a pretty high read latency initially. */ |
3197 | gbl->curr_read_lat = rlat + 16; | |
3da42859 DN |
3198 | if (gbl->curr_read_lat > max_latency) |
3199 | gbl->curr_read_lat = max_latency; | |
3200 | ||
1273dd9e | 3201 | writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); |
3da42859 | 3202 | |
16502a0b MV |
3203 | /* Advertise write latency. */ |
3204 | writel(wlat, &phy_mgr_cfg->afi_wlat); | |
3da42859 DN |
3205 | } |
3206 | ||
51cea0b6 MV |
3207 | /** |
3208 | * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings | |
3209 | * | |
3210 | * Set VFIFO and LFIFO to instant-on settings in skip calibration mode. | |
3211 | */ | |
3da42859 DN |
3212 | static void mem_skip_calibrate(void) |
3213 | { | |
5ded7320 MV |
3214 | u32 vfifo_offset; |
3215 | u32 i, j, r; | |
3da42859 DN |
3216 | |
3217 | debug("%s:%d\n", __func__, __LINE__); | |
3218 | /* Need to update every shadow register set used by the interface */ | |
1fa0c8c4 | 3219 | for (r = 0; r < rwcfg->mem_number_of_ranks; |
51cea0b6 | 3220 | r += NUM_RANKS_PER_SHADOW_REG) { |
3da42859 DN |
3221 | /* |
3222 | * Set output phase alignment settings appropriate for | |
3223 | * skip calibration. | |
3224 | */ | |
1fa0c8c4 | 3225 | for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { |
3da42859 | 3226 | scc_mgr_set_dqs_en_phase(i, 0); |
160695d8 MV |
3227 | if (iocfg->dll_chain_length == 6) |
3228 | scc_mgr_set_dqdqs_output_phase(i, 6); | |
3229 | else | |
3230 | scc_mgr_set_dqdqs_output_phase(i, 7); | |
3da42859 DN |
3231 | /* |
3232 | * Case:33398 | |
3233 | * | |
3234 | * Write data arrives to the I/O two cycles before write | |
3235 | * latency is reached (720 deg). | |
3236 | * -> due to bit-slip in a/c bus | |
3237 | * -> to allow board skew where dqs is longer than ck | |
3238 | * -> how often can this happen!? | |
3239 | * -> can claim back some ptaps for high freq | |
3240 | * support if we can relax this, but i digress... | |
3241 | * | |
3242 | * The write_clk leads mem_ck by 90 deg | |
3243 | * The minimum ptap of the OPA is 180 deg | |
3244 | * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay | |
3245 | * The write_clk is always delayed by 2 ptaps | |
3246 | * | |
3247 | * Hence, to make DQS aligned to CK, we need to delay | |
3248 | * DQS by: | |
139823ec MV |
3249 | * (720 - 90 - 180 - 2) * |
3250 | * (360 / iocfg->dll_chain_length) | |
3da42859 | 3251 | * |
160695d8 | 3252 | * Dividing the above by (360 / iocfg->dll_chain_length) |
3da42859 DN |
3253 | * gives us the number of ptaps, which simplies to: |
3254 | * | |
160695d8 | 3255 | * (1.25 * iocfg->dll_chain_length - 2) |
3da42859 | 3256 | */ |
51cea0b6 | 3257 | scc_mgr_set_dqdqs_output_phase(i, |
6d7a3330 | 3258 | ((125 * iocfg->dll_chain_length) / 100) - 2); |
3da42859 | 3259 | } |
1273dd9e MV |
3260 | writel(0xff, &sdr_scc_mgr->dqs_ena); |
3261 | writel(0xff, &sdr_scc_mgr->dqs_io_ena); | |
3da42859 | 3262 | |
1fa0c8c4 | 3263 | for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { |
1273dd9e MV |
3264 | writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | |
3265 | SCC_MGR_GROUP_COUNTER_OFFSET); | |
3da42859 | 3266 | } |
1273dd9e MV |
3267 | writel(0xff, &sdr_scc_mgr->dq_ena); |
3268 | writel(0xff, &sdr_scc_mgr->dm_ena); | |
3269 | writel(0, &sdr_scc_mgr->update); | |
3da42859 DN |
3270 | } |
3271 | ||
3272 | /* Compensate for simulation model behaviour */ | |
1fa0c8c4 | 3273 | for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { |
3da42859 DN |
3274 | scc_mgr_set_dqs_bus_in_delay(i, 10); |
3275 | scc_mgr_load_dqs(i); | |
3276 | } | |
1273dd9e | 3277 | writel(0, &sdr_scc_mgr->update); |
3da42859 DN |
3278 | |
3279 | /* | |
3280 | * ArriaV has hard FIFOs that can only be initialized by incrementing | |
3281 | * in sequencer. | |
3282 | */ | |
96fd4362 | 3283 | vfifo_offset = misccfg->calib_vfifo_offset; |
51cea0b6 | 3284 | for (j = 0; j < vfifo_offset; j++) |
1273dd9e | 3285 | writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy); |
1273dd9e | 3286 | writel(0, &phy_mgr_cmd->fifo_reset); |
3da42859 DN |
3287 | |
3288 | /* | |
51cea0b6 MV |
3289 | * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal |
3290 | * setting from generation-time constant. | |
3da42859 | 3291 | */ |
96fd4362 | 3292 | gbl->curr_read_lat = misccfg->calib_lfifo_offset; |
1273dd9e | 3293 | writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); |
3da42859 DN |
3294 | } |
3295 | ||
3589fbfb MV |
3296 | /** |
3297 | * mem_calibrate() - Memory calibration entry point. | |
3298 | * | |
3299 | * Perform memory calibration. | |
3300 | */ | |
5ded7320 | 3301 | static u32 mem_calibrate(void) |
3da42859 | 3302 | { |
5ded7320 MV |
3303 | u32 i; |
3304 | u32 rank_bgn, sr; | |
3305 | u32 write_group, write_test_bgn; | |
3306 | u32 read_group, read_test_bgn; | |
3307 | u32 run_groups, current_run; | |
3308 | u32 failing_groups = 0; | |
3309 | u32 group_failed = 0; | |
3da42859 | 3310 | |
1fa0c8c4 MV |
3311 | const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width / |
3312 | rwcfg->mem_if_write_dqs_width; | |
33c42bb8 | 3313 | |
3da42859 | 3314 | debug("%s:%d\n", __func__, __LINE__); |
3da42859 | 3315 | |
16502a0b | 3316 | /* Initialize the data settings */ |
3da42859 DN |
3317 | gbl->error_substage = CAL_SUBSTAGE_NIL; |
3318 | gbl->error_stage = CAL_STAGE_NIL; | |
3319 | gbl->error_group = 0xff; | |
3320 | gbl->fom_in = 0; | |
3321 | gbl->fom_out = 0; | |
3322 | ||
16502a0b MV |
3323 | /* Initialize WLAT and RLAT. */ |
3324 | mem_init_latency(); | |
3325 | ||
3326 | /* Initialize bit slips. */ | |
3327 | mem_precharge_and_activate(); | |
3da42859 | 3328 | |
1fa0c8c4 | 3329 | for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { |
1273dd9e MV |
3330 | writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | |
3331 | SCC_MGR_GROUP_COUNTER_OFFSET); | |
fa5d821b MV |
3332 | /* Only needed once to set all groups, pins, DQ, DQS, DM. */ |
3333 | if (i == 0) | |
3334 | scc_mgr_set_hhp_extras(); | |
3335 | ||
c5c5f537 | 3336 | scc_set_bypass_mode(i); |
3da42859 DN |
3337 | } |
3338 | ||
722c9685 | 3339 | /* Calibration is skipped. */ |
3da42859 DN |
3340 | if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) { |
3341 | /* | |
3342 | * Set VFIFO and LFIFO to instant-on settings in skip | |
3343 | * calibration mode. | |
3344 | */ | |
3345 | mem_skip_calibrate(); | |
3da42859 | 3346 | |
722c9685 MV |
3347 | /* |
3348 | * Do not remove this line as it makes sure all of our | |
3349 | * decisions have been applied. | |
3350 | */ | |
3351 | writel(0, &sdr_scc_mgr->update); | |
3352 | return 1; | |
3353 | } | |
3da42859 | 3354 | |
722c9685 MV |
3355 | /* Calibration is not skipped. */ |
3356 | for (i = 0; i < NUM_CALIB_REPEAT; i++) { | |
3357 | /* | |
3358 | * Zero all delay chain/phase settings for all | |
3359 | * groups and all shadow register sets. | |
3360 | */ | |
3361 | scc_mgr_zero_all(); | |
3362 | ||
f085ac3b | 3363 | run_groups = ~0; |
722c9685 MV |
3364 | |
3365 | for (write_group = 0, write_test_bgn = 0; write_group | |
1fa0c8c4 MV |
3366 | < rwcfg->mem_if_write_dqs_width; write_group++, |
3367 | write_test_bgn += rwcfg->mem_dq_per_write_dqs) { | |
c452dcd0 | 3368 | /* Initialize the group failure */ |
722c9685 MV |
3369 | group_failed = 0; |
3370 | ||
3371 | current_run = run_groups & ((1 << | |
3372 | RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1); | |
3373 | run_groups = run_groups >> | |
3374 | RW_MGR_NUM_DQS_PER_WRITE_GROUP; | |
3375 | ||
3376 | if (current_run == 0) | |
3377 | continue; | |
3378 | ||
3379 | writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS | | |
3380 | SCC_MGR_GROUP_COUNTER_OFFSET); | |
3381 | scc_mgr_zero_group(write_group, 0); | |
3382 | ||
33c42bb8 MV |
3383 | for (read_group = write_group * rwdqs_ratio, |
3384 | read_test_bgn = 0; | |
c452dcd0 | 3385 | read_group < (write_group + 1) * rwdqs_ratio; |
33c42bb8 | 3386 | read_group++, |
1fa0c8c4 | 3387 | read_test_bgn += rwcfg->mem_dq_per_read_dqs) { |
33c42bb8 MV |
3388 | if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO) |
3389 | continue; | |
3390 | ||
722c9685 | 3391 | /* Calibrate the VFIFO */ |
33c42bb8 MV |
3392 | if (rw_mgr_mem_calibrate_vfifo(read_group, |
3393 | read_test_bgn)) | |
3394 | continue; | |
3395 | ||
139823ec MV |
3396 | if (!(gbl->phy_debug_mode_flags & |
3397 | PHY_DEBUG_SWEEP_ALL_GROUPS)) | |
33c42bb8 | 3398 | return 0; |
c452dcd0 MV |
3399 | |
3400 | /* The group failed, we're done. */ | |
3401 | goto grp_failed; | |
722c9685 | 3402 | } |
3da42859 | 3403 | |
722c9685 | 3404 | /* Calibrate the output side */ |
c452dcd0 | 3405 | for (rank_bgn = 0, sr = 0; |
1fa0c8c4 | 3406 | rank_bgn < rwcfg->mem_number_of_ranks; |
c452dcd0 MV |
3407 | rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) { |
3408 | if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) | |
3409 | continue; | |
4ac21610 | 3410 | |
c452dcd0 | 3411 | /* Not needed in quick mode! */ |
139823ec MV |
3412 | if (STATIC_CALIB_STEPS & |
3413 | CALIB_SKIP_DELAY_SWEEPS) | |
c452dcd0 | 3414 | continue; |
4ac21610 | 3415 | |
c452dcd0 | 3416 | /* Calibrate WRITEs */ |
db3a6061 | 3417 | if (!rw_mgr_mem_calibrate_writes(rank_bgn, |
139823ec MV |
3418 | write_group, |
3419 | write_test_bgn)) | |
c452dcd0 | 3420 | continue; |
4ac21610 | 3421 | |
c452dcd0 | 3422 | group_failed = 1; |
139823ec MV |
3423 | if (!(gbl->phy_debug_mode_flags & |
3424 | PHY_DEBUG_SWEEP_ALL_GROUPS)) | |
c452dcd0 | 3425 | return 0; |
722c9685 | 3426 | } |
3da42859 | 3427 | |
c452dcd0 MV |
3428 | /* Some group failed, we're done. */ |
3429 | if (group_failed) | |
3430 | goto grp_failed; | |
3431 | ||
3432 | for (read_group = write_group * rwdqs_ratio, | |
3433 | read_test_bgn = 0; | |
3434 | read_group < (write_group + 1) * rwdqs_ratio; | |
3435 | read_group++, | |
1fa0c8c4 | 3436 | read_test_bgn += rwcfg->mem_dq_per_read_dqs) { |
c452dcd0 MV |
3437 | if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) |
3438 | continue; | |
3439 | ||
78cdd7d0 | 3440 | if (!rw_mgr_mem_calibrate_vfifo_end(read_group, |
139823ec | 3441 | read_test_bgn)) |
c452dcd0 MV |
3442 | continue; |
3443 | ||
139823ec MV |
3444 | if (!(gbl->phy_debug_mode_flags & |
3445 | PHY_DEBUG_SWEEP_ALL_GROUPS)) | |
c452dcd0 MV |
3446 | return 0; |
3447 | ||
3448 | /* The group failed, we're done. */ | |
3449 | goto grp_failed; | |
3da42859 DN |
3450 | } |
3451 | ||
c452dcd0 MV |
3452 | /* No group failed, continue as usual. */ |
3453 | continue; | |
3454 | ||
3455 | grp_failed: /* A group failed, increment the counter. */ | |
3456 | failing_groups++; | |
722c9685 MV |
3457 | } |
3458 | ||
3459 | /* | |
3460 | * USER If there are any failing groups then report | |
3461 | * the failure. | |
3462 | */ | |
3463 | if (failing_groups != 0) | |
3464 | return 0; | |
3465 | ||
c50ae303 MV |
3466 | if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO) |
3467 | continue; | |
3468 | ||
722c9685 | 3469 | /* Calibrate the LFIFO */ |
c50ae303 MV |
3470 | if (!rw_mgr_mem_calibrate_lfifo()) |
3471 | return 0; | |
3da42859 DN |
3472 | } |
3473 | ||
3474 | /* | |
3475 | * Do not remove this line as it makes sure all of our decisions | |
3476 | * have been applied. | |
3477 | */ | |
1273dd9e | 3478 | writel(0, &sdr_scc_mgr->update); |
3da42859 DN |
3479 | return 1; |
3480 | } | |
3481 | ||
23a040c0 MV |
3482 | /** |
3483 | * run_mem_calibrate() - Perform memory calibration | |
3484 | * | |
3485 | * This function triggers the entire memory calibration procedure. | |
3486 | */ | |
3487 | static int run_mem_calibrate(void) | |
3da42859 | 3488 | { |
23a040c0 | 3489 | int pass; |
bba77110 | 3490 | u32 ctrl_cfg; |
3da42859 DN |
3491 | |
3492 | debug("%s:%d\n", __func__, __LINE__); | |
3493 | ||
3494 | /* Reset pass/fail status shown on afi_cal_success/fail */ | |
1273dd9e | 3495 | writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status); |
3da42859 | 3496 | |
23a040c0 | 3497 | /* Stop tracking manager. */ |
bba77110 MV |
3498 | ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg); |
3499 | writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK, | |
3500 | &sdr_ctrl->ctrl_cfg); | |
3da42859 | 3501 | |
9fa9c90e | 3502 | phy_mgr_initialize(); |
3da42859 DN |
3503 | rw_mgr_mem_initialize(); |
3504 | ||
23a040c0 | 3505 | /* Perform the actual memory calibration. */ |
3da42859 DN |
3506 | pass = mem_calibrate(); |
3507 | ||
3508 | mem_precharge_and_activate(); | |
1273dd9e | 3509 | writel(0, &phy_mgr_cmd->fifo_reset); |
3da42859 | 3510 | |
23a040c0 MV |
3511 | /* Handoff. */ |
3512 | rw_mgr_mem_handoff(); | |
3da42859 | 3513 | /* |
23a040c0 MV |
3514 | * In Hard PHY this is a 2-bit control: |
3515 | * 0: AFI Mux Select | |
3516 | * 1: DDIO Mux Select | |
3da42859 | 3517 | */ |
23a040c0 | 3518 | writel(0x2, &phy_mgr_cfg->mux_sel); |
3da42859 | 3519 | |
23a040c0 | 3520 | /* Start tracking manager. */ |
bba77110 | 3521 | writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); |
23a040c0 MV |
3522 | |
3523 | return pass; | |
3524 | } | |
3525 | ||
3526 | /** | |
3527 | * debug_mem_calibrate() - Report result of memory calibration | |
3528 | * @pass: Value indicating whether calibration passed or failed | |
3529 | * | |
3530 | * This function reports the results of the memory calibration | |
3531 | * and writes debug information into the register file. | |
3532 | */ | |
3533 | static void debug_mem_calibrate(int pass) | |
3534 | { | |
5ded7320 | 3535 | u32 debug_info; |
3da42859 DN |
3536 | |
3537 | if (pass) { | |
3538 | printf("%s: CALIBRATION PASSED\n", __FILE__); | |
3539 | ||
3540 | gbl->fom_in /= 2; | |
3541 | gbl->fom_out /= 2; | |
3542 | ||
3543 | if (gbl->fom_in > 0xff) | |
3544 | gbl->fom_in = 0xff; | |
3545 | ||
3546 | if (gbl->fom_out > 0xff) | |
3547 | gbl->fom_out = 0xff; | |
3548 | ||
3549 | /* Update the FOM in the register file */ | |
3550 | debug_info = gbl->fom_in; | |
3551 | debug_info |= gbl->fom_out << 8; | |
1273dd9e | 3552 | writel(debug_info, &sdr_reg_file->fom); |
3da42859 | 3553 | |
1273dd9e MV |
3554 | writel(debug_info, &phy_mgr_cfg->cal_debug_info); |
3555 | writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status); | |
3da42859 DN |
3556 | } else { |
3557 | printf("%s: CALIBRATION FAILED\n", __FILE__); | |
3558 | ||
3559 | debug_info = gbl->error_stage; | |
3560 | debug_info |= gbl->error_substage << 8; | |
3561 | debug_info |= gbl->error_group << 16; | |
3562 | ||
1273dd9e MV |
3563 | writel(debug_info, &sdr_reg_file->failing_stage); |
3564 | writel(debug_info, &phy_mgr_cfg->cal_debug_info); | |
3565 | writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status); | |
3da42859 DN |
3566 | |
3567 | /* Update the failing group/stage in the register file */ | |
3568 | debug_info = gbl->error_stage; | |
3569 | debug_info |= gbl->error_substage << 8; | |
3570 | debug_info |= gbl->error_group << 16; | |
1273dd9e | 3571 | writel(debug_info, &sdr_reg_file->failing_stage); |
3da42859 DN |
3572 | } |
3573 | ||
23a040c0 | 3574 | printf("%s: Calibration complete\n", __FILE__); |
3da42859 DN |
3575 | } |
3576 | ||
bb06434b MV |
3577 | /** |
3578 | * hc_initialize_rom_data() - Initialize ROM data | |
3579 | * | |
3580 | * Initialize ROM data. | |
3581 | */ | |
3da42859 DN |
3582 | static void hc_initialize_rom_data(void) |
3583 | { | |
04955cf2 MV |
3584 | unsigned int nelem = 0; |
3585 | const u32 *rom_init; | |
bb06434b | 3586 | u32 i, addr; |
3da42859 | 3587 | |
04955cf2 | 3588 | socfpga_get_seq_inst_init(&rom_init, &nelem); |
c4815f76 | 3589 | addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET; |
04955cf2 MV |
3590 | for (i = 0; i < nelem; i++) |
3591 | writel(rom_init[i], addr + (i << 2)); | |
3da42859 | 3592 | |
04955cf2 | 3593 | socfpga_get_seq_ac_init(&rom_init, &nelem); |
c4815f76 | 3594 | addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET; |
04955cf2 MV |
3595 | for (i = 0; i < nelem; i++) |
3596 | writel(rom_init[i], addr + (i << 2)); | |
3da42859 DN |
3597 | } |
3598 | ||
9c1ab2ca MV |
3599 | /** |
3600 | * initialize_reg_file() - Initialize SDR register file | |
3601 | * | |
3602 | * Initialize SDR register file. | |
3603 | */ | |
3da42859 DN |
3604 | static void initialize_reg_file(void) |
3605 | { | |
3da42859 | 3606 | /* Initialize the register file with the correct data */ |
96fd4362 | 3607 | writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature); |
1273dd9e MV |
3608 | writel(0, &sdr_reg_file->debug_data_addr); |
3609 | writel(0, &sdr_reg_file->cur_stage); | |
3610 | writel(0, &sdr_reg_file->fom); | |
3611 | writel(0, &sdr_reg_file->failing_stage); | |
3612 | writel(0, &sdr_reg_file->debug1); | |
3613 | writel(0, &sdr_reg_file->debug2); | |
3da42859 DN |
3614 | } |
3615 | ||
2ca151f8 MV |
3616 | /** |
3617 | * initialize_hps_phy() - Initialize HPS PHY | |
3618 | * | |
3619 | * Initialize HPS PHY. | |
3620 | */ | |
3da42859 DN |
3621 | static void initialize_hps_phy(void) |
3622 | { | |
5ded7320 | 3623 | u32 reg; |
3da42859 DN |
3624 | /* |
3625 | * Tracking also gets configured here because it's in the | |
3626 | * same register. | |
3627 | */ | |
5ded7320 MV |
3628 | u32 trk_sample_count = 7500; |
3629 | u32 trk_long_idle_sample_count = (10 << 16) | 100; | |
3da42859 DN |
3630 | /* |
3631 | * Format is number of outer loops in the 16 MSB, sample | |
3632 | * count in 16 LSB. | |
3633 | */ | |
3634 | ||
3635 | reg = 0; | |
3636 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2); | |
3637 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1); | |
3638 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1); | |
3639 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1); | |
3640 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0); | |
3641 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1); | |
3642 | /* | |
3643 | * This field selects the intrinsic latency to RDATA_EN/FULL path. | |
3644 | * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles. | |
3645 | */ | |
3646 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0); | |
3647 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET( | |
3648 | trk_sample_count); | |
6cb9f167 | 3649 | writel(reg, &sdr_ctrl->phy_ctrl0); |
3da42859 DN |
3650 | |
3651 | reg = 0; | |
3652 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET( | |
3653 | trk_sample_count >> | |
3654 | SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH); | |
3655 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET( | |
3656 | trk_long_idle_sample_count); | |
6cb9f167 | 3657 | writel(reg, &sdr_ctrl->phy_ctrl1); |
3da42859 DN |
3658 | |
3659 | reg = 0; | |
3660 | reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET( | |
3661 | trk_long_idle_sample_count >> | |
3662 | SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH); | |
6cb9f167 | 3663 | writel(reg, &sdr_ctrl->phy_ctrl2); |
3da42859 DN |
3664 | } |
3665 | ||
880e46f2 MV |
3666 | /** |
3667 | * initialize_tracking() - Initialize tracking | |
3668 | * | |
3669 | * Initialize the register file with usable initial data. | |
3670 | */ | |
3da42859 DN |
3671 | static void initialize_tracking(void) |
3672 | { | |
880e46f2 MV |
3673 | /* |
3674 | * Initialize the register file with the correct data. | |
3675 | * Compute usable version of value in case we skip full | |
3676 | * computation later. | |
3677 | */ | |
139823ec MV |
3678 | writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, |
3679 | iocfg->delay_per_dchain_tap) - 1, | |
880e46f2 MV |
3680 | &sdr_reg_file->dtaps_per_ptap); |
3681 | ||
3682 | /* trk_sample_count */ | |
3683 | writel(7500, &sdr_reg_file->trk_sample_count); | |
3684 | ||
3685 | /* longidle outer loop [15:0] */ | |
3686 | writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle); | |
3da42859 DN |
3687 | |
3688 | /* | |
880e46f2 MV |
3689 | * longidle sample count [31:24] |
3690 | * trfc, worst case of 933Mhz 4Gb [23:16] | |
3691 | * trcd, worst case [15:8] | |
3692 | * vfifo wait [7:0] | |
3da42859 | 3693 | */ |
880e46f2 MV |
3694 | writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0), |
3695 | &sdr_reg_file->delays); | |
3da42859 | 3696 | |
880e46f2 | 3697 | /* mux delay */ |
1fa0c8c4 MV |
3698 | writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) | |
3699 | (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0), | |
880e46f2 MV |
3700 | &sdr_reg_file->trk_rw_mgr_addr); |
3701 | ||
1fa0c8c4 | 3702 | writel(rwcfg->mem_if_read_dqs_width, |
880e46f2 MV |
3703 | &sdr_reg_file->trk_read_dqs_width); |
3704 | ||
3705 | /* trefi [7:0] */ | |
1fa0c8c4 | 3706 | writel((rwcfg->refresh_all << 24) | (1000 << 0), |
880e46f2 | 3707 | &sdr_reg_file->trk_rfsh); |
3da42859 DN |
3708 | } |
3709 | ||
3710 | int sdram_calibration_full(void) | |
3711 | { | |
3712 | struct param_type my_param; | |
3713 | struct gbl_type my_gbl; | |
5ded7320 | 3714 | u32 pass; |
84e0b0cf MV |
3715 | |
3716 | memset(&my_param, 0, sizeof(my_param)); | |
3717 | memset(&my_gbl, 0, sizeof(my_gbl)); | |
3da42859 DN |
3718 | |
3719 | param = &my_param; | |
3720 | gbl = &my_gbl; | |
3721 | ||
d718a26b | 3722 | rwcfg = socfpga_get_sdram_rwmgr_config(); |
10c14261 | 3723 | iocfg = socfpga_get_sdram_io_config(); |
042ff2d0 | 3724 | misccfg = socfpga_get_sdram_misc_config(); |
d718a26b | 3725 | |
3da42859 DN |
3726 | /* Set the calibration enabled by default */ |
3727 | gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT; | |
3728 | /* | |
3729 | * Only sweep all groups (regardless of fail state) by default | |
3730 | * Set enabled read test by default. | |
3731 | */ | |
3732 | #if DISABLE_GUARANTEED_READ | |
3733 | gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ; | |
3734 | #endif | |
3735 | /* Initialize the register file */ | |
3736 | initialize_reg_file(); | |
3737 | ||
3738 | /* Initialize any PHY CSR */ | |
3739 | initialize_hps_phy(); | |
3740 | ||
3741 | scc_mgr_initialize(); | |
3742 | ||
3743 | initialize_tracking(); | |
3744 | ||
3da42859 DN |
3745 | printf("%s: Preparing to start memory calibration\n", __FILE__); |
3746 | ||
3747 | debug("%s:%d\n", __func__, __LINE__); | |
23f62b36 MV |
3748 | debug_cond(DLEVEL == 1, |
3749 | "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ", | |
1fa0c8c4 MV |
3750 | rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm, |
3751 | rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs, | |
3752 | rwcfg->mem_virtual_groups_per_read_dqs, | |
3753 | rwcfg->mem_virtual_groups_per_write_dqs); | |
23f62b36 MV |
3754 | debug_cond(DLEVEL == 1, |
3755 | "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ", | |
1fa0c8c4 MV |
3756 | rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width, |
3757 | rwcfg->mem_data_width, rwcfg->mem_data_mask_width, | |
160695d8 | 3758 | iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap); |
23f62b36 | 3759 | debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u", |
160695d8 | 3760 | iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length); |
139823ec MV |
3761 | debug_cond(DLEVEL == 1, |
3762 | "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ", | |
160695d8 MV |
3763 | iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max, |
3764 | iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max); | |
23f62b36 | 3765 | debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ", |
160695d8 MV |
3766 | iocfg->io_in_delay_max, iocfg->io_out1_delay_max, |
3767 | iocfg->io_out2_delay_max); | |
23f62b36 | 3768 | debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n", |
160695d8 | 3769 | iocfg->dqs_in_reserve, iocfg->dqs_out_reserve); |
3da42859 DN |
3770 | |
3771 | hc_initialize_rom_data(); | |
3772 | ||
3773 | /* update info for sims */ | |
3774 | reg_file_set_stage(CAL_STAGE_NIL); | |
3775 | reg_file_set_group(0); | |
3776 | ||
3777 | /* | |
3778 | * Load global needed for those actions that require | |
3779 | * some dynamic calibration support. | |
3780 | */ | |
3781 | dyn_calib_steps = STATIC_CALIB_STEPS; | |
3782 | /* | |
3783 | * Load global to allow dynamic selection of delay loop settings | |
3784 | * based on calibration mode. | |
3785 | */ | |
3786 | if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS)) | |
3787 | skip_delay_mask = 0xff; | |
3788 | else | |
3789 | skip_delay_mask = 0x0; | |
3790 | ||
3791 | pass = run_mem_calibrate(); | |
23a040c0 | 3792 | debug_mem_calibrate(pass); |
3da42859 DN |
3793 | return pass; |
3794 | } |