[people/ms/u-boot.git] / drivers / ddr / fsl / mpc86xx_ddr.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <asm/io.h>
#include <fsl_ddr_sdram.h>

#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif

void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
			     unsigned int ctrl_num, int step)
{
	unsigned int i;
	struct ccsr_ddr __iomem *ddr;

	switch (ctrl_num) {
	case 0:
		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
		break;
	case 1:
		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
		break;
	default:
		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
		return;
	}

	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
		if (i == 0) {
			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
			out_be32(&ddr->cs0_config, regs->cs[i].config);

		} else if (i == 1) {
			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
			out_be32(&ddr->cs1_config, regs->cs[i].config);

		} else if (i == 2) {
			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
			out_be32(&ddr->cs2_config, regs->cs[i].config);

		} else if (i == 3) {
			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
			out_be32(&ddr->cs3_config, regs->cs[i].config);
		}
	}

	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
	out_be32(&ddr->init_addr, regs->ddr_init_addr);
	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);

	debug("before go\n");

	/*
	 * 200 painful micro-seconds must elapse between
	 * the DDR clock setup and the DDR config enable.
	 */
	udelay(200);
	asm volatile("sync;isync");

	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);

	/*
	 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
	 */
	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
		udelay(10000);		/* throttle polling rate */
	}
}
Commit	Line	Data
46ff4f11 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
5b8031cc	4	* SPDX-License-Identifier: GPL-2.0
46ff4f11 KG	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
5614e71b	9	#include <fsl_ddr_sdram.h>
46ff4f11 KG	10
	11	#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
	12	#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
	13	#endif
	14
	15	void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
c63e1370	16	unsigned int ctrl_num, int step)
46ff4f11 KG	17	{
46ff4f11 KG	18	unsigned int i;
9a17eb5b	19	struct ccsr_ddr __iomem *ddr;
46ff4f11 KG	20
	21	switch (ctrl_num) {
	22	case 0:
5614e71b	23	ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
46ff4f11 KG	24	break;
46ff4f11 KG	25	case 1:
5614e71b	26	ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
46ff4f11 KG	27	break;
	28	default:
	29	printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
	30	return;
	31	}
	32
	33	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
	34	if (i == 0) {
46ff4f11 KG	35	out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
	36	out_be32(&ddr->cs0_config, regs->cs[i].config);
	37
	38	} else if (i == 1) {
	39	out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
	40	out_be32(&ddr->cs1_config, regs->cs[i].config);
	41
	42	} else if (i == 2) {
	43	out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
	44	out_be32(&ddr->cs2_config, regs->cs[i].config);
	45
	46	} else if (i == 3) {
	47	out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
	48	out_be32(&ddr->cs3_config, regs->cs[i].config);
	49	}
	50	}
	51
	52	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
	53	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
	54	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
	55	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
	56	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
e7ee23ec	57	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
46ff4f11	58	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
9a17eb5b	59	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
46ff4f11 KG	60	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
	61	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
	62	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
	63	out_be32(&ddr->init_addr, regs->ddr_init_addr);
	64	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
	65
	66	debug("before go\n");
	67
	68	/*
	69	* 200 painful micro-seconds must elapse between
	70	* the DDR clock setup and the DDR config enable.
	71	*/
	72	udelay(200);
	73	asm volatile("sync;isync");
	74
e7ee23ec	75	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
46ff4f11 KG	76
	77	/*
	78	* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
	79	*/
	80	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
	81	udelay(10000); /* throttle polling rate */
	82	}
	83	}