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58e5e9af | 1 | /* |
34e026f9 | 2 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
58e5e9af KG |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
9ac4ffbd | 10 | #ifdef CONFIG_PPC |
58e5e9af | 11 | #include <asm/fsl_law.h> |
9ac4ffbd | 12 | #endif |
e820a131 | 13 | #include <div64.h> |
58e5e9af | 14 | |
5614e71b | 15 | #include <fsl_ddr.h> |
9a17eb5b | 16 | #include <fsl_immap.h> |
5614e71b | 17 | #include <asm/io.h> |
58e5e9af | 18 | |
e820a131 | 19 | /* To avoid 64-bit full-divides, we factor this here */ |
a2879634 KM |
20 | #define ULL_2E12 2000000000000ULL |
21 | #define UL_5POW12 244140625UL | |
22 | #define UL_2POW13 (1UL << 13) | |
e820a131 | 23 | |
a2879634 | 24 | #define ULL_8FS 0xFFFFFFFFULL |
e820a131 | 25 | |
34e026f9 YS |
26 | u32 fsl_ddr_get_version(void) |
27 | { | |
28 | struct ccsr_ddr __iomem *ddr; | |
29 | u32 ver_major_minor_errata; | |
30 | ||
31 | ddr = (void *)_DDR_ADDR; | |
32 | ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; | |
33 | ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; | |
34 | ||
35 | return ver_major_minor_errata; | |
36 | } | |
37 | ||
58e5e9af | 38 | /* |
905acde2 YS |
39 | * Round up mclk_ps to nearest 1 ps in memory controller code |
40 | * if the error is 0.5ps or more. | |
58e5e9af KG |
41 | * |
42 | * If an imprecise data rate is too high due to rounding error | |
43 | * propagation, compute a suitably rounded mclk_ps to compute | |
44 | * a working memory controller configuration. | |
45 | */ | |
46 | unsigned int get_memory_clk_period_ps(void) | |
47 | { | |
e820a131 KM |
48 | unsigned int data_rate = get_ddr_freq(0); |
49 | unsigned int result; | |
50 | ||
51 | /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ | |
905acde2 | 52 | unsigned long long rem, mclk_ps = ULL_2E12; |
e820a131 KM |
53 | |
54 | /* Now perform the big divide, the result fits in 32-bits */ | |
905acde2 YS |
55 | rem = do_div(mclk_ps, data_rate); |
56 | result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; | |
58e5e9af | 57 | |
905acde2 | 58 | return result; |
58e5e9af KG |
59 | } |
60 | ||
61 | /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ | |
62 | unsigned int picos_to_mclk(unsigned int picos) | |
63 | { | |
e820a131 | 64 | unsigned long long clks, clks_rem; |
905acde2 | 65 | unsigned long data_rate = get_ddr_freq(0); |
58e5e9af | 66 | |
e820a131 | 67 | /* Short circuit for zero picos */ |
58e5e9af KG |
68 | if (!picos) |
69 | return 0; | |
70 | ||
e820a131 | 71 | /* First multiply the time by the data rate (32x32 => 64) */ |
905acde2 | 72 | clks = picos * (unsigned long long)data_rate; |
e820a131 KM |
73 | /* |
74 | * Now divide by 5^12 and track the 32-bit remainder, then divide | |
75 | * by 2*(2^12) using shifts (and updating the remainder). | |
76 | */ | |
a2879634 | 77 | clks_rem = do_div(clks, UL_5POW12); |
905acde2 | 78 | clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; |
e820a131 KM |
79 | clks >>= 13; |
80 | ||
905acde2 YS |
81 | /* If we had a remainder greater than the 1ps error, then round up */ |
82 | if (clks_rem > data_rate) | |
58e5e9af | 83 | clks++; |
58e5e9af | 84 | |
e820a131 | 85 | /* Clamp to the maximum representable value */ |
a2879634 KM |
86 | if (clks > ULL_8FS) |
87 | clks = ULL_8FS; | |
58e5e9af KG |
88 | return (unsigned int) clks; |
89 | } | |
90 | ||
91 | unsigned int mclk_to_picos(unsigned int mclk) | |
92 | { | |
93 | return get_memory_clk_period_ps() * mclk; | |
94 | } | |
95 | ||
9ac4ffbd | 96 | #ifdef CONFIG_PPC |
58e5e9af KG |
97 | void |
98 | __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, | |
a4c66509 | 99 | unsigned int law_memctl, |
58e5e9af KG |
100 | unsigned int ctrl_num) |
101 | { | |
e7563aff KG |
102 | unsigned long long base = memctl_common_params->base_address; |
103 | unsigned long long size = memctl_common_params->total_mem; | |
104 | ||
58e5e9af KG |
105 | /* |
106 | * If no DIMMs on this controller, do not proceed any further. | |
107 | */ | |
108 | if (!memctl_common_params->ndimms_present) { | |
109 | return; | |
110 | } | |
111 | ||
e7563aff KG |
112 | #if !defined(CONFIG_PHYS_64BIT) |
113 | if (base >= CONFIG_MAX_MEM_MAPPED) | |
114 | return; | |
115 | if ((base + size) >= CONFIG_MAX_MEM_MAPPED) | |
116 | size = CONFIG_MAX_MEM_MAPPED - base; | |
117 | #endif | |
a4c66509 YS |
118 | if (set_ddr_laws(base, size, law_memctl) < 0) { |
119 | printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, | |
120 | law_memctl); | |
121 | return ; | |
58e5e9af | 122 | } |
a4c66509 YS |
123 | debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", |
124 | base, size, law_memctl); | |
58e5e9af KG |
125 | } |
126 | ||
127 | __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void | |
128 | fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, | |
129 | unsigned int memctl_interleaved, | |
130 | unsigned int ctrl_num); | |
9ac4ffbd | 131 | #endif |
d9c147f3 | 132 | |
a4c66509 YS |
133 | void fsl_ddr_set_intl3r(const unsigned int granule_size) |
134 | { | |
135 | #ifdef CONFIG_E6500 | |
136 | u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); | |
137 | *mcintl3r = 0x80000000 | (granule_size & 0x1f); | |
138 | debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); | |
139 | #endif | |
140 | } | |
141 | ||
eb539412 YS |
142 | u32 fsl_ddr_get_intl3r(void) |
143 | { | |
144 | u32 val = 0; | |
145 | #ifdef CONFIG_E6500 | |
146 | u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); | |
147 | val = *mcintl3r; | |
148 | #endif | |
149 | return val; | |
150 | } | |
151 | ||
1d71efbb | 152 | void print_ddr_info(unsigned int start_ctrl) |
d9c147f3 | 153 | { |
9a17eb5b YS |
154 | struct ccsr_ddr __iomem *ddr = |
155 | (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); | |
e76cd5d4 | 156 | |
a4c66509 YS |
157 | #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) |
158 | u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); | |
159 | #endif | |
d9c147f3 | 160 | #if (CONFIG_NUM_DDR_CONTROLLERS > 1) |
4e5b1bd0 | 161 | uint32_t cs0_config = ddr_in32(&ddr->cs0_config); |
d9c147f3 | 162 | #endif |
4e5b1bd0 | 163 | uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); |
d9c147f3 PT |
164 | int cas_lat; |
165 | ||
123922b1 | 166 | #if CONFIG_NUM_DDR_CONTROLLERS >= 2 |
1d71efbb YS |
167 | if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || |
168 | (start_ctrl == 1)) { | |
5614e71b | 169 | ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; |
4e5b1bd0 | 170 | sdram_cfg = ddr_in32(&ddr->sdram_cfg); |
123922b1 YS |
171 | } |
172 | #endif | |
173 | #if CONFIG_NUM_DDR_CONTROLLERS >= 3 | |
1d71efbb YS |
174 | if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || |
175 | (start_ctrl == 2)) { | |
5614e71b | 176 | ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; |
4e5b1bd0 | 177 | sdram_cfg = ddr_in32(&ddr->sdram_cfg); |
123922b1 YS |
178 | } |
179 | #endif | |
1d71efbb YS |
180 | |
181 | if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { | |
182 | puts(" (DDR not enabled)\n"); | |
183 | return; | |
184 | } | |
185 | ||
d9c147f3 PT |
186 | puts(" (DDR"); |
187 | switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> | |
188 | SDRAM_CFG_SDRAM_TYPE_SHIFT) { | |
189 | case SDRAM_TYPE_DDR1: | |
190 | puts("1"); | |
191 | break; | |
192 | case SDRAM_TYPE_DDR2: | |
193 | puts("2"); | |
194 | break; | |
195 | case SDRAM_TYPE_DDR3: | |
196 | puts("3"); | |
197 | break; | |
34e026f9 YS |
198 | case SDRAM_TYPE_DDR4: |
199 | puts("4"); | |
200 | break; | |
d9c147f3 PT |
201 | default: |
202 | puts("?"); | |
203 | break; | |
204 | } | |
205 | ||
206 | if (sdram_cfg & SDRAM_CFG_32_BE) | |
207 | puts(", 32-bit"); | |
0b3b1766 PA |
208 | else if (sdram_cfg & SDRAM_CFG_16_BE) |
209 | puts(", 16-bit"); | |
d9c147f3 PT |
210 | else |
211 | puts(", 64-bit"); | |
212 | ||
213 | /* Calculate CAS latency based on timing cfg values */ | |
34e026f9 YS |
214 | cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); |
215 | if (fsl_ddr_get_version() <= 0x40400) | |
216 | cas_lat += 1; | |
217 | else | |
218 | cas_lat += 2; | |
219 | cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; | |
d9c147f3 PT |
220 | printf(", CL=%d", cas_lat >> 1); |
221 | if (cas_lat & 0x1) | |
222 | puts(".5"); | |
223 | ||
224 | if (sdram_cfg & SDRAM_CFG_ECC_EN) | |
225 | puts(", ECC on)"); | |
226 | else | |
227 | puts(", ECC off)"); | |
228 | ||
a4c66509 YS |
229 | #if (CONFIG_NUM_DDR_CONTROLLERS == 3) |
230 | #ifdef CONFIG_E6500 | |
231 | if (*mcintl3r & 0x80000000) { | |
232 | puts("\n"); | |
233 | puts(" DDR Controller Interleaving Mode: "); | |
234 | switch (*mcintl3r & 0x1f) { | |
235 | case FSL_DDR_3WAY_1KB_INTERLEAVING: | |
236 | puts("3-way 1KB"); | |
237 | break; | |
238 | case FSL_DDR_3WAY_4KB_INTERLEAVING: | |
239 | puts("3-way 4KB"); | |
240 | break; | |
241 | case FSL_DDR_3WAY_8KB_INTERLEAVING: | |
242 | puts("3-way 8KB"); | |
243 | break; | |
244 | default: | |
245 | puts("3-way UNKNOWN"); | |
246 | break; | |
247 | } | |
248 | } | |
249 | #endif | |
250 | #endif | |
251 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) | |
1d71efbb | 252 | if ((cs0_config & 0x20000000) && (start_ctrl == 0)) { |
d9c147f3 PT |
253 | puts("\n"); |
254 | puts(" DDR Controller Interleaving Mode: "); | |
255 | ||
256 | switch ((cs0_config >> 24) & 0xf) { | |
6b1e1254 YS |
257 | case FSL_DDR_256B_INTERLEAVING: |
258 | puts("256B"); | |
259 | break; | |
d9c147f3 PT |
260 | case FSL_DDR_CACHE_LINE_INTERLEAVING: |
261 | puts("cache line"); | |
262 | break; | |
263 | case FSL_DDR_PAGE_INTERLEAVING: | |
264 | puts("page"); | |
265 | break; | |
266 | case FSL_DDR_BANK_INTERLEAVING: | |
267 | puts("bank"); | |
268 | break; | |
269 | case FSL_DDR_SUPERBANK_INTERLEAVING: | |
270 | puts("super-bank"); | |
271 | break; | |
272 | default: | |
273 | puts("invalid"); | |
274 | break; | |
275 | } | |
276 | } | |
277 | #endif | |
278 | ||
279 | if ((sdram_cfg >> 8) & 0x7f) { | |
280 | puts("\n"); | |
281 | puts(" DDR Chip-Select Interleaving Mode: "); | |
282 | switch(sdram_cfg >> 8 & 0x7f) { | |
283 | case FSL_DDR_CS0_CS1_CS2_CS3: | |
284 | puts("CS0+CS1+CS2+CS3"); | |
285 | break; | |
286 | case FSL_DDR_CS0_CS1: | |
287 | puts("CS0+CS1"); | |
288 | break; | |
289 | case FSL_DDR_CS2_CS3: | |
290 | puts("CS2+CS3"); | |
291 | break; | |
292 | case FSL_DDR_CS0_CS1_AND_CS2_CS3: | |
293 | puts("CS0+CS1 and CS2+CS3"); | |
294 | break; | |
295 | default: | |
296 | puts("invalid"); | |
297 | break; | |
298 | } | |
299 | } | |
300 | } | |
1d71efbb YS |
301 | |
302 | void __weak detail_board_ddr_info(void) | |
303 | { | |
304 | print_ddr_info(0); | |
305 | } | |
306 | ||
307 | void board_add_ram_info(int use_default) | |
308 | { | |
309 | detail_board_ddr_info(); | |
310 | } |