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6867e19a TFC |
1 | /* |
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | |
3 | * All rights reserved. | |
4 | * | |
5 | * SPDX-License-Identifier: BSD-3-Clause | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/io.h> | |
10 | #include <linux/errno.h> | |
11 | #include <asm/arch/fpga_manager.h> | |
12 | #include <asm/arch/reset_manager.h> | |
13 | #include <asm/arch/system_manager.h> | |
14 | ||
15 | DECLARE_GLOBAL_DATA_PTR; | |
16 | ||
17 | #define FPGA_TIMEOUT_CNT 0x1000000 | |
18 | ||
19 | static struct socfpga_fpga_manager *fpgamgr_regs = | |
20 | (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; | |
21 | static struct socfpga_system_manager *sysmgr_regs = | |
22 | (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; | |
23 | ||
24 | /* Set CD ratio */ | |
25 | static void fpgamgr_set_cd_ratio(unsigned long ratio) | |
26 | { | |
27 | clrsetbits_le32(&fpgamgr_regs->ctrl, | |
28 | 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB, | |
29 | (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); | |
30 | } | |
31 | ||
32 | /* Start the FPGA programming by initialize the FPGA Manager */ | |
33 | static int fpgamgr_program_init(void) | |
34 | { | |
35 | unsigned long msel, i; | |
36 | ||
37 | /* Get the MSEL value */ | |
38 | msel = readl(&fpgamgr_regs->stat); | |
39 | msel &= FPGAMGRREGS_STAT_MSEL_MASK; | |
40 | msel >>= FPGAMGRREGS_STAT_MSEL_LSB; | |
41 | ||
42 | /* | |
43 | * Set the cfg width | |
44 | * If MSEL[3] = 1, cfg width = 32 bit | |
45 | */ | |
46 | if (msel & 0x8) { | |
47 | setbits_le32(&fpgamgr_regs->ctrl, | |
48 | FPGAMGRREGS_CTRL_CFGWDTH_MASK); | |
49 | ||
50 | /* To determine the CD ratio */ | |
51 | /* MSEL[1:0] = 0, CD Ratio = 1 */ | |
52 | if ((msel & 0x3) == 0x0) | |
53 | fpgamgr_set_cd_ratio(CDRATIO_x1); | |
54 | /* MSEL[1:0] = 1, CD Ratio = 4 */ | |
55 | else if ((msel & 0x3) == 0x1) | |
56 | fpgamgr_set_cd_ratio(CDRATIO_x4); | |
57 | /* MSEL[1:0] = 2, CD Ratio = 8 */ | |
58 | else if ((msel & 0x3) == 0x2) | |
59 | fpgamgr_set_cd_ratio(CDRATIO_x8); | |
60 | ||
61 | } else { /* MSEL[3] = 0 */ | |
62 | clrbits_le32(&fpgamgr_regs->ctrl, | |
63 | FPGAMGRREGS_CTRL_CFGWDTH_MASK); | |
64 | ||
65 | /* To determine the CD ratio */ | |
66 | /* MSEL[1:0] = 0, CD Ratio = 1 */ | |
67 | if ((msel & 0x3) == 0x0) | |
68 | fpgamgr_set_cd_ratio(CDRATIO_x1); | |
69 | /* MSEL[1:0] = 1, CD Ratio = 2 */ | |
70 | else if ((msel & 0x3) == 0x1) | |
71 | fpgamgr_set_cd_ratio(CDRATIO_x2); | |
72 | /* MSEL[1:0] = 2, CD Ratio = 4 */ | |
73 | else if ((msel & 0x3) == 0x2) | |
74 | fpgamgr_set_cd_ratio(CDRATIO_x4); | |
75 | } | |
76 | ||
77 | /* To enable FPGA Manager configuration */ | |
78 | clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); | |
79 | ||
80 | /* To enable FPGA Manager drive over configuration line */ | |
81 | setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); | |
82 | ||
83 | /* Put FPGA into reset phase */ | |
84 | setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); | |
85 | ||
86 | /* (1) wait until FPGA enter reset phase */ | |
87 | for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { | |
88 | if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE) | |
89 | break; | |
90 | } | |
91 | ||
92 | /* If not in reset state, return error */ | |
93 | if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) { | |
94 | puts("FPGA: Could not reset\n"); | |
95 | return -1; | |
96 | } | |
97 | ||
98 | /* Release FPGA from reset phase */ | |
99 | clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); | |
100 | ||
101 | /* (2) wait until FPGA enter configuration phase */ | |
102 | for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { | |
103 | if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE) | |
104 | break; | |
105 | } | |
106 | ||
107 | /* If not in configuration state, return error */ | |
108 | if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) { | |
109 | puts("FPGA: Could not configure\n"); | |
110 | return -2; | |
111 | } | |
112 | ||
113 | /* Clear all interrupts in CB Monitor */ | |
114 | writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi); | |
115 | ||
116 | /* Enable AXI configuration */ | |
117 | setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
122 | /* Ensure the FPGA entering config done */ | |
123 | static int fpgamgr_program_poll_cd(void) | |
124 | { | |
125 | const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | | |
126 | FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; | |
127 | unsigned long reg, i; | |
128 | ||
129 | /* (3) wait until full config done */ | |
130 | for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { | |
131 | reg = readl(&fpgamgr_regs->gpio_ext_porta); | |
132 | ||
133 | /* Config error */ | |
134 | if (!(reg & mask)) { | |
135 | printf("FPGA: Configuration error.\n"); | |
136 | return -3; | |
137 | } | |
138 | ||
139 | /* Config done without error */ | |
140 | if (reg & mask) | |
141 | break; | |
142 | } | |
143 | ||
144 | /* Timeout happened, return error */ | |
145 | if (i == FPGA_TIMEOUT_CNT) { | |
146 | printf("FPGA: Timeout waiting for program.\n"); | |
147 | return -4; | |
148 | } | |
149 | ||
150 | /* Disable AXI configuration */ | |
151 | clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | /* Ensure the FPGA entering init phase */ | |
157 | static int fpgamgr_program_poll_initphase(void) | |
158 | { | |
159 | unsigned long i; | |
160 | ||
161 | /* Additional clocks for the CB to enter initialization phase */ | |
162 | if (fpgamgr_dclkcnt_set(0x4)) | |
163 | return -5; | |
164 | ||
165 | /* (4) wait until FPGA enter init phase or user mode */ | |
166 | for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { | |
167 | if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) | |
168 | break; | |
169 | if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) | |
170 | break; | |
171 | } | |
172 | ||
173 | /* If not in configuration state, return error */ | |
174 | if (i == FPGA_TIMEOUT_CNT) | |
175 | return -6; | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | /* Ensure the FPGA entering user mode */ | |
181 | static int fpgamgr_program_poll_usermode(void) | |
182 | { | |
183 | unsigned long i; | |
184 | ||
185 | /* Additional clocks for the CB to exit initialization phase */ | |
186 | if (fpgamgr_dclkcnt_set(0x5000)) | |
187 | return -7; | |
188 | ||
189 | /* (5) wait until FPGA enter user mode */ | |
190 | for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { | |
191 | if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) | |
192 | break; | |
193 | } | |
194 | /* If not in configuration state, return error */ | |
195 | if (i == FPGA_TIMEOUT_CNT) | |
196 | return -8; | |
197 | ||
198 | /* To release FPGA Manager drive over configuration line */ | |
199 | clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | /* | |
205 | * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. | |
206 | * Return 0 for sucess, non-zero for error. | |
207 | */ | |
208 | int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) | |
209 | { | |
210 | unsigned long status; | |
211 | ||
212 | if ((uint32_t)rbf_data & 0x3) { | |
213 | puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); | |
214 | return -EINVAL; | |
215 | } | |
216 | ||
217 | /* Prior programming the FPGA, all bridges need to be shut off */ | |
218 | ||
219 | /* Disable all signals from hps peripheral controller to fpga */ | |
220 | writel(0, &sysmgr_regs->fpgaintfgrp_module); | |
221 | ||
222 | /* Disable all signals from FPGA to HPS SDRAM */ | |
223 | #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 | |
224 | writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); | |
225 | ||
226 | /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ | |
227 | socfpga_bridges_reset(1); | |
228 | ||
229 | /* Unmap the bridges from NIC-301 */ | |
230 | writel(0x1, SOCFPGA_L3REGS_ADDRESS); | |
231 | ||
232 | /* Initialize the FPGA Manager */ | |
233 | status = fpgamgr_program_init(); | |
234 | if (status) | |
235 | return status; | |
236 | ||
237 | /* Write the RBF data to FPGA Manager */ | |
238 | fpgamgr_program_write(rbf_data, rbf_size); | |
239 | ||
240 | /* Ensure the FPGA entering config done */ | |
241 | status = fpgamgr_program_poll_cd(); | |
242 | if (status) | |
243 | return status; | |
244 | ||
245 | /* Ensure the FPGA entering init phase */ | |
246 | status = fpgamgr_program_poll_initphase(); | |
247 | if (status) | |
248 | return status; | |
249 | ||
250 | /* Ensure the FPGA entering user mode */ | |
251 | return fpgamgr_program_poll_usermode(); | |
252 | } |