[people/ms/u-boot.git] / drivers / fpga / xilinx.c

/*
 * (C) Copyright 2012-2013, Xilinx, Michal Simek
 *
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 * Keith Outwater, keith_outwater@mvis.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 *  Xilinx FPGA support
 */

#include <common.h>
#include <fpga.h>
#include <virtex2.h>
#include <spartan2.h>
#include <spartan3.h>
#include <zynqpl.h>

/* Local Static Functions */
static int xilinx_validate(xilinx_desc *desc, char *fn);

/* ------------------------------------------------------------------------- */

int fpga_is_partial_data(int devnum, size_t img_len)
{
	const fpga_desc * const desc = fpga_get_desc(devnum);
	xilinx_desc *desc_xilinx = desc->devdesc;

	/* Check datasize against FPGA size */
	if (img_len >= desc_xilinx->size)
		return 0;

	/* datasize is smaller, must be partial data */
	return 1;
}

int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
		       bitstream_type bstype)
{
	unsigned int length;
	unsigned int swapsize;
	unsigned char *dataptr;
	unsigned int i;
	const fpga_desc *desc;
	xilinx_desc *xdesc;

	dataptr = (unsigned char *)fpgadata;
	/* Find out fpga_description */
	desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
	/* Assign xilinx device description */
	xdesc = desc->devdesc;

	/* skip the first bytes of the bitsteam, their meaning is unknown */
	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	dataptr += length;

	/* get design name (identifier, length, string) */
	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	if (*dataptr++ != 0x61) {
		debug("%s: Design name id not recognized in bitstream\n",
		      __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	printf("  design filename = \"%s\"\n", dataptr);
	dataptr += length;

	/* get part number (identifier, length, string) */
	if (*dataptr++ != 0x62) {
		printf("%s: Part number id not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;

	if (xdesc->name) {
		i = (ulong)strstr((char *)dataptr, xdesc->name);
		if (!i) {
			printf("%s: Wrong bitstream ID for this device\n",
			       __func__);
			printf("%s: Bitstream ID %s, current device ID %d/%s\n",
			       __func__, dataptr, devnum, xdesc->name);
			return FPGA_FAIL;
		}
	} else {
		printf("%s: Please fill correct device ID to xilinx_desc\n",
		       __func__);
	}
	printf("  part number = \"%s\"\n", dataptr);
	dataptr += length;

	/* get date (identifier, length, string) */
	if (*dataptr++ != 0x63) {
		printf("%s: Date identifier not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr += 2;
	printf("  date = \"%s\"\n", dataptr);
	dataptr += length;

	/* get time (identifier, length, string) */
	if (*dataptr++ != 0x64) {
		printf("%s: Time identifier not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr += 2;
	printf("  time = \"%s\"\n", dataptr);
	dataptr += length;

	/* get fpga data length (identifier, length) */
	if (*dataptr++ != 0x65) {
		printf("%s: Data length id not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}
	swapsize = ((unsigned int) *dataptr << 24) +
		   ((unsigned int) *(dataptr + 1) << 16) +
		   ((unsigned int) *(dataptr + 2) << 8) +
		   ((unsigned int) *(dataptr + 3));
	dataptr += 4;
	printf("  bytes in bitstream = %d\n", swapsize);

	return fpga_load(devnum, dataptr, swapsize, bstype);
}

int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
		bitstream_type bstype)
{
	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->load) {
		printf("%s: Missing load operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->load(desc, buf, bsize, bstype);
}

#if defined(CONFIG_CMD_FPGA_LOADFS)
int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
		   fpga_fs_info *fpga_fsinfo)
{
	if (!xilinx_validate(desc, (char *)__func__)) {
		printf("%s: Invalid device descriptor\n", __func__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->loadfs) {
		printf("%s: Missing loadfs operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
}
#endif

int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->dump) {
		printf("%s: Missing dump operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->dump(desc, buf, bsize);
}

int xilinx_info(xilinx_desc *desc)
{
	int ret_val = FPGA_FAIL;

	if (xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("Family:        \t");
		switch (desc->family) {
		case xilinx_spartan2:
			printf ("Spartan-II\n");
			break;
		case xilinx_spartan3:
			printf ("Spartan-III\n");
			break;
		case xilinx_virtex2:
			printf ("Virtex-II\n");
			break;
		case xilinx_zynq:
			printf("Zynq PL\n");
			break;
		case xilinx_zynqmp:
			printf("ZynqMP PL\n");
			break;
			/* Add new family types here */
		default:
			printf ("Unknown family type, %d\n", desc->family);
		}

		printf ("Interface type:\t");
		switch (desc->iface) {
		case slave_serial:
			printf ("Slave Serial\n");
			break;
		case master_serial:	/* Not used */
			printf ("Master Serial\n");
			break;
		case slave_parallel:
			printf ("Slave Parallel\n");
			break;
		case jtag_mode:		/* Not used */
			printf ("JTAG Mode\n");
			break;
		case slave_selectmap:
			printf ("Slave SelectMap Mode\n");
			break;
		case master_selectmap:
			printf ("Master SelectMap Mode\n");
			break;
		case devcfg:
			printf("Device configuration interface (Zynq)\n");
			break;
		case csu_dma:
			printf("csu_dma configuration interface (ZynqMP)\n");
			break;
			/* Add new interface types here */
		default:
			printf ("Unsupported interface type, %d\n", desc->iface);
		}

		printf("Device Size:   \t%zd bytes\n"
		       "Cookie:        \t0x%x (%d)\n",
		       desc->size, desc->cookie, desc->cookie);
		if (desc->name)
			printf("Device name:   \t%s\n", desc->name);

		if (desc->iface_fns)
			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
		else
			printf ("No Device Function Table.\n");

		if (desc->operations && desc->operations->info)
			desc->operations->info(desc);

		ret_val = FPGA_SUCCESS;
	} else {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
	}

	return ret_val;
}

/* ------------------------------------------------------------------------- */

static int xilinx_validate(xilinx_desc *desc, char *fn)
{
	int ret_val = false;

	if (desc) {
		if ((desc->family > min_xilinx_type) &&
			(desc->family < max_xilinx_type)) {
			if ((desc->iface > min_xilinx_iface_type) &&
				(desc->iface < max_xilinx_iface_type)) {
				if (desc->size) {
					ret_val = true;
				} else
					printf ("%s: NULL part size\n", fn);
			} else
				printf ("%s: Invalid Interface type, %d\n",
						fn, desc->iface);
		} else
			printf ("%s: Invalid family type, %d\n", fn, desc->family);
	} else
		printf ("%s: NULL descriptor!\n", fn);

	return ret_val;
}
Commit	Line	Data
5d3207da	1	/*
d5dae85f MS	2	* (C) Copyright 2012-2013, Xilinx, Michal Simek
d5dae85f MS	3	*
5d3207da WD	4	* (C) Copyright 2002
	5	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	6	* Keith Outwater, keith_outwater@mvis.com
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
5d3207da WD	9	*/
	10
	11	/*
	12	* Xilinx FPGA support
	13	*/
	14
	15	#include <common.h>
6631db47	16	#include <fpga.h>
5d3207da WD	17	#include <virtex2.h>
5d3207da WD	18	#include <spartan2.h>
875c7893	19	#include <spartan3.h>
d5dae85f	20	#include <zynqpl.h>
5d3207da	21
5d3207da	22	/* Local Static Functions */
f8c1be98	23	static int xilinx_validate(xilinx_desc desc, char fn);
5d3207da WD	24
	25	/* ------------------------------------------------------------------------- */
	26
8b93a92f GS	27	int fpga_is_partial_data(int devnum, size_t img_len)
	28	{
	29	const fpga_desc * const desc = fpga_get_desc(devnum);
	30	xilinx_desc *desc_xilinx = desc->devdesc;
	31
	32	/* Check datasize against FPGA size */
	33	if (img_len >= desc_xilinx->size)
	34	return 0;
	35
	36	/* datasize is smaller, must be partial data */
	37	return 1;
	38	}
	39
7a78bd26 MS	40	int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
7a78bd26 MS	41	bitstream_type bstype)
52c20644 MS	42	{
	43	unsigned int length;
	44	unsigned int swapsize;
52c20644 MS	45	unsigned char *dataptr;
52c20644 MS	46	unsigned int i;
6631db47	47	const fpga_desc *desc;
f8c1be98	48	xilinx_desc *xdesc;
52c20644 MS	49
52c20644 MS	50	dataptr = (unsigned char *)fpgadata;
6631db47 MS	51	/* Find out fpga_description */
	52	desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
	53	/* Assign xilinx device description */
	54	xdesc = desc->devdesc;
52c20644 MS	55
	56	/* skip the first bytes of the bitsteam, their meaning is unknown */
	57	length = (dataptr << 8) + (dataptr + 1);
	58	dataptr += 2;
	59	dataptr += length;
	60
	61	/* get design name (identifier, length, string) */
	62	length = (dataptr << 8) + (dataptr + 1);
	63	dataptr += 2;
	64	if (*dataptr++ != 0x61) {
	65	debug("%s: Design name id not recognized in bitstream\n",
	66	__func__);
	67	return FPGA_FAIL;
	68	}
	69
	70	length = (dataptr << 8) + (dataptr + 1);
	71	dataptr += 2;
d863909f SDPP	72	printf(" design filename = \"%s\"\n", dataptr);
d863909f SDPP	73	dataptr += length;
52c20644 MS	74
	75	/* get part number (identifier, length, string) */
	76	if (*dataptr++ != 0x62) {
	77	printf("%s: Part number id not recognized in bitstream\n",
	78	__func__);
	79	return FPGA_FAIL;
	80	}
	81
	82	length = (dataptr << 8) + (dataptr + 1);
	83	dataptr += 2;
6631db47 MS	84
6631db47 MS	85	if (xdesc->name) {
d863909f	86	i = (ulong)strstr((char *)dataptr, xdesc->name);
f7213267	87	if (!i) {
6631db47 MS	88	printf("%s: Wrong bitstream ID for this device\n",
	89	__func__);
	90	printf("%s: Bitstream ID %s, current device ID %d/%s\n",
d863909f	91	__func__, dataptr, devnum, xdesc->name);
6631db47 MS	92	return FPGA_FAIL;
	93	}
	94	} else {
f8c1be98	95	printf("%s: Please fill correct device ID to xilinx_desc\n",
6631db47 MS	96	__func__);
6631db47 MS	97	}
d863909f SDPP	98	printf(" part number = \"%s\"\n", dataptr);
d863909f SDPP	99	dataptr += length;
52c20644 MS	100
	101	/* get date (identifier, length, string) */
	102	if (*dataptr++ != 0x63) {
	103	printf("%s: Date identifier not recognized in bitstream\n",
	104	__func__);
	105	return FPGA_FAIL;
	106	}
	107
	108	length = (dataptr << 8) + (dataptr+1);
	109	dataptr += 2;
d863909f SDPP	110	printf(" date = \"%s\"\n", dataptr);
d863909f SDPP	111	dataptr += length;
52c20644 MS	112
	113	/* get time (identifier, length, string) */
	114	if (*dataptr++ != 0x64) {
	115	printf("%s: Time identifier not recognized in bitstream\n",
	116	__func__);
	117	return FPGA_FAIL;
	118	}
	119
	120	length = (dataptr << 8) + (dataptr+1);
	121	dataptr += 2;
d863909f SDPP	122	printf(" time = \"%s\"\n", dataptr);
d863909f SDPP	123	dataptr += length;
52c20644 MS	124
	125	/* get fpga data length (identifier, length) */
	126	if (*dataptr++ != 0x65) {
	127	printf("%s: Data length id not recognized in bitstream\n",
	128	__func__);
	129	return FPGA_FAIL;
	130	}
	131	swapsize = ((unsigned int) *dataptr << 24) +
	132	((unsigned int) *(dataptr + 1) << 16) +
	133	((unsigned int) *(dataptr + 2) << 8) +
	134	((unsigned int) *(dataptr + 3));
	135	dataptr += 4;
	136	printf(" bytes in bitstream = %d\n", swapsize);
	137
7a78bd26	138	return fpga_load(devnum, dataptr, swapsize, bstype);
52c20644 MS	139	}
52c20644 MS	140
7a78bd26 MS	141	int xilinx_load(xilinx_desc desc, const void buf, size_t bsize,
7a78bd26 MS	142	bitstream_type bstype)
5d3207da	143	{
77ddac94	144	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da	145	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
14cfc4f3 MS	146	return FPGA_FAIL;
14cfc4f3 MS	147	}
5d3207da	148
6cd68c81 MS	149	if (!desc->operations \|\| !desc->operations->load) {
	150	printf("%s: Missing load operation\n", __func__);
	151	return FPGA_FAIL;
	152	}
	153
7a78bd26	154	return desc->operations->load(desc, buf, bsize, bstype);
5d3207da WD	155	}
5d3207da WD	156
1a897668 SDPP	157	#if defined(CONFIG_CMD_FPGA_LOADFS)
	158	int xilinx_loadfs(xilinx_desc desc, const void buf, size_t bsize,
	159	fpga_fs_info *fpga_fsinfo)
	160	{
	161	if (!xilinx_validate(desc, (char *)__func__)) {
	162	printf("%s: Invalid device descriptor\n", __func__);
	163	return FPGA_FAIL;
	164	}
	165
6cd68c81 MS	166	if (!desc->operations \|\| !desc->operations->loadfs) {
6cd68c81 MS	167	printf("%s: Missing loadfs operation\n", __func__);
1a897668	168	return FPGA_FAIL;
6cd68c81	169	}
1a897668 SDPP	170
	171	return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
	172	}
	173	#endif
	174
f8c1be98	175	int xilinx_dump(xilinx_desc desc, const void buf, size_t bsize)
5d3207da	176	{
77ddac94	177	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da	178	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
14cfc4f3 MS	179	return FPGA_FAIL;
14cfc4f3 MS	180	}
5d3207da	181
6cd68c81 MS	182	if (!desc->operations \|\| !desc->operations->dump) {
	183	printf("%s: Missing dump operation\n", __func__);
	184	return FPGA_FAIL;
	185	}
	186
14cfc4f3	187	return desc->operations->dump(desc, buf, bsize);
5d3207da WD	188	}
5d3207da WD	189
f8c1be98	190	int xilinx_info(xilinx_desc *desc)
5d3207da WD	191	{
	192	int ret_val = FPGA_FAIL;
	193
77ddac94	194	if (xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da WD	195	printf ("Family: \t");
5d3207da WD	196	switch (desc->family) {
b625b9ae	197	case xilinx_spartan2:
5d3207da WD	198	printf ("Spartan-II\n");
5d3207da WD	199	break;
2a6e3869	200	case xilinx_spartan3:
875c7893 WD	201	printf ("Spartan-III\n");
875c7893 WD	202	break;
d9071ce0	203	case xilinx_virtex2:
5d3207da WD	204	printf ("Virtex-II\n");
5d3207da WD	205	break;
d5dae85f MS	206	case xilinx_zynq:
	207	printf("Zynq PL\n");
	208	break;
6b245014 SDPP	209	case xilinx_zynqmp:
	210	printf("ZynqMP PL\n");
	211	break;
5d3207da WD	212	/* Add new family types here */
	213	default:
	214	printf ("Unknown family type, %d\n", desc->family);
	215	}
	216
	217	printf ("Interface type:\t");
	218	switch (desc->iface) {
	219	case slave_serial:
	220	printf ("Slave Serial\n");
	221	break;
	222	case master_serial: /* Not used */
	223	printf ("Master Serial\n");
	224	break;
	225	case slave_parallel:
	226	printf ("Slave Parallel\n");
	227	break;
	228	case jtag_mode: /* Not used */
	229	printf ("JTAG Mode\n");
	230	break;
	231	case slave_selectmap:
	232	printf ("Slave SelectMap Mode\n");
	233	break;
	234	case master_selectmap:
	235	printf ("Master SelectMap Mode\n");
	236	break;
d5dae85f MS	237	case devcfg:
	238	printf("Device configuration interface (Zynq)\n");
	239	break;
6b245014 SDPP	240	case csu_dma:
	241	printf("csu_dma configuration interface (ZynqMP)\n");
	242	break;
5d3207da WD	243	/* Add new interface types here */
	244	default:
	245	printf ("Unsupported interface type, %d\n", desc->iface);
	246	}
	247
ddc94378 SG	248	printf("Device Size: \t%zd bytes\n"
	249	"Cookie: \t0x%x (%d)\n",
	250	desc->size, desc->cookie, desc->cookie);
6631db47 MS	251	if (desc->name)
6631db47 MS	252	printf("Device name: \t%s\n", desc->name);
5d3207da	253
e136eaeb	254	if (desc->iface_fns)
5d3207da	255	printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
e136eaeb	256	else
5d3207da WD	257	printf ("No Device Function Table.\n");
5d3207da WD	258
e136eaeb MS	259	if (desc->operations && desc->operations->info)
	260	desc->operations->info(desc);
	261
5d3207da WD	262	ret_val = FPGA_SUCCESS;
	263	} else {
	264	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
	265	}
	266
	267	return ret_val;
	268	}
	269
5d3207da WD	270	/* ------------------------------------------------------------------------- */
5d3207da WD	271
f8c1be98	272	static int xilinx_validate(xilinx_desc desc, char fn)
5d3207da	273	{
472d5460	274	int ret_val = false;
5d3207da WD	275
	276	if (desc) {
	277	if ((desc->family > min_xilinx_type) &&
	278	(desc->family < max_xilinx_type)) {
	279	if ((desc->iface > min_xilinx_iface_type) &&
	280	(desc->iface < max_xilinx_iface_type)) {
	281	if (desc->size) {
472d5460	282	ret_val = true;
5d3207da WD	283	} else
	284	printf ("%s: NULL part size\n", fn);
	285	} else
	286	printf ("%s: Invalid Interface type, %d\n",
	287	fn, desc->iface);
	288	} else
	289	printf ("%s: Invalid family type, %d\n", fn, desc->family);
	290	} else
	291	printf ("%s: NULL descriptor!\n", fn);
	292
	293	return ret_val;
	294	}