[people/ms/u-boot.git] / drivers / fpga / xilinx.c

/*
 * (C) Copyright 2012-2013, Xilinx, Michal Simek
 *
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 * Keith Outwater, keith_outwater@mvis.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 *  Xilinx FPGA support
 */

#include <common.h>
#include <fpga.h>
#include <virtex2.h>
#include <spartan2.h>
#include <spartan3.h>
#include <zynqpl.h>

/* Local Static Functions */
static int xilinx_validate(xilinx_desc *desc, char *fn);

/* ------------------------------------------------------------------------- */

int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
		       bitstream_type bstype)
{
	unsigned int length;
	unsigned int swapsize;
	unsigned char *dataptr;
	unsigned int i;
	const fpga_desc *desc;
	xilinx_desc *xdesc;

	dataptr = (unsigned char *)fpgadata;
	/* Find out fpga_description */
	desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
	/* Assign xilinx device description */
	xdesc = desc->devdesc;

	/* skip the first bytes of the bitsteam, their meaning is unknown */
	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	dataptr += length;

	/* get design name (identifier, length, string) */
	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	if (*dataptr++ != 0x61) {
		debug("%s: Design name id not recognized in bitstream\n",
		      __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	printf("  design filename = \"%s\"\n", dataptr);
	dataptr += length;

	/* get part number (identifier, length, string) */
	if (*dataptr++ != 0x62) {
		printf("%s: Part number id not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;

	if (xdesc->name) {
		i = (ulong)strstr((char *)dataptr, xdesc->name);
		if (!i) {
			printf("%s: Wrong bitstream ID for this device\n",
			       __func__);
			printf("%s: Bitstream ID %s, current device ID %d/%s\n",
			       __func__, dataptr, devnum, xdesc->name);
			return FPGA_FAIL;
		}
	} else {
		printf("%s: Please fill correct device ID to xilinx_desc\n",
		       __func__);
	}
	printf("  part number = \"%s\"\n", dataptr);
	dataptr += length;

	/* get date (identifier, length, string) */
	if (*dataptr++ != 0x63) {
		printf("%s: Date identifier not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr += 2;
	printf("  date = \"%s\"\n", dataptr);
	dataptr += length;

	/* get time (identifier, length, string) */
	if (*dataptr++ != 0x64) {
		printf("%s: Time identifier not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr += 2;
	printf("  time = \"%s\"\n", dataptr);
	dataptr += length;

	/* get fpga data length (identifier, length) */
	if (*dataptr++ != 0x65) {
		printf("%s: Data length id not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}
	swapsize = ((unsigned int) *dataptr << 24) +
		   ((unsigned int) *(dataptr + 1) << 16) +
		   ((unsigned int) *(dataptr + 2) << 8) +
		   ((unsigned int) *(dataptr + 3));
	dataptr += 4;
	printf("  bytes in bitstream = %d\n", swapsize);

	return fpga_load(devnum, dataptr, swapsize, bstype);
}

int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
		bitstream_type bstype)
{
	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->load) {
		printf("%s: Missing load operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->load(desc, buf, bsize, bstype);
}

#if defined(CONFIG_CMD_FPGA_LOADFS)
int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
		   fpga_fs_info *fpga_fsinfo)
{
	if (!xilinx_validate(desc, (char *)__func__)) {
		printf("%s: Invalid device descriptor\n", __func__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->loadfs) {
		printf("%s: Missing loadfs operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
}
#endif

int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->dump) {
		printf("%s: Missing dump operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->dump(desc, buf, bsize);
}

int xilinx_info(xilinx_desc *desc)
{
	int ret_val = FPGA_FAIL;

	if (xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("Family:        \t");
		switch (desc->family) {
		case xilinx_spartan2:
			printf ("Spartan-II\n");
			break;
		case xilinx_spartan3:
			printf ("Spartan-III\n");
			break;
		case xilinx_virtex2:
			printf ("Virtex-II\n");
			break;
		case xilinx_zynq:
			printf("Zynq PL\n");
			break;
		case xilinx_zynqmp:
			printf("ZynqMP PL\n");
			break;
			/* Add new family types here */
		default:
			printf ("Unknown family type, %d\n", desc->family);
		}

		printf ("Interface type:\t");
		switch (desc->iface) {
		case slave_serial:
			printf ("Slave Serial\n");
			break;
		case master_serial:	/* Not used */
			printf ("Master Serial\n");
			break;
		case slave_parallel:
			printf ("Slave Parallel\n");
			break;
		case jtag_mode:		/* Not used */
			printf ("JTAG Mode\n");
			break;
		case slave_selectmap:
			printf ("Slave SelectMap Mode\n");
			break;
		case master_selectmap:
			printf ("Master SelectMap Mode\n");
			break;
		case devcfg:
			printf("Device configuration interface (Zynq)\n");
			break;
		case csu_dma:
			printf("csu_dma configuration interface (ZynqMP)\n");
			break;
			/* Add new interface types here */
		default:
			printf ("Unsupported interface type, %d\n", desc->iface);
		}

		printf("Device Size:   \t%zd bytes\n"
		       "Cookie:        \t0x%x (%d)\n",
		       desc->size, desc->cookie, desc->cookie);
		if (desc->name)
			printf("Device name:   \t%s\n", desc->name);

		if (desc->iface_fns)
			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
		else
			printf ("No Device Function Table.\n");

		if (desc->operations && desc->operations->info)
			desc->operations->info(desc);

		ret_val = FPGA_SUCCESS;
	} else {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
	}

	return ret_val;
}

/* ------------------------------------------------------------------------- */

static int xilinx_validate(xilinx_desc *desc, char *fn)
{
	int ret_val = false;

	if (desc) {
		if ((desc->family > min_xilinx_type) &&
			(desc->family < max_xilinx_type)) {
			if ((desc->iface > min_xilinx_iface_type) &&
				(desc->iface < max_xilinx_iface_type)) {
				if (desc->size) {
					ret_val = true;
				} else
					printf ("%s: NULL part size\n", fn);
			} else
				printf ("%s: Invalid Interface type, %d\n",
						fn, desc->iface);
		} else
			printf ("%s: Invalid family type, %d\n", fn, desc->family);
	} else
		printf ("%s: NULL descriptor!\n", fn);

	return ret_val;
}
Commit	Line	Data
5d3207da	1	/*
d5dae85f MS	2	* (C) Copyright 2012-2013, Xilinx, Michal Simek
d5dae85f MS	3	*
5d3207da WD	4	* (C) Copyright 2002
	5	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	6	* Keith Outwater, keith_outwater@mvis.com
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
5d3207da WD	9	*/
	10
	11	/*
	12	* Xilinx FPGA support
	13	*/
	14
	15	#include <common.h>
6631db47	16	#include <fpga.h>
5d3207da WD	17	#include <virtex2.h>
5d3207da WD	18	#include <spartan2.h>
875c7893	19	#include <spartan3.h>
d5dae85f	20	#include <zynqpl.h>
5d3207da	21
5d3207da	22	/* Local Static Functions */
f8c1be98	23	static int xilinx_validate(xilinx_desc desc, char fn);
5d3207da WD	24
	25	/* ------------------------------------------------------------------------- */
	26
7a78bd26 MS	27	int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
7a78bd26 MS	28	bitstream_type bstype)
52c20644 MS	29	{
	30	unsigned int length;
	31	unsigned int swapsize;
52c20644 MS	32	unsigned char *dataptr;
52c20644 MS	33	unsigned int i;
6631db47	34	const fpga_desc *desc;
f8c1be98	35	xilinx_desc *xdesc;
52c20644 MS	36
52c20644 MS	37	dataptr = (unsigned char *)fpgadata;
6631db47 MS	38	/* Find out fpga_description */
	39	desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
	40	/* Assign xilinx device description */
	41	xdesc = desc->devdesc;
52c20644 MS	42
	43	/* skip the first bytes of the bitsteam, their meaning is unknown */
	44	length = (dataptr << 8) + (dataptr + 1);
	45	dataptr += 2;
	46	dataptr += length;
	47
	48	/* get design name (identifier, length, string) */
	49	length = (dataptr << 8) + (dataptr + 1);
	50	dataptr += 2;
	51	if (*dataptr++ != 0x61) {
	52	debug("%s: Design name id not recognized in bitstream\n",
	53	__func__);
	54	return FPGA_FAIL;
	55	}
	56
	57	length = (dataptr << 8) + (dataptr + 1);
	58	dataptr += 2;
d863909f SDPP	59	printf(" design filename = \"%s\"\n", dataptr);
d863909f SDPP	60	dataptr += length;
52c20644 MS	61
	62	/* get part number (identifier, length, string) */
	63	if (*dataptr++ != 0x62) {
	64	printf("%s: Part number id not recognized in bitstream\n",
	65	__func__);
	66	return FPGA_FAIL;
	67	}
	68
	69	length = (dataptr << 8) + (dataptr + 1);
	70	dataptr += 2;
6631db47 MS	71
6631db47 MS	72	if (xdesc->name) {
d863909f	73	i = (ulong)strstr((char *)dataptr, xdesc->name);
f7213267	74	if (!i) {
6631db47 MS	75	printf("%s: Wrong bitstream ID for this device\n",
	76	__func__);
	77	printf("%s: Bitstream ID %s, current device ID %d/%s\n",
d863909f	78	__func__, dataptr, devnum, xdesc->name);
6631db47 MS	79	return FPGA_FAIL;
	80	}
	81	} else {
f8c1be98	82	printf("%s: Please fill correct device ID to xilinx_desc\n",
6631db47 MS	83	__func__);
6631db47 MS	84	}
d863909f SDPP	85	printf(" part number = \"%s\"\n", dataptr);
d863909f SDPP	86	dataptr += length;
52c20644 MS	87
	88	/* get date (identifier, length, string) */
	89	if (*dataptr++ != 0x63) {
	90	printf("%s: Date identifier not recognized in bitstream\n",
	91	__func__);
	92	return FPGA_FAIL;
	93	}
	94
	95	length = (dataptr << 8) + (dataptr+1);
	96	dataptr += 2;
d863909f SDPP	97	printf(" date = \"%s\"\n", dataptr);
d863909f SDPP	98	dataptr += length;
52c20644 MS	99
	100	/* get time (identifier, length, string) */
	101	if (*dataptr++ != 0x64) {
	102	printf("%s: Time identifier not recognized in bitstream\n",
	103	__func__);
	104	return FPGA_FAIL;
	105	}
	106
	107	length = (dataptr << 8) + (dataptr+1);
	108	dataptr += 2;
d863909f SDPP	109	printf(" time = \"%s\"\n", dataptr);
d863909f SDPP	110	dataptr += length;
52c20644 MS	111
	112	/* get fpga data length (identifier, length) */
	113	if (*dataptr++ != 0x65) {
	114	printf("%s: Data length id not recognized in bitstream\n",
	115	__func__);
	116	return FPGA_FAIL;
	117	}
	118	swapsize = ((unsigned int) *dataptr << 24) +
	119	((unsigned int) *(dataptr + 1) << 16) +
	120	((unsigned int) *(dataptr + 2) << 8) +
	121	((unsigned int) *(dataptr + 3));
	122	dataptr += 4;
	123	printf(" bytes in bitstream = %d\n", swapsize);
	124
7a78bd26	125	return fpga_load(devnum, dataptr, swapsize, bstype);
52c20644 MS	126	}
52c20644 MS	127
7a78bd26 MS	128	int xilinx_load(xilinx_desc desc, const void buf, size_t bsize,
7a78bd26 MS	129	bitstream_type bstype)
5d3207da	130	{
77ddac94	131	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da	132	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
14cfc4f3 MS	133	return FPGA_FAIL;
14cfc4f3 MS	134	}
5d3207da	135
6cd68c81 MS	136	if (!desc->operations \|\| !desc->operations->load) {
	137	printf("%s: Missing load operation\n", __func__);
	138	return FPGA_FAIL;
	139	}
	140
7a78bd26	141	return desc->operations->load(desc, buf, bsize, bstype);
5d3207da WD	142	}
5d3207da WD	143
1a897668 SDPP	144	#if defined(CONFIG_CMD_FPGA_LOADFS)
	145	int xilinx_loadfs(xilinx_desc desc, const void buf, size_t bsize,
	146	fpga_fs_info *fpga_fsinfo)
	147	{
	148	if (!xilinx_validate(desc, (char *)__func__)) {
	149	printf("%s: Invalid device descriptor\n", __func__);
	150	return FPGA_FAIL;
	151	}
	152
6cd68c81 MS	153	if (!desc->operations \|\| !desc->operations->loadfs) {
6cd68c81 MS	154	printf("%s: Missing loadfs operation\n", __func__);
1a897668	155	return FPGA_FAIL;
6cd68c81	156	}
1a897668 SDPP	157
	158	return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
	159	}
	160	#endif
	161
f8c1be98	162	int xilinx_dump(xilinx_desc desc, const void buf, size_t bsize)
5d3207da	163	{
77ddac94	164	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da	165	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
14cfc4f3 MS	166	return FPGA_FAIL;
14cfc4f3 MS	167	}
5d3207da	168
6cd68c81 MS	169	if (!desc->operations \|\| !desc->operations->dump) {
	170	printf("%s: Missing dump operation\n", __func__);
	171	return FPGA_FAIL;
	172	}
	173
14cfc4f3	174	return desc->operations->dump(desc, buf, bsize);
5d3207da WD	175	}
5d3207da WD	176
f8c1be98	177	int xilinx_info(xilinx_desc *desc)
5d3207da WD	178	{
	179	int ret_val = FPGA_FAIL;
	180
77ddac94	181	if (xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da WD	182	printf ("Family: \t");
5d3207da WD	183	switch (desc->family) {
b625b9ae	184	case xilinx_spartan2:
5d3207da WD	185	printf ("Spartan-II\n");
5d3207da WD	186	break;
2a6e3869	187	case xilinx_spartan3:
875c7893 WD	188	printf ("Spartan-III\n");
875c7893 WD	189	break;
d9071ce0	190	case xilinx_virtex2:
5d3207da WD	191	printf ("Virtex-II\n");
5d3207da WD	192	break;
d5dae85f MS	193	case xilinx_zynq:
	194	printf("Zynq PL\n");
	195	break;
6b245014 SDPP	196	case xilinx_zynqmp:
	197	printf("ZynqMP PL\n");
	198	break;
5d3207da WD	199	/* Add new family types here */
	200	default:
	201	printf ("Unknown family type, %d\n", desc->family);
	202	}
	203
	204	printf ("Interface type:\t");
	205	switch (desc->iface) {
	206	case slave_serial:
	207	printf ("Slave Serial\n");
	208	break;
	209	case master_serial: /* Not used */
	210	printf ("Master Serial\n");
	211	break;
	212	case slave_parallel:
	213	printf ("Slave Parallel\n");
	214	break;
	215	case jtag_mode: /* Not used */
	216	printf ("JTAG Mode\n");
	217	break;
	218	case slave_selectmap:
	219	printf ("Slave SelectMap Mode\n");
	220	break;
	221	case master_selectmap:
	222	printf ("Master SelectMap Mode\n");
	223	break;
d5dae85f MS	224	case devcfg:
	225	printf("Device configuration interface (Zynq)\n");
	226	break;
6b245014 SDPP	227	case csu_dma:
	228	printf("csu_dma configuration interface (ZynqMP)\n");
	229	break;
5d3207da WD	230	/* Add new interface types here */
	231	default:
	232	printf ("Unsupported interface type, %d\n", desc->iface);
	233	}
	234
ddc94378 SG	235	printf("Device Size: \t%zd bytes\n"
	236	"Cookie: \t0x%x (%d)\n",
	237	desc->size, desc->cookie, desc->cookie);
6631db47 MS	238	if (desc->name)
6631db47 MS	239	printf("Device name: \t%s\n", desc->name);
5d3207da	240
e136eaeb	241	if (desc->iface_fns)
5d3207da	242	printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
e136eaeb	243	else
5d3207da WD	244	printf ("No Device Function Table.\n");
5d3207da WD	245
e136eaeb MS	246	if (desc->operations && desc->operations->info)
	247	desc->operations->info(desc);
	248
5d3207da WD	249	ret_val = FPGA_SUCCESS;
	250	} else {
	251	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
	252	}
	253
	254	return ret_val;
	255	}
	256
5d3207da WD	257	/* ------------------------------------------------------------------------- */
5d3207da WD	258
f8c1be98	259	static int xilinx_validate(xilinx_desc desc, char fn)
5d3207da	260	{
472d5460	261	int ret_val = false;
5d3207da WD	262
	263	if (desc) {
	264	if ((desc->family > min_xilinx_type) &&
	265	(desc->family < max_xilinx_type)) {
	266	if ((desc->iface > min_xilinx_iface_type) &&
	267	(desc->iface < max_xilinx_iface_type)) {
	268	if (desc->size) {
472d5460	269	ret_val = true;
5d3207da WD	270	} else
	271	printf ("%s: NULL part size\n", fn);
	272	} else
	273	printf ("%s: Invalid Interface type, %d\n",
	274	fn, desc->iface);
	275	} else
	276	printf ("%s: Invalid family type, %d\n", fn, desc->family);
	277	} else
	278	printf ("%s: NULL descriptor!\n", fn);
	279
	280	return ret_val;
	281	}