]>
Commit | Line | Data |
---|---|---|
d5dae85f MS |
1 | /* |
2 | * (C) Copyright 2012-2013, Xilinx, Michal Simek | |
3 | * | |
4 | * (C) Copyright 2012 | |
5 | * Joe Hershberger <joe.hershberger@ni.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
d5dae85f MS |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <asm/io.h> | |
12 | #include <zynqpl.h> | |
13 | #include <asm/arch/hardware.h> | |
14 | #include <asm/arch/sys_proto.h> | |
15 | ||
16 | #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 | |
17 | #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 | |
18 | #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 | |
19 | #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 | |
20 | #define DEVCFG_ISR_DMA_DONE 0x00002000 | |
21 | #define DEVCFG_ISR_PCFG_DONE 0x00000004 | |
22 | #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000 | |
23 | #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 | |
24 | #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 | |
25 | #define DEVCFG_STATUS_PCFG_INIT 0x00000010 | |
26 | #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 | |
27 | #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 | |
28 | ||
29 | #ifndef CONFIG_SYS_FPGA_WAIT | |
30 | #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ | |
31 | #endif | |
32 | ||
33 | #ifndef CONFIG_SYS_FPGA_PROG_TIME | |
34 | #define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */ | |
35 | #endif | |
36 | ||
37 | int zynq_info(Xilinx_desc *desc) | |
38 | { | |
39 | return FPGA_SUCCESS; | |
40 | } | |
41 | ||
42 | #define DUMMY_WORD 0xffffffff | |
43 | ||
44 | /* Xilinx binary format header */ | |
45 | static const u32 bin_format[] = { | |
46 | DUMMY_WORD, /* Dummy words */ | |
47 | DUMMY_WORD, | |
48 | DUMMY_WORD, | |
49 | DUMMY_WORD, | |
50 | DUMMY_WORD, | |
51 | DUMMY_WORD, | |
52 | DUMMY_WORD, | |
53 | DUMMY_WORD, | |
54 | 0x000000bb, /* Sync word */ | |
55 | 0x11220044, /* Sync word */ | |
56 | DUMMY_WORD, | |
57 | DUMMY_WORD, | |
58 | 0xaa995566, /* Sync word */ | |
59 | }; | |
60 | ||
61 | #define SWAP_NO 1 | |
62 | #define SWAP_DONE 2 | |
63 | ||
64 | /* | |
65 | * Load the whole word from unaligned buffer | |
66 | * Keep in your mind that it is byte loading on little-endian system | |
67 | */ | |
68 | static u32 load_word(const void *buf, u32 swap) | |
69 | { | |
70 | u32 word = 0; | |
71 | u8 *bitc = (u8 *)buf; | |
72 | int p; | |
73 | ||
74 | if (swap == SWAP_NO) { | |
75 | for (p = 0; p < 4; p++) { | |
76 | word <<= 8; | |
77 | word |= bitc[p]; | |
78 | } | |
79 | } else { | |
80 | for (p = 3; p >= 0; p--) { | |
81 | word <<= 8; | |
82 | word |= bitc[p]; | |
83 | } | |
84 | } | |
85 | ||
86 | return word; | |
87 | } | |
88 | ||
89 | static u32 check_header(const void *buf) | |
90 | { | |
91 | u32 i, pattern; | |
92 | int swap = SWAP_NO; | |
93 | u32 *test = (u32 *)buf; | |
94 | ||
95 | debug("%s: Let's check bitstream header\n", __func__); | |
96 | ||
97 | /* Checking that passing bin is not a bitstream */ | |
98 | for (i = 0; i < ARRAY_SIZE(bin_format); i++) { | |
99 | pattern = load_word(&test[i], swap); | |
100 | ||
101 | /* | |
102 | * Bitstreams in binary format are swapped | |
103 | * compare to regular bistream. | |
104 | * Do not swap dummy word but if swap is done assume | |
105 | * that parsing buffer is binary format | |
106 | */ | |
107 | if ((__swab32(pattern) != DUMMY_WORD) && | |
108 | (__swab32(pattern) == bin_format[i])) { | |
109 | pattern = __swab32(pattern); | |
110 | swap = SWAP_DONE; | |
111 | debug("%s: data swapped - let's swap\n", __func__); | |
112 | } | |
113 | ||
114 | debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, | |
115 | (u32)&test[i], pattern, bin_format[i]); | |
116 | if (pattern != bin_format[i]) { | |
117 | debug("%s: Bitstream is not recognized\n", __func__); | |
118 | return 0; | |
119 | } | |
120 | } | |
121 | debug("%s: Found bitstream header at %x %s swapinng\n", __func__, | |
122 | (u32)buf, swap == SWAP_NO ? "without" : "with"); | |
123 | ||
124 | return swap; | |
125 | } | |
126 | ||
127 | static void *check_data(u8 *buf, size_t bsize, u32 *swap) | |
128 | { | |
129 | u32 word, p = 0; /* possition */ | |
130 | ||
131 | /* Because buf doesn't need to be aligned let's read it by chars */ | |
132 | for (p = 0; p < bsize; p++) { | |
133 | word = load_word(&buf[p], SWAP_NO); | |
134 | debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); | |
135 | ||
136 | /* Find the first bitstream dummy word */ | |
137 | if (word == DUMMY_WORD) { | |
138 | debug("%s: Found dummy word at position %x/%x\n", | |
139 | __func__, p, (u32)&buf[p]); | |
140 | *swap = check_header(&buf[p]); | |
141 | if (*swap) { | |
142 | /* FIXME add full bitstream checking here */ | |
143 | return &buf[p]; | |
144 | } | |
145 | } | |
146 | /* Loop can be huge - support CTRL + C */ | |
147 | if (ctrlc()) | |
148 | return 0; | |
149 | } | |
150 | return 0; | |
151 | } | |
152 | ||
153 | ||
154 | int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) | |
155 | { | |
156 | unsigned long ts; /* Timestamp */ | |
157 | u32 partialbit = 0; | |
158 | u32 i, control, isr_status, status, swap, diff; | |
159 | u32 *buf_start; | |
160 | ||
161 | /* Detect if we are going working with partial or full bitstream */ | |
162 | if (bsize != desc->size) { | |
163 | printf("%s: Working with partial bitstream\n", __func__); | |
164 | partialbit = 1; | |
165 | } | |
166 | ||
167 | buf_start = check_data((u8 *)buf, bsize, &swap); | |
168 | if (!buf_start) | |
169 | return FPGA_FAIL; | |
170 | ||
171 | /* Check if data is postpone from start */ | |
172 | diff = (u32)buf_start - (u32)buf; | |
173 | if (diff) { | |
174 | printf("%s: Bitstream is not validated yet (diff %x)\n", | |
175 | __func__, diff); | |
176 | return FPGA_FAIL; | |
177 | } | |
178 | ||
179 | if ((u32)buf_start & 0x3) { | |
180 | u32 *new_buf = (u32 *)((u32)buf & ~0x3); | |
181 | ||
182 | printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, | |
183 | (u32)buf_start, (u32)new_buf, swap); | |
184 | ||
185 | for (i = 0; i < (bsize/4); i++) | |
186 | new_buf[i] = load_word(&buf_start[i], swap); | |
187 | ||
188 | swap = SWAP_DONE; | |
189 | buf = new_buf; | |
190 | } else if (swap != SWAP_DONE) { | |
191 | /* For bitstream which are aligned */ | |
192 | u32 *new_buf = (u32 *)buf; | |
193 | ||
194 | printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, | |
195 | swap); | |
196 | ||
197 | for (i = 0; i < (bsize/4); i++) | |
198 | new_buf[i] = load_word(&buf_start[i], swap); | |
199 | ||
200 | swap = SWAP_DONE; | |
201 | } | |
202 | ||
203 | if (!partialbit) { | |
204 | zynq_slcr_devcfg_disable(); | |
205 | ||
206 | /* Setting PCFG_PROG_B signal to high */ | |
207 | control = readl(&devcfg_base->ctrl); | |
208 | writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); | |
209 | /* Setting PCFG_PROG_B signal to low */ | |
210 | writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); | |
211 | ||
212 | /* Polling the PCAP_INIT status for Reset */ | |
213 | ts = get_timer(0); | |
214 | while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { | |
215 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { | |
216 | printf("%s: Timeout wait for INIT to clear\n", | |
217 | __func__); | |
218 | return FPGA_FAIL; | |
219 | } | |
220 | } | |
221 | ||
222 | /* Setting PCFG_PROG_B signal to high */ | |
223 | writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); | |
224 | ||
225 | /* Polling the PCAP_INIT status for Set */ | |
226 | ts = get_timer(0); | |
227 | while (!(readl(&devcfg_base->status) & | |
228 | DEVCFG_STATUS_PCFG_INIT)) { | |
229 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { | |
230 | printf("%s: Timeout wait for INIT to set\n", | |
231 | __func__); | |
232 | return FPGA_FAIL; | |
233 | } | |
234 | } | |
235 | } | |
236 | ||
237 | isr_status = readl(&devcfg_base->int_sts); | |
238 | ||
239 | /* Clear it all, so if Boot ROM comes back, it can proceed */ | |
240 | writel(0xFFFFFFFF, &devcfg_base->int_sts); | |
241 | ||
242 | if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) { | |
243 | debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); | |
244 | ||
245 | /* If RX FIFO overflow, need to flush RX FIFO first */ | |
246 | if (isr_status & DEVCFG_ISR_RX_FIFO_OV) { | |
247 | writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); | |
248 | writel(0xFFFFFFFF, &devcfg_base->int_sts); | |
249 | } | |
250 | return FPGA_FAIL; | |
251 | } | |
252 | ||
253 | status = readl(&devcfg_base->status); | |
254 | ||
255 | debug("%s: Status = 0x%08X\n", __func__, status); | |
256 | ||
257 | if (status & DEVCFG_STATUS_DMA_CMD_Q_F) { | |
258 | debug("%s: Error: device busy\n", __func__); | |
259 | return FPGA_FAIL; | |
260 | } | |
261 | ||
262 | debug("%s: Device ready\n", __func__); | |
263 | ||
264 | if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) { | |
265 | if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) { | |
266 | /* Error state, transfer cannot occur */ | |
267 | debug("%s: ISR indicates error\n", __func__); | |
268 | return FPGA_FAIL; | |
269 | } else { | |
270 | /* Clear out the status */ | |
271 | writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); | |
272 | } | |
273 | } | |
274 | ||
275 | if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) { | |
276 | /* Clear the count of completed DMA transfers */ | |
277 | writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); | |
278 | } | |
279 | ||
280 | debug("%s: Source = 0x%08X\n", __func__, (u32)buf); | |
281 | debug("%s: Size = %zu\n", __func__, bsize); | |
282 | ||
283 | /* Set up the transfer */ | |
284 | writel((u32)buf | 1, &devcfg_base->dma_src_addr); | |
285 | writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); | |
286 | writel(bsize >> 2, &devcfg_base->dma_src_len); | |
287 | writel(0, &devcfg_base->dma_dst_len); | |
288 | ||
289 | isr_status = readl(&devcfg_base->int_sts); | |
290 | ||
291 | /* Polling the PCAP_INIT status for Set */ | |
292 | ts = get_timer(0); | |
293 | while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { | |
294 | if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { | |
295 | debug("%s: Error: isr = 0x%08X\n", __func__, | |
296 | isr_status); | |
297 | debug("%s: Write count = 0x%08X\n", __func__, | |
298 | readl(&devcfg_base->write_count)); | |
299 | debug("%s: Read count = 0x%08X\n", __func__, | |
300 | readl(&devcfg_base->read_count)); | |
301 | ||
302 | return FPGA_FAIL; | |
303 | } | |
304 | if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { | |
305 | printf("%s: Timeout wait for DMA to complete\n", | |
306 | __func__); | |
307 | return FPGA_FAIL; | |
308 | } | |
309 | isr_status = readl(&devcfg_base->int_sts); | |
310 | } | |
311 | ||
312 | debug("%s: DMA transfer is done\n", __func__); | |
313 | ||
314 | /* Check FPGA configuration completion */ | |
315 | ts = get_timer(0); | |
316 | while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { | |
317 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { | |
318 | printf("%s: Timeout wait for FPGA to config\n", | |
319 | __func__); | |
320 | return FPGA_FAIL; | |
321 | } | |
322 | isr_status = readl(&devcfg_base->int_sts); | |
323 | } | |
324 | ||
325 | debug("%s: FPGA config done\n", __func__); | |
326 | ||
327 | /* Clear out the DMA status */ | |
328 | writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); | |
329 | ||
330 | if (!partialbit) | |
331 | zynq_slcr_devcfg_enable(); | |
332 | ||
333 | return FPGA_SUCCESS; | |
334 | } | |
335 | ||
336 | int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) | |
337 | { | |
338 | return FPGA_FAIL; | |
339 | } |