[people/ms/u-boot.git] / drivers / gpio / gpio-uniphier.c

/*
 * Copyright (C) 2016-2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <linux/errno.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>

#define UNIPHIER_GPIO_PORT_DATA		0x0	/* data */
#define UNIPHIER_GPIO_PORT_DIR		0x4	/* direction (1:in, 0:out) */
#define UNIPHIER_GPIO_IRQ_EN		0x90	/* irq enable */

struct uniphier_gpio_priv {
	void __iomem *regs;
};

static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
{
	unsigned int reg;

	reg = (bank + 1) * 8;

	/*
	 * Unfortunately, the GPIO port registers are not contiguous because
	 * offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
	 */
	if (reg >= UNIPHIER_GPIO_IRQ_EN)
		reg += 0x10;

	return reg;
}

static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
					    unsigned int *bank, u32 *mask)
{
	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
}

static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
				     unsigned int reg, u32 mask, u32 val)
{
	u32 tmp;

	tmp = readl(priv->regs + reg);
	tmp &= ~mask;
	tmp |= mask & val;
	writel(tmp, priv->regs + reg);
}

static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
				     unsigned int reg, u32 mask, u32 val)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);

	if (!mask)
		return;

	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
				 mask, val);
}

static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
				       unsigned int reg, int val)
{
	unsigned int bank;
	u32 mask;

	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);

	uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
}

static int uniphier_gpio_offset_read(struct udevice *dev,
				     unsigned int offset, unsigned int reg)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	unsigned int bank, reg_offset;
	u32 mask;

	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;

	return !!(readl(priv->regs + reg_offset) & mask);
}

static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
{
	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
						GPIOF_INPUT : GPIOF_OUTPUT;
}

static int uniphier_gpio_direction_input(struct udevice *dev,
					 unsigned int offset)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);

	return 0;
}

static int uniphier_gpio_direction_output(struct udevice *dev,
					  unsigned int offset, int value)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);

	return 0;
}

static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
{
	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
}

static int uniphier_gpio_set_value(struct udevice *dev,
				   unsigned int offset, int value)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);

	return 0;
}

static const struct dm_gpio_ops uniphier_gpio_ops = {
	.direction_input	= uniphier_gpio_direction_input,
	.direction_output	= uniphier_gpio_direction_output,
	.get_value		= uniphier_gpio_get_value,
	.set_value		= uniphier_gpio_set_value,
	.get_function		= uniphier_gpio_get_function,
};

static int uniphier_gpio_probe(struct udevice *dev)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	fdt_addr_t addr;

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = devm_ioremap(dev, addr, SZ_512);
	if (!priv->regs)
		return -ENOMEM;

	uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
					      "ngpios", 0);

	return 0;
}

static const struct udevice_id uniphier_gpio_match[] = {
	{ .compatible = "socionext,uniphier-gpio" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(uniphier_gpio) = {
	.name	= "uniphier-gpio",
	.id	= UCLASS_GPIO,
	.of_match = uniphier_gpio_match,
	.probe	= uniphier_gpio_probe,
	.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
	.ops	= &uniphier_gpio_ops,
};
Commit	Line	Data
b9a66b63	1	/*
c5fb1c25	2	* Copyright (C) 2016-2017 Socionext Inc.
4e3d8406	3	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
b9a66b63 MY	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
9d922450	9	#include <dm.h>
b9a66b63 MY	10	#include <linux/bitops.h>
b9a66b63 MY	11	#include <linux/io.h>
bc82a131	12	#include <linux/sizes.h>
1221ce45	13	#include <linux/errno.h>
c5fb1c25	14	#include <asm/global_data.h>
b9a66b63	15	#include <asm/gpio.h>
e9986a4f	16	#include <dt-bindings/gpio/uniphier-gpio.h>
b9a66b63	17
c5fb1c25 MY	18	#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
	19	#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
	20	#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
b9a66b63 MY	21
b9a66b63 MY	22	struct uniphier_gpio_priv {
c5fb1c25	23	void __iomem *regs;
b9a66b63 MY	24	};
b9a66b63 MY	25
c5fb1c25 MY	26	static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
	27	{
	28	unsigned int reg;
	29
	30	reg = (bank + 1) * 8;
	31
	32	/*
	33	* Unfortunately, the GPIO port registers are not contiguous because
	34	* offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
	35	*/
	36	if (reg >= UNIPHIER_GPIO_IRQ_EN)
	37	reg += 0x10;
	38
	39	return reg;
	40	}
	41
	42	static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
	43	unsigned int bank, u32 mask)
	44	{
	45	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
	46	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
	47	}
	48
	49	static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
	50	unsigned int reg, u32 mask, u32 val)
b9a66b63	51	{
b9a66b63 MY	52	u32 tmp;
b9a66b63 MY	53
c5fb1c25 MY	54	tmp = readl(priv->regs + reg);
	55	tmp &= ~mask;
	56	tmp \|= mask & val;
	57	writel(tmp, priv->regs + reg);
b9a66b63 MY	58	}
b9a66b63 MY	59
c5fb1c25 MY	60	static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
c5fb1c25 MY	61	unsigned int reg, u32 mask, u32 val)
b9a66b63 MY	62	{
	63	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	64
c5fb1c25 MY	65	if (!mask)
	66	return;
	67
	68	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
	69	mask, val);
b9a66b63 MY	70	}
b9a66b63 MY	71
c5fb1c25 MY	72	static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
c5fb1c25 MY	73	unsigned int reg, int val)
b9a66b63	74	{
c5fb1c25 MY	75	unsigned int bank;
c5fb1c25 MY	76	u32 mask;
b9a66b63	77
c5fb1c25 MY	78	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
	79
	80	uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
b9a66b63 MY	81	}
b9a66b63 MY	82
c5fb1c25 MY	83	static int uniphier_gpio_offset_read(struct udevice *dev,
c5fb1c25 MY	84	unsigned int offset, unsigned int reg)
b9a66b63	85	{
c5fb1c25 MY	86	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	87	unsigned int bank, reg_offset;
	88	u32 mask;
b9a66b63	89
c5fb1c25 MY	90	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
	91	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
	92
	93	return !!(readl(priv->regs + reg_offset) & mask);
b9a66b63 MY	94	}
b9a66b63 MY	95
c5fb1c25	96	static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
b9a66b63	97	{
c5fb1c25 MY	98	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
c5fb1c25 MY	99	GPIOF_INPUT : GPIOF_OUTPUT;
b9a66b63 MY	100	}
b9a66b63 MY	101
c5fb1c25 MY	102	static int uniphier_gpio_direction_input(struct udevice *dev,
c5fb1c25 MY	103	unsigned int offset)
b9a66b63	104	{
c5fb1c25	105	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
b9a66b63 MY	106
	107	return 0;
	108	}
	109
c5fb1c25 MY	110	static int uniphier_gpio_direction_output(struct udevice *dev,
c5fb1c25 MY	111	unsigned int offset, int value)
b9a66b63	112	{
c5fb1c25 MY	113	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
	114	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
	115
	116	return 0;
	117	}
	118
	119	static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
	120	{
	121	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
	122	}
	123
	124	static int uniphier_gpio_set_value(struct udevice *dev,
	125	unsigned int offset, int value)
	126	{
	127	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
	128
	129	return 0;
b9a66b63 MY	130	}
	131
	132	static const struct dm_gpio_ops uniphier_gpio_ops = {
	133	.direction_input = uniphier_gpio_direction_input,
	134	.direction_output = uniphier_gpio_direction_output,
	135	.get_value = uniphier_gpio_get_value,
	136	.set_value = uniphier_gpio_set_value,
	137	.get_function = uniphier_gpio_get_function,
	138	};
	139
	140	static int uniphier_gpio_probe(struct udevice *dev)
	141	{
	142	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	143	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
b9a66b63	144	fdt_addr_t addr;
b9a66b63	145
a821c4af	146	addr = devfdt_get_addr(dev);
b9a66b63 MY	147	if (addr == FDT_ADDR_T_NONE)
	148	return -EINVAL;
	149
c5fb1c25 MY	150	priv->regs = devm_ioremap(dev, addr, SZ_512);
c5fb1c25 MY	151	if (!priv->regs)
b9a66b63 MY	152	return -ENOMEM;
b9a66b63 MY	153
c5fb1c25 MY	154	uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
c5fb1c25 MY	155	"ngpios", 0);
b9a66b63 MY	156
	157	return 0;
	158	}
	159
b9a66b63 MY	160	static const struct udevice_id uniphier_gpio_match[] = {
	161	{ .compatible = "socionext,uniphier-gpio" },
	162	{ /* sentinel */ }
	163	};
	164
	165	U_BOOT_DRIVER(uniphier_gpio) = {
c5fb1c25	166	.name = "uniphier-gpio",
b9a66b63 MY	167	.id = UCLASS_GPIO,
	168	.of_match = uniphier_gpio_match,
	169	.probe = uniphier_gpio_probe,
b9a66b63 MY	170	.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
	171	.ops = &uniphier_gpio_ops,
	172	};