[people/ms/u-boot.git] / drivers / gpio / mxc_gpio.c

/*
 * Copyright (C) 2009
 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
 *
 * Copyright (C) 2011
 * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <errno.h>
#include <dm.h>
#include <malloc.h>
#include <asm/arch/imx-regs.h>
#include <asm/gpio.h>
#include <asm/io.h>

enum mxc_gpio_direction {
	MXC_GPIO_DIRECTION_IN,
	MXC_GPIO_DIRECTION_OUT,
};

#define GPIO_PER_BANK			32

struct mxc_gpio_plat {
	int bank_index;
	struct gpio_regs *regs;
};

struct mxc_bank_info {
	struct gpio_regs *regs;
};

#ifndef CONFIG_DM_GPIO
#define GPIO_TO_PORT(n)		(n / 32)

/* GPIO port description */
static unsigned long gpio_ports[] = {
	[0] = GPIO1_BASE_ADDR,
	[1] = GPIO2_BASE_ADDR,
	[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
		defined(CONFIG_MX7) || defined(CONFIG_MX8M)
	[3] = GPIO4_BASE_ADDR,
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
		defined(CONFIG_MX7) || defined(CONFIG_MX8M)
	[4] = GPIO5_BASE_ADDR,
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
	[5] = GPIO6_BASE_ADDR,
#endif
#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
	[6] = GPIO7_BASE_ADDR,
#endif
#endif
};

static int mxc_gpio_direction(unsigned int gpio,
	enum mxc_gpio_direction direction)
{
	unsigned int port = GPIO_TO_PORT(gpio);
	struct gpio_regs *regs;
	u32 l;

	if (port >= ARRAY_SIZE(gpio_ports))
		return -1;

	gpio &= 0x1f;

	regs = (struct gpio_regs *)gpio_ports[port];

	l = readl(&regs->gpio_dir);

	switch (direction) {
	case MXC_GPIO_DIRECTION_OUT:
		l |= 1 << gpio;
		break;
	case MXC_GPIO_DIRECTION_IN:
		l &= ~(1 << gpio);
	}
	writel(l, &regs->gpio_dir);

	return 0;
}

int gpio_set_value(unsigned gpio, int value)
{
	unsigned int port = GPIO_TO_PORT(gpio);
	struct gpio_regs *regs;
	u32 l;

	if (port >= ARRAY_SIZE(gpio_ports))
		return -1;

	gpio &= 0x1f;

	regs = (struct gpio_regs *)gpio_ports[port];

	l = readl(&regs->gpio_dr);
	if (value)
		l |= 1 << gpio;
	else
		l &= ~(1 << gpio);
	writel(l, &regs->gpio_dr);

	return 0;
}

int gpio_get_value(unsigned gpio)
{
	unsigned int port = GPIO_TO_PORT(gpio);
	struct gpio_regs *regs;
	u32 val;

	if (port >= ARRAY_SIZE(gpio_ports))
		return -1;

	gpio &= 0x1f;

	regs = (struct gpio_regs *)gpio_ports[port];

	val = (readl(&regs->gpio_psr) >> gpio) & 0x01;

	return val;
}

int gpio_request(unsigned gpio, const char *label)
{
	unsigned int port = GPIO_TO_PORT(gpio);
	if (port >= ARRAY_SIZE(gpio_ports))
		return -1;
	return 0;
}

int gpio_free(unsigned gpio)
{
	return 0;
}

int gpio_direction_input(unsigned gpio)
{
	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
}

int gpio_direction_output(unsigned gpio, int value)
{
	int ret = gpio_set_value(gpio, value);

	if (ret < 0)
		return ret;

	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
}
#endif

#ifdef CONFIG_DM_GPIO
#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;

static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
{
	u32 val;

	val = readl(&regs->gpio_dir);

	return val & (1 << offset) ? 1 : 0;
}

static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
				    enum mxc_gpio_direction direction)
{
	u32 l;

	l = readl(&regs->gpio_dir);

	switch (direction) {
	case MXC_GPIO_DIRECTION_OUT:
		l |= 1 << offset;
		break;
	case MXC_GPIO_DIRECTION_IN:
		l &= ~(1 << offset);
	}
	writel(l, &regs->gpio_dir);
}

static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
				    int value)
{
	u32 l;

	l = readl(&regs->gpio_dr);
	if (value)
		l |= 1 << offset;
	else
		l &= ~(1 << offset);
	writel(l, &regs->gpio_dr);
}

static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
{
	return (readl(&regs->gpio_psr) >> offset) & 0x01;
}

/* set GPIO pin 'gpio' as an input */
static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct mxc_bank_info *bank = dev_get_priv(dev);

	/* Configure GPIO direction as input. */
	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);

	return 0;
}

/* set GPIO pin 'gpio' as an output, with polarity 'value' */
static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	struct mxc_bank_info *bank = dev_get_priv(dev);

	/* Configure GPIO output value. */
	mxc_gpio_bank_set_value(bank->regs, offset, value);

	/* Configure GPIO direction as output. */
	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);

	return 0;
}

/* read GPIO IN value of pin 'gpio' */
static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct mxc_bank_info *bank = dev_get_priv(dev);

	return mxc_gpio_bank_get_value(bank->regs, offset);
}

/* write GPIO OUT value to pin 'gpio' */
static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
				 int value)
{
	struct mxc_bank_info *bank = dev_get_priv(dev);

	mxc_gpio_bank_set_value(bank->regs, offset, value);

	return 0;
}

static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
{
	struct mxc_bank_info *bank = dev_get_priv(dev);

	/* GPIOF_FUNC is not implemented yet */
	if (mxc_gpio_is_output(bank->regs, offset))
		return GPIOF_OUTPUT;
	else
		return GPIOF_INPUT;
}

static const struct dm_gpio_ops gpio_mxc_ops = {
	.direction_input	= mxc_gpio_direction_input,
	.direction_output	= mxc_gpio_direction_output,
	.get_value		= mxc_gpio_get_value,
	.set_value		= mxc_gpio_set_value,
	.get_function		= mxc_gpio_get_function,
};

static int mxc_gpio_probe(struct udevice *dev)
{
	struct mxc_bank_info *bank = dev_get_priv(dev);
	struct mxc_gpio_plat *plat = dev_get_platdata(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	int banknum;
	char name[18], *str;

	banknum = plat->bank_index;
	sprintf(name, "GPIO%d_", banknum + 1);
	str = strdup(name);
	if (!str)
		return -ENOMEM;
	uc_priv->bank_name = str;
	uc_priv->gpio_count = GPIO_PER_BANK;
	bank->regs = plat->regs;

	return 0;
}

static int mxc_gpio_bind(struct udevice *dev)
{
	struct mxc_gpio_plat *plat = dev->platdata;
	fdt_addr_t addr;

	/*
	 * If platdata already exsits, directly return.
	 * Actually only when DT is not supported, platdata
	 * is statically initialized in U_BOOT_DEVICES.Here
	 * will return.
	 */
	if (plat)
		return 0;

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	/*
	 * TODO:
	 * When every board is converted to driver model and DT is supported,
	 * this can be done by auto-alloc feature, but not using calloc
	 * to alloc memory for platdata.
	 *
	 * For example mxc_plat below uses platform data rather than device
	 * tree.
	 *
	 * NOTE: DO NOT COPY this code if you are using device tree.
	 */
	plat = calloc(1, sizeof(*plat));
	if (!plat)
		return -ENOMEM;

	plat->regs = (struct gpio_regs *)addr;
	plat->bank_index = dev->req_seq;
	dev->platdata = plat;

	return 0;
}

static const struct udevice_id mxc_gpio_ids[] = {
	{ .compatible = "fsl,imx35-gpio" },
	{ }
};

U_BOOT_DRIVER(gpio_mxc) = {
	.name	= "gpio_mxc",
	.id	= UCLASS_GPIO,
	.ops	= &gpio_mxc_ops,
	.probe	= mxc_gpio_probe,
	.priv_auto_alloc_size = sizeof(struct mxc_bank_info),
	.of_match = mxc_gpio_ids,
	.bind	= mxc_gpio_bind,
};

#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct mxc_gpio_plat mxc_plat[] = {
	{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
		defined(CONFIG_MX8M)
	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
		defined(CONFIG_MX8M)
	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
#ifndef CONFIG_MX8M
	{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
#endif
#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
	{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
#endif
};

U_BOOT_DEVICES(mxc_gpios) = {
	{ "gpio_mxc", &mxc_plat[0] },
	{ "gpio_mxc", &mxc_plat[1] },
	{ "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
		defined(CONFIG_MX8M)
	{ "gpio_mxc", &mxc_plat[3] },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
		defined(CONFIG_MX8M)
	{ "gpio_mxc", &mxc_plat[4] },
#ifndef CONFIG_MX8M
	{ "gpio_mxc", &mxc_plat[5] },
#endif
#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
	{ "gpio_mxc", &mxc_plat[6] },
#endif
};
#endif
#endif
Commit	Line	Data
b30de3cc GL	1	/*
	2	* Copyright (C) 2009
	3	* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
	4	*
d8e0ca85 SB	5	* Copyright (C) 2011
	6	* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
b30de3cc GL	9	*/
b30de3cc GL	10	#include <common.h>
441d0cff SG	11	#include <errno.h>
	12	#include <dm.h>
	13	#include <malloc.h>
c4ea1424	14	#include <asm/arch/imx-regs.h>
d8e0ca85	15	#include <asm/gpio.h>
c4ea1424	16	#include <asm/io.h>
b30de3cc	17
d8e0ca85 SB	18	enum mxc_gpio_direction {
	19	MXC_GPIO_DIRECTION_IN,
	20	MXC_GPIO_DIRECTION_OUT,
	21	};
	22
441d0cff SG	23	#define GPIO_PER_BANK 32
	24
	25	struct mxc_gpio_plat {
637a7693	26	int bank_index;
441d0cff SG	27	struct gpio_regs *regs;
	28	};
	29
	30	struct mxc_bank_info {
441d0cff SG	31	struct gpio_regs *regs;
	32	};
	33
	34	#ifndef CONFIG_DM_GPIO
8d28c211	35	#define GPIO_TO_PORT(n) (n / 32)
d8e0ca85	36
b30de3cc GL	37	/* GPIO port description */
b30de3cc GL	38	static unsigned long gpio_ports[] = {
c4ea1424 SB	39	[0] = GPIO1_BASE_ADDR,
	40	[1] = GPIO2_BASE_ADDR,
	41	[2] = GPIO3_BASE_ADDR,
e71c39de	42	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \
26dd3464	43	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \
8953d866	44	defined(CONFIG_MX7) \|\| defined(CONFIG_MX8M)
c4ea1424 SB	45	[3] = GPIO4_BASE_ADDR,
c4ea1424 SB	46	#endif
26dd3464	47	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \
8953d866	48	defined(CONFIG_MX7) \|\| defined(CONFIG_MX8M)
01643ec1	49	[4] = GPIO5_BASE_ADDR,
8953d866	50	#if !(defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL) \|\| defined(CONFIG_MX8M))
01643ec1	51	[5] = GPIO6_BASE_ADDR,
e71c39de	52	#endif
f2753b06	53	#endif
26dd3464	54	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| defined(CONFIG_MX7)
290e7cfd	55	#if !(defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL))
01643ec1 LHR	56	[6] = GPIO7_BASE_ADDR,
01643ec1 LHR	57	#endif
f2753b06	58	#endif
b30de3cc GL	59	};
b30de3cc GL	60
d8e0ca85 SB	61	static int mxc_gpio_direction(unsigned int gpio,
d8e0ca85 SB	62	enum mxc_gpio_direction direction)
b30de3cc	63	{
be282554	64	unsigned int port = GPIO_TO_PORT(gpio);
c4ea1424	65	struct gpio_regs *regs;
b30de3cc GL	66	u32 l;
	67
	68	if (port >= ARRAY_SIZE(gpio_ports))
365d6070	69	return -1;
b30de3cc GL	70
	71	gpio &= 0x1f;
	72
c4ea1424 SB	73	regs = (struct gpio_regs *)gpio_ports[port];
	74
	75	l = readl(&regs->gpio_dir);
	76
b30de3cc	77	switch (direction) {
c4ea1424	78	case MXC_GPIO_DIRECTION_OUT:
b30de3cc GL	79	l \|= 1 << gpio;
b30de3cc GL	80	break;
c4ea1424	81	case MXC_GPIO_DIRECTION_IN:
b30de3cc GL	82	l &= ~(1 << gpio);
b30de3cc GL	83	}
c4ea1424	84	writel(l, &regs->gpio_dir);
b30de3cc GL	85
	86	return 0;
	87	}
	88
365d6070	89	int gpio_set_value(unsigned gpio, int value)
b30de3cc	90	{
be282554	91	unsigned int port = GPIO_TO_PORT(gpio);
c4ea1424	92	struct gpio_regs *regs;
b30de3cc GL	93	u32 l;
	94
	95	if (port >= ARRAY_SIZE(gpio_ports))
365d6070	96	return -1;
b30de3cc GL	97
	98	gpio &= 0x1f;
	99
c4ea1424 SB	100	regs = (struct gpio_regs *)gpio_ports[port];
	101
	102	l = readl(&regs->gpio_dr);
b30de3cc GL	103	if (value)
	104	l \|= 1 << gpio;
	105	else
	106	l &= ~(1 << gpio);
c4ea1424	107	writel(l, &regs->gpio_dr);
365d6070 JH	108
365d6070 JH	109	return 0;
b30de3cc	110	}
7d27cd08	111
365d6070	112	int gpio_get_value(unsigned gpio)
7d27cd08	113	{
be282554	114	unsigned int port = GPIO_TO_PORT(gpio);
c4ea1424	115	struct gpio_regs *regs;
365d6070	116	u32 val;
7d27cd08 SB	117
7d27cd08 SB	118	if (port >= ARRAY_SIZE(gpio_ports))
365d6070	119	return -1;
7d27cd08 SB	120
	121	gpio &= 0x1f;
	122
c4ea1424 SB	123	regs = (struct gpio_regs *)gpio_ports[port];
c4ea1424 SB	124
5dafa454	125	val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
7d27cd08	126
365d6070	127	return val;
7d27cd08	128	}
d8e0ca85	129
365d6070	130	int gpio_request(unsigned gpio, const char *label)
d8e0ca85	131	{
be282554	132	unsigned int port = GPIO_TO_PORT(gpio);
d8e0ca85	133	if (port >= ARRAY_SIZE(gpio_ports))
365d6070	134	return -1;
d8e0ca85 SB	135	return 0;
	136	}
	137
365d6070	138	int gpio_free(unsigned gpio)
d8e0ca85	139	{
365d6070	140	return 0;
d8e0ca85 SB	141	}
d8e0ca85 SB	142
365d6070	143	int gpio_direction_input(unsigned gpio)
d8e0ca85	144	{
365d6070	145	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
d8e0ca85 SB	146	}
d8e0ca85 SB	147
365d6070	148	int gpio_direction_output(unsigned gpio, int value)
d8e0ca85	149	{
04c79cbd	150	int ret = gpio_set_value(gpio, value);
d8e0ca85 SB	151
	152	if (ret < 0)
	153	return ret;
	154
04c79cbd	155	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
d8e0ca85	156	}
441d0cff SG	157	#endif
	158
	159	#ifdef CONFIG_DM_GPIO
99c0ae16 PF	160	#include <fdtdec.h>
	161	DECLARE_GLOBAL_DATA_PTR;
	162
441d0cff SG	163	static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
	164	{
	165	u32 val;
	166
	167	val = readl(&regs->gpio_dir);
	168
	169	return val & (1 << offset) ? 1 : 0;
	170	}
	171
	172	static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
	173	enum mxc_gpio_direction direction)
	174	{
	175	u32 l;
	176
	177	l = readl(&regs->gpio_dir);
	178
	179	switch (direction) {
	180	case MXC_GPIO_DIRECTION_OUT:
	181	l \|= 1 << offset;
	182	break;
	183	case MXC_GPIO_DIRECTION_IN:
	184	l &= ~(1 << offset);
	185	}
	186	writel(l, &regs->gpio_dir);
	187	}
	188
	189	static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
	190	int value)
	191	{
	192	u32 l;
	193
	194	l = readl(&regs->gpio_dr);
	195	if (value)
	196	l \|= 1 << offset;
	197	else
	198	l &= ~(1 << offset);
	199	writel(l, &regs->gpio_dr);
	200	}
	201
	202	static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
	203	{
	204	return (readl(&regs->gpio_psr) >> offset) & 0x01;
	205	}
	206
441d0cff SG	207	/* set GPIO pin 'gpio' as an input */
	208	static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
	209	{
	210	struct mxc_bank_info *bank = dev_get_priv(dev);
441d0cff SG	211
	212	/* Configure GPIO direction as input. */
	213	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
	214
	215	return 0;
	216	}
	217
	218	/* set GPIO pin 'gpio' as an output, with polarity 'value' */
	219	static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
	220	int value)
	221	{
	222	struct mxc_bank_info *bank = dev_get_priv(dev);
441d0cff SG	223
	224	/* Configure GPIO output value. */
	225	mxc_gpio_bank_set_value(bank->regs, offset, value);
	226
	227	/* Configure GPIO direction as output. */
	228	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
	229
	230	return 0;
	231	}
	232
	233	/* read GPIO IN value of pin 'gpio' */
	234	static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
	235	{
	236	struct mxc_bank_info *bank = dev_get_priv(dev);
441d0cff SG	237
	238	return mxc_gpio_bank_get_value(bank->regs, offset);
	239	}
	240
	241	/* write GPIO OUT value to pin 'gpio' */
	242	static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
	243	int value)
	244	{
	245	struct mxc_bank_info *bank = dev_get_priv(dev);
441d0cff SG	246
	247	mxc_gpio_bank_set_value(bank->regs, offset, value);
	248
	249	return 0;
	250	}
	251
441d0cff SG	252	static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
	253	{
	254	struct mxc_bank_info *bank = dev_get_priv(dev);
	255
441d0cff SG	256	/* GPIOF_FUNC is not implemented yet */
	257	if (mxc_gpio_is_output(bank->regs, offset))
	258	return GPIOF_OUTPUT;
	259	else
	260	return GPIOF_INPUT;
	261	}
	262
	263	static const struct dm_gpio_ops gpio_mxc_ops = {
441d0cff SG	264	.direction_input = mxc_gpio_direction_input,
	265	.direction_output = mxc_gpio_direction_output,
	266	.get_value = mxc_gpio_get_value,
	267	.set_value = mxc_gpio_set_value,
	268	.get_function = mxc_gpio_get_function,
441d0cff SG	269	};
441d0cff SG	270
441d0cff SG	271	static int mxc_gpio_probe(struct udevice *dev)
	272	{
	273	struct mxc_bank_info *bank = dev_get_priv(dev);
	274	struct mxc_gpio_plat *plat = dev_get_platdata(dev);
e564f054	275	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
441d0cff SG	276	int banknum;
	277	char name[18], *str;
	278
637a7693	279	banknum = plat->bank_index;
441d0cff SG	280	sprintf(name, "GPIO%d_", banknum + 1);
	281	str = strdup(name);
	282	if (!str)
	283	return -ENOMEM;
	284	uc_priv->bank_name = str;
	285	uc_priv->gpio_count = GPIO_PER_BANK;
	286	bank->regs = plat->regs;
	287
	288	return 0;
	289	}
	290
99c0ae16 PF	291	static int mxc_gpio_bind(struct udevice *dev)
	292	{
	293	struct mxc_gpio_plat *plat = dev->platdata;
	294	fdt_addr_t addr;
	295
	296	/*
	297	* If platdata already exsits, directly return.
	298	* Actually only when DT is not supported, platdata
	299	* is statically initialized in U_BOOT_DEVICES.Here
	300	* will return.
	301	*/
	302	if (plat)
	303	return 0;
	304
a821c4af	305	addr = devfdt_get_addr(dev);
99c0ae16	306	if (addr == FDT_ADDR_T_NONE)
7c84319a	307	return -EINVAL;
99c0ae16 PF	308
	309	/*
	310	* TODO:
	311	* When every board is converted to driver model and DT is supported,
	312	* this can be done by auto-alloc feature, but not using calloc
	313	* to alloc memory for platdata.
4d686041 SG	314	*
	315	* For example mxc_plat below uses platform data rather than device
	316	* tree.
	317	*
	318	* NOTE: DO NOT COPY this code if you are using device tree.
99c0ae16 PF	319	*/
	320	plat = calloc(1, sizeof(*plat));
	321	if (!plat)
	322	return -ENOMEM;
	323
	324	plat->regs = (struct gpio_regs *)addr;
	325	plat->bank_index = dev->req_seq;
	326	dev->platdata = plat;
	327
	328	return 0;
	329	}
	330
	331	static const struct udevice_id mxc_gpio_ids[] = {
	332	{ .compatible = "fsl,imx35-gpio" },
	333	{ }
	334	};
	335
441d0cff SG	336	U_BOOT_DRIVER(gpio_mxc) = {
	337	.name = "gpio_mxc",
	338	.id = UCLASS_GPIO,
	339	.ops = &gpio_mxc_ops,
	340	.probe = mxc_gpio_probe,
	341	.priv_auto_alloc_size = sizeof(struct mxc_bank_info),
99c0ae16 PF	342	.of_match = mxc_gpio_ids,
	343	.bind = mxc_gpio_bind,
	344	};
	345
0f925822	346	#if !CONFIG_IS_ENABLED(OF_CONTROL)
99c0ae16 PF	347	static const struct mxc_gpio_plat mxc_plat[] = {
	348	{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
	349	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
	350	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
	351	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \
8953d866 PF	352	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \
8953d866 PF	353	defined(CONFIG_MX8M)
99c0ae16 PF	354	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
99c0ae16 PF	355	#endif
8953d866 PF	356	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \
8953d866 PF	357	defined(CONFIG_MX8M)
99c0ae16	358	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
8953d866	359	#ifndef CONFIG_MX8M
99c0ae16 PF	360	{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
99c0ae16 PF	361	#endif
8953d866	362	#endif
99c0ae16 PF	363	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
	364	{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
	365	#endif
441d0cff SG	366	};
	367
	368	U_BOOT_DEVICES(mxc_gpios) = {
	369	{ "gpio_mxc", &mxc_plat[0] },
	370	{ "gpio_mxc", &mxc_plat[1] },
	371	{ "gpio_mxc", &mxc_plat[2] },
	372	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \
8953d866 PF	373	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \
8953d866 PF	374	defined(CONFIG_MX8M)
441d0cff SG	375	{ "gpio_mxc", &mxc_plat[3] },
441d0cff SG	376	#endif
8953d866 PF	377	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \
8953d866 PF	378	defined(CONFIG_MX8M)
441d0cff	379	{ "gpio_mxc", &mxc_plat[4] },
8953d866	380	#ifndef CONFIG_MX8M
441d0cff SG	381	{ "gpio_mxc", &mxc_plat[5] },
441d0cff SG	382	#endif
8953d866	383	#endif
441d0cff SG	384	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
	385	{ "gpio_mxc", &mxc_plat[6] },
	386	#endif
	387	};
	388	#endif
99c0ae16	389	#endif