[people/ms/u-boot.git] / drivers / gpio / tegra_gpio.c

/*
 * NVIDIA Tegra20 GPIO handling.
 *  (C) Copyright 2010-2012,2015
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
 * Tom Warren (twarren@nvidia.com)
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/bitops.h>
#include <asm/arch/tegra.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

static const int CONFIG_SFIO = 0;
static const int CONFIG_GPIO = 1;
static const int DIRECTION_INPUT = 0;
static const int DIRECTION_OUTPUT = 1;

struct tegra_gpio_platdata {
	struct gpio_ctlr_bank *bank;
	const char *port_name;	/* Name of port, e.g. "B" */
	int base_gpio;		/* Port number for this port (0, 1,.., n-1) */
};

/* Information about each port at run-time */
struct tegra_port_info {
	struct gpio_ctlr_bank *bank;
	int base_gpio;		/* Port number for this port (0, 1,.., n-1) */
};

/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
static int get_config(unsigned gpio)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;
	int type;

	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
	type = (u >> GPIO_BIT(gpio)) & 1;

	debug("get_config: port = %d, bit = %d is %s\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");

	return type ? CONFIG_GPIO : CONFIG_SFIO;
}

/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
static void set_config(unsigned gpio, int type)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;

	debug("set_config: port = %d, bit = %d, %s\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");

	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
	if (type != CONFIG_SFIO)
		u |= 1 << GPIO_BIT(gpio);
	else
		u &= ~(1 << GPIO_BIT(gpio));
	writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
}

/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
static int get_direction(unsigned gpio)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;
	int dir;

	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
	dir =  (u >> GPIO_BIT(gpio)) & 1;

	debug("get_direction: port = %d, bit = %d, %s\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");

	return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
}

/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
static void set_direction(unsigned gpio, int output)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;

	debug("set_direction: port = %d, bit = %d, %s\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");

	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
	if (output != DIRECTION_INPUT)
		u |= 1 << GPIO_BIT(gpio);
	else
		u &= ~(1 << GPIO_BIT(gpio));
	writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
}

/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
static void set_level(unsigned gpio, int high)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;

	debug("set_level: port = %d, bit %d == %d\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);

	u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
	if (high)
		u |= 1 << GPIO_BIT(gpio);
	else
		u &= ~(1 << GPIO_BIT(gpio));
	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
}

/*
 * Generic_GPIO primitives.
 */

/* set GPIO pin 'gpio' as an input */
static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct tegra_port_info *state = dev_get_priv(dev);

	/* Configure GPIO direction as input. */
	set_direction(state->base_gpio + offset, DIRECTION_INPUT);

	/* Enable the pin as a GPIO */
	set_config(state->base_gpio + offset, 1);

	return 0;
}

/* set GPIO pin 'gpio' as an output, with polarity 'value' */
static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	struct tegra_port_info *state = dev_get_priv(dev);
	int gpio = state->base_gpio + offset;

	/* Configure GPIO output value. */
	set_level(gpio, value);

	/* Configure GPIO direction as output. */
	set_direction(gpio, DIRECTION_OUTPUT);

	/* Enable the pin as a GPIO */
	set_config(state->base_gpio + offset, 1);

	return 0;
}

/* read GPIO IN value of pin 'gpio' */
static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct tegra_port_info *state = dev_get_priv(dev);
	int gpio = state->base_gpio + offset;
	int val;

	debug("%s: pin = %d (port %d:bit %d)\n", __func__,
	      gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));

	if (get_direction(gpio) == DIRECTION_INPUT)
		val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
	else
		val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);

	return (val >> GPIO_BIT(gpio)) & 1;
}

/* write GPIO OUT value to pin 'gpio' */
static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
	struct tegra_port_info *state = dev_get_priv(dev);
	int gpio = state->base_gpio + offset;

	debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
	      gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);

	/* Configure GPIO output value. */
	set_level(gpio, value);

	return 0;
}

void gpio_config_table(const struct tegra_gpio_config *config, int len)
{
	int i;

	for (i = 0; i < len; i++) {
		switch (config[i].init) {
		case TEGRA_GPIO_INIT_IN:
			set_direction(config[i].gpio, DIRECTION_INPUT);
			break;
		case TEGRA_GPIO_INIT_OUT0:
			set_level(config[i].gpio, 0);
			set_direction(config[i].gpio, DIRECTION_OUTPUT);
			break;
		case TEGRA_GPIO_INIT_OUT1:
			set_level(config[i].gpio, 1);
			set_direction(config[i].gpio, DIRECTION_OUTPUT);
			break;
		}
		set_config(config[i].gpio, CONFIG_GPIO);
	}
}

static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
{
	struct tegra_port_info *state = dev_get_priv(dev);
	int gpio = state->base_gpio + offset;

	if (!get_config(gpio))
		return GPIOF_FUNC;
	else if (get_direction(gpio))
		return GPIOF_OUTPUT;
	else
		return GPIOF_INPUT;
}

static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
			    struct ofnode_phandle_args *args)
{
	int gpio, port, ret;

	gpio = args->args[0];
	port = gpio / TEGRA_GPIOS_PER_PORT;
	ret = device_get_child(dev, port, &desc->dev);
	if (ret)
		return ret;
	desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;

	return 0;
}

static const struct dm_gpio_ops gpio_tegra_ops = {
	.direction_input	= tegra_gpio_direction_input,
	.direction_output	= tegra_gpio_direction_output,
	.get_value		= tegra_gpio_get_value,
	.set_value		= tegra_gpio_set_value,
	.get_function		= tegra_gpio_get_function,
	.xlate			= tegra_gpio_xlate,
};

/**
 * Returns the name of a GPIO port
 *
 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
 *
 * @base_port: Base port number (0, 1..n-1)
 * @return allocated string containing the name
 */
static char *gpio_port_name(int base_port)
{
	char *name, *s;

	name = malloc(3);
	if (name) {
		s = name;
		*s++ = 'A' + (base_port % 26);
		if (base_port >= 26)
			*s++ = *name;
		*s = '\0';
	}

	return name;
}

static const struct udevice_id tegra_gpio_ids[] = {
	{ .compatible = "nvidia,tegra30-gpio" },
	{ .compatible = "nvidia,tegra20-gpio" },
	{ }
};

static int gpio_tegra_probe(struct udevice *dev)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct tegra_port_info *priv = dev->priv;
	struct tegra_gpio_platdata *plat = dev->platdata;

	/* Only child devices have ports */
	if (!plat)
		return 0;

	priv->bank = plat->bank;
	priv->base_gpio = plat->base_gpio;

	uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
	uc_priv->bank_name = plat->port_name;

	return 0;
}

/**
 * We have a top-level GPIO device with no actual GPIOs. It has a child
 * device for each Tegra port.
 */
static int gpio_tegra_bind(struct udevice *parent)
{
	struct tegra_gpio_platdata *plat = parent->platdata;
	struct gpio_ctlr *ctlr;
	int bank_count;
	int bank;
	int ret;

	/* If this is a child device, there is nothing to do here */
	if (plat)
		return 0;

	/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
#ifdef CONFIG_SPL_BUILD
	ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	bank_count = TEGRA_GPIO_BANKS;
#else
	{
	int len;

	/*
	 * This driver does not make use of interrupts, other than to figure
	 * out the number of GPIO banks
	 */
	len = dev_read_size(parent, "interrupts");
	if (len < 0)
		return len;
	bank_count = len / 3 / sizeof(u32);
	ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
	if ((ulong)ctlr == FDT_ADDR_T_NONE)
		return -EINVAL;
	}
#endif
	for (bank = 0; bank < bank_count; bank++) {
		int port;

		for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
			struct tegra_gpio_platdata *plat;
			struct udevice *dev;
			int base_port;

			plat = calloc(1, sizeof(*plat));
			if (!plat)
				return -ENOMEM;
			plat->bank = &ctlr->gpio_bank[bank];
			base_port = bank * TEGRA_PORTS_PER_BANK + port;
			plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
			plat->port_name = gpio_port_name(base_port);

			ret = device_bind(parent, parent->driver,
					  plat->port_name, plat, -1, &dev);
			if (ret)
				return ret;
			dev_set_of_offset(dev, dev_of_offset(parent));
		}
	}

	return 0;
}

U_BOOT_DRIVER(gpio_tegra) = {
	.name	= "gpio_tegra",
	.id	= UCLASS_GPIO,
	.of_match = tegra_gpio_ids,
	.bind	= gpio_tegra_bind,
	.probe = gpio_tegra_probe,
	.priv_auto_alloc_size = sizeof(struct tegra_port_info),
	.ops	= &gpio_tegra_ops,
	.flags	= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
4e5ae09e	1	/*
00a2749d	2	* NVIDIA Tegra20 GPIO handling.
fe82857c	3	* (C) Copyright 2010-2012,2015
4e5ae09e TW	4	* NVIDIA Corporation <www.nvidia.com>
4e5ae09e TW	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
4e5ae09e TW	7	*/
	8
	9	/*
	10	* Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
	11	* Tom Warren (twarren@nvidia.com)
	12	*/
	13
	14	#include <common.h>
2fccd2d9 SG	15	#include <dm.h>
	16	#include <malloc.h>
	17	#include <errno.h>
	18	#include <fdtdec.h>
4e5ae09e TW	19	#include <asm/io.h>
4e5ae09e TW	20	#include <asm/bitops.h>
150c2493	21	#include <asm/arch/tegra.h>
4e5ae09e	22	#include <asm/gpio.h>
2fccd2d9	23	#include <dm/device-internal.h>
838aa5c9	24	#include <dt-bindings/gpio/gpio.h>
2fccd2d9 SG	25
2fccd2d9 SG	26	DECLARE_GLOBAL_DATA_PTR;
4e5ae09e	27
fe82857c SW	28	static const int CONFIG_SFIO = 0;
	29	static const int CONFIG_GPIO = 1;
	30	static const int DIRECTION_INPUT = 0;
	31	static const int DIRECTION_OUTPUT = 1;
	32
2fccd2d9 SG	33	struct tegra_gpio_platdata {
	34	struct gpio_ctlr_bank *bank;
	35	const char port_name; / Name of port, e.g. "B" */
	36	int base_gpio; /* Port number for this port (0, 1,.., n-1) */
	37	};
4e5ae09e	38
2fccd2d9 SG	39	/* Information about each port at run-time */
2fccd2d9 SG	40	struct tegra_port_info {
2fccd2d9 SG	41	struct gpio_ctlr_bank *bank;
	42	int base_gpio; /* Port number for this port (0, 1,.., n-1) */
	43	};
4e5ae09e	44
fe82857c	45	/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
365d6070	46	static int get_config(unsigned gpio)
4e5ae09e	47	{
365d6070 JH	48	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	49	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	50	u32 u;
	51	int type;
	52
365d6070	53	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
fe82857c	54	type = (u >> GPIO_BIT(gpio)) & 1;
4e5ae09e TW	55
4e5ae09e TW	56	debug("get_config: port = %d, bit = %d is %s\n",
365d6070	57	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
4e5ae09e	58
fe82857c	59	return type ? CONFIG_GPIO : CONFIG_SFIO;
4e5ae09e TW	60	}
4e5ae09e TW	61
fe82857c	62	/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
365d6070	63	static void set_config(unsigned gpio, int type)
4e5ae09e	64	{
365d6070 JH	65	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	66	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	67	u32 u;
	68
	69	debug("set_config: port = %d, bit = %d, %s\n",
365d6070	70	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
4e5ae09e	71
365d6070	72	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
fe82857c	73	if (type != CONFIG_SFIO)
365d6070	74	u \|= 1 << GPIO_BIT(gpio);
4e5ae09e	75	else
365d6070 JH	76	u &= ~(1 << GPIO_BIT(gpio));
365d6070 JH	77	writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
4e5ae09e TW	78	}
4e5ae09e TW	79
365d6070 JH	80	/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
365d6070 JH	81	static int get_direction(unsigned gpio)
4e5ae09e	82	{
365d6070 JH	83	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	84	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	85	u32 u;
	86	int dir;
	87
365d6070 JH	88	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
365d6070 JH	89	dir = (u >> GPIO_BIT(gpio)) & 1;
4e5ae09e TW	90
4e5ae09e TW	91	debug("get_direction: port = %d, bit = %d, %s\n",
365d6070	92	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
4e5ae09e	93
fe82857c	94	return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
4e5ae09e TW	95	}
4e5ae09e TW	96
365d6070 JH	97	/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
365d6070 JH	98	static void set_direction(unsigned gpio, int output)
4e5ae09e	99	{
365d6070 JH	100	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	101	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	102	u32 u;
	103
	104	debug("set_direction: port = %d, bit = %d, %s\n",
365d6070	105	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
4e5ae09e	106
365d6070	107	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
fe82857c	108	if (output != DIRECTION_INPUT)
365d6070	109	u \|= 1 << GPIO_BIT(gpio);
4e5ae09e	110	else
365d6070 JH	111	u &= ~(1 << GPIO_BIT(gpio));
365d6070 JH	112	writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
4e5ae09e TW	113	}
4e5ae09e TW	114
365d6070 JH	115	/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
365d6070 JH	116	static void set_level(unsigned gpio, int high)
4e5ae09e	117	{
365d6070 JH	118	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	119	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	120	u32 u;
	121
	122	debug("set_level: port = %d, bit %d == %d\n",
365d6070	123	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
4e5ae09e	124
365d6070	125	u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
4e5ae09e	126	if (high)
365d6070	127	u \|= 1 << GPIO_BIT(gpio);
4e5ae09e	128	else
365d6070 JH	129	u &= ~(1 << GPIO_BIT(gpio));
365d6070 JH	130	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
4e5ae09e TW	131	}
	132
	133	/*
	134	* Generic_GPIO primitives.
	135	*/
	136
365d6070	137	/* set GPIO pin 'gpio' as an input */
2fccd2d9	138	static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
4e5ae09e	139	{
2fccd2d9	140	struct tegra_port_info *state = dev_get_priv(dev);
4e5ae09e TW	141
4e5ae09e TW	142	/* Configure GPIO direction as input. */
fe82857c	143	set_direction(state->base_gpio + offset, DIRECTION_INPUT);
4e5ae09e	144
0c35e3a8 SW	145	/* Enable the pin as a GPIO */
	146	set_config(state->base_gpio + offset, 1);
	147
4e5ae09e TW	148	return 0;
	149	}
	150
365d6070	151	/* set GPIO pin 'gpio' as an output, with polarity 'value' */
2fccd2d9 SG	152	static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
2fccd2d9 SG	153	int value)
4e5ae09e	154	{
2fccd2d9 SG	155	struct tegra_port_info *state = dev_get_priv(dev);
2fccd2d9 SG	156	int gpio = state->base_gpio + offset;
4e5ae09e TW	157
4e5ae09e TW	158	/* Configure GPIO output value. */
365d6070	159	set_level(gpio, value);
4e5ae09e TW	160
4e5ae09e TW	161	/* Configure GPIO direction as output. */
fe82857c	162	set_direction(gpio, DIRECTION_OUTPUT);
4e5ae09e	163
0c35e3a8 SW	164	/* Enable the pin as a GPIO */
	165	set_config(state->base_gpio + offset, 1);
	166
4e5ae09e TW	167	return 0;
	168	}
	169
365d6070	170	/* read GPIO IN value of pin 'gpio' */
2fccd2d9	171	static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
4e5ae09e	172	{
2fccd2d9 SG	173	struct tegra_port_info *state = dev_get_priv(dev);
2fccd2d9 SG	174	int gpio = state->base_gpio + offset;
4e5ae09e TW	175	int val;
4e5ae09e TW	176
2fccd2d9 SG	177	debug("%s: pin = %d (port %d:bit %d)\n", __func__,
2fccd2d9 SG	178	gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
4e5ae09e	179
651827c0 SG	180	if (get_direction(gpio) == DIRECTION_INPUT)
	181	val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
	182	else
	183	val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
4e5ae09e	184
365d6070	185	return (val >> GPIO_BIT(gpio)) & 1;
4e5ae09e TW	186	}
4e5ae09e TW	187
365d6070	188	/* write GPIO OUT value to pin 'gpio' */
2fccd2d9	189	static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
4e5ae09e	190	{
2fccd2d9 SG	191	struct tegra_port_info *state = dev_get_priv(dev);
2fccd2d9 SG	192	int gpio = state->base_gpio + offset;
2fccd2d9	193
4e5ae09e	194	debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
2fccd2d9	195	gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
4e5ae09e TW	196
4e5ae09e TW	197	/* Configure GPIO output value. */
365d6070 JH	198	set_level(gpio, value);
	199
	200	return 0;
4e5ae09e TW	201	}
4e5ae09e TW	202
eceb3f26 SW	203	void gpio_config_table(const struct tegra_gpio_config *config, int len)
	204	{
	205	int i;
	206
	207	for (i = 0; i < len; i++) {
	208	switch (config[i].init) {
	209	case TEGRA_GPIO_INIT_IN:
fe82857c	210	set_direction(config[i].gpio, DIRECTION_INPUT);
eceb3f26 SW	211	break;
eceb3f26 SW	212	case TEGRA_GPIO_INIT_OUT0:
f9d3cab0	213	set_level(config[i].gpio, 0);
fe82857c	214	set_direction(config[i].gpio, DIRECTION_OUTPUT);
eceb3f26 SW	215	break;
eceb3f26 SW	216	case TEGRA_GPIO_INIT_OUT1:
f9d3cab0	217	set_level(config[i].gpio, 1);
fe82857c	218	set_direction(config[i].gpio, DIRECTION_OUTPUT);
eceb3f26 SW	219	break;
eceb3f26 SW	220	}
fe82857c	221	set_config(config[i].gpio, CONFIG_GPIO);
eceb3f26 SW	222	}
	223	}
	224
2fccd2d9 SG	225	static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
	226	{
	227	struct tegra_port_info *state = dev_get_priv(dev);
	228	int gpio = state->base_gpio + offset;
	229
2fccd2d9 SG	230	if (!get_config(gpio))
	231	return GPIOF_FUNC;
	232	else if (get_direction(gpio))
	233	return GPIOF_OUTPUT;
	234	else
	235	return GPIOF_INPUT;
	236	}
	237
838aa5c9	238	static int tegra_gpio_xlate(struct udevice dev, struct gpio_desc desc,
3a57123e	239	struct ofnode_phandle_args *args)
838aa5c9 SG	240	{
	241	int gpio, port, ret;
	242
	243	gpio = args->args[0];
	244	port = gpio / TEGRA_GPIOS_PER_PORT;
	245	ret = device_get_child(dev, port, &desc->dev);
	246	if (ret)
	247	return ret;
	248	desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
	249	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
	250
	251	return 0;
	252	}
	253
2fccd2d9	254	static const struct dm_gpio_ops gpio_tegra_ops = {
2fccd2d9 SG	255	.direction_input = tegra_gpio_direction_input,
	256	.direction_output = tegra_gpio_direction_output,
	257	.get_value = tegra_gpio_get_value,
	258	.set_value = tegra_gpio_set_value,
	259	.get_function = tegra_gpio_get_function,
838aa5c9	260	.xlate = tegra_gpio_xlate,
2fccd2d9 SG	261	};
	262
	263	/**
	264	* Returns the name of a GPIO port
	265	*
	266	* GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
	267	*
	268	* @base_port: Base port number (0, 1..n-1)
	269	* @return allocated string containing the name
4e5ae09e	270	*/
2fccd2d9	271	static char *gpio_port_name(int base_port)
4e5ae09e	272	{
2fccd2d9 SG	273	char name, s;
	274
	275	name = malloc(3);
	276	if (name) {
	277	s = name;
	278	*s++ = 'A' + (base_port % 26);
	279	if (base_port >= 26)
	280	s++ = name;
	281	*s = '\0';
	282	}
4e5ae09e	283
2fccd2d9 SG	284	return name;
	285	}
	286
	287	static const struct udevice_id tegra_gpio_ids[] = {
	288	{ .compatible = "nvidia,tegra30-gpio" },
	289	{ .compatible = "nvidia,tegra20-gpio" },
	290	{ }
	291	};
	292
	293	static int gpio_tegra_probe(struct udevice *dev)
	294	{
e564f054	295	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
2fccd2d9 SG	296	struct tegra_port_info *priv = dev->priv;
	297	struct tegra_gpio_platdata *plat = dev->platdata;
	298
	299	/* Only child devices have ports */
	300	if (!plat)
	301	return 0;
	302
	303	priv->bank = plat->bank;
	304	priv->base_gpio = plat->base_gpio;
	305
	306	uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
	307	uc_priv->bank_name = plat->port_name;
	308
	309	return 0;
	310	}
	311
	312	/**
	313	* We have a top-level GPIO device with no actual GPIOs. It has a child
	314	* device for each Tegra port.
	315	*/
	316	static int gpio_tegra_bind(struct udevice *parent)
	317	{
	318	struct tegra_gpio_platdata *plat = parent->platdata;
	319	struct gpio_ctlr *ctlr;
	320	int bank_count;
	321	int bank;
	322	int ret;
2fccd2d9 SG	323
	324	/* If this is a child device, there is nothing to do here */
	325	if (plat)
	326	return 0;
	327
bdfb3416 SG	328	/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
	329	#ifdef CONFIG_SPL_BUILD
	330	ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	331	bank_count = TEGRA_GPIO_BANKS;
	332	#else
	333	{
	334	int len;
	335
2fccd2d9 SG	336	/*
	337	* This driver does not make use of interrupts, other than to figure
	338	* out the number of GPIO banks
	339	*/
56f5c40a SG	340	len = dev_read_size(parent, "interrupts");
	341	if (len < 0)
	342	return len;
2fccd2d9	343	bank_count = len / 3 / sizeof(u32);
56f5c40a SG	344	ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
	345	if ((ulong)ctlr == FDT_ADDR_T_NONE)
	346	return -EINVAL;
bdfb3416 SG	347	}
bdfb3416 SG	348	#endif
2fccd2d9 SG	349	for (bank = 0; bank < bank_count; bank++) {
	350	int port;
	351
	352	for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
	353	struct tegra_gpio_platdata *plat;
	354	struct udevice *dev;
	355	int base_port;
	356
	357	plat = calloc(1, sizeof(*plat));
	358	if (!plat)
	359	return -ENOMEM;
	360	plat->bank = &ctlr->gpio_bank[bank];
	361	base_port = bank * TEGRA_PORTS_PER_BANK + port;
	362	plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
	363	plat->port_name = gpio_port_name(base_port);
	364
	365	ret = device_bind(parent, parent->driver,
	366	plat->port_name, plat, -1, &dev);
	367	if (ret)
	368	return ret;
e160f7d4	369	dev_set_of_offset(dev, dev_of_offset(parent));
2fccd2d9	370	}
4e5ae09e	371	}
2fccd2d9 SG	372
2fccd2d9 SG	373	return 0;
4e5ae09e	374	}
2fccd2d9 SG	375
	376	U_BOOT_DRIVER(gpio_tegra) = {
	377	.name = "gpio_tegra",
	378	.id = UCLASS_GPIO,
	379	.of_match = tegra_gpio_ids,
	380	.bind = gpio_tegra_bind,
	381	.probe = gpio_tegra_probe,
	382	.priv_auto_alloc_size = sizeof(struct tegra_port_info),
	383	.ops = &gpio_tegra_ops,
bdfb3416	384	.flags = DM_FLAG_PRE_RELOC,
2fccd2d9	385	};