[people/ms/u-boot.git] / drivers / i2c / designware_i2c.c

/*
 * (C) Copyright 2009
 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <pci.h>
#include <asm/io.h>
#include "designware_i2c.h"

struct dw_scl_sda_cfg {
	u32 ss_hcnt;
	u32 fs_hcnt;
	u32 ss_lcnt;
	u32 fs_lcnt;
	u32 sda_hold;
};

#ifdef CONFIG_X86
/* BayTrail HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg byt_config = {
	.ss_hcnt = 0x200,
	.fs_hcnt = 0x55,
	.ss_lcnt = 0x200,
	.fs_lcnt = 0x99,
	.sda_hold = 0x6,
};
#endif

struct dw_i2c {
	struct i2c_regs *regs;
	struct dw_scl_sda_cfg *scl_sda_cfg;
};

#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;

	writel(ena, &i2c_base->ic_enable);
}
#else
static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;
	int timeout = 100;

	do {
		writel(ena, &i2c_base->ic_enable);
		if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
			return;

		/*
		 * Wait 10 times the signaling period of the highest I2C
		 * transfer supported by the driver (for 400KHz this is
		 * 25us) as described in the DesignWare I2C databook.
		 */
		udelay(25);
	} while (timeout--);

	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
}
#endif

/*
 * i2c_set_bus_speed - Set the i2c speed
 * @speed:	required i2c speed
 *
 * Set the i2c speed.
 */
static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
					   struct dw_scl_sda_cfg *scl_sda_cfg,
					   unsigned int speed)
{
	unsigned int cntl;
	unsigned int hcnt, lcnt;
	int i2c_spd;

	if (speed >= I2C_MAX_SPEED)
		i2c_spd = IC_SPEED_MODE_MAX;
	else if (speed >= I2C_FAST_SPEED)
		i2c_spd = IC_SPEED_MODE_FAST;
	else
		i2c_spd = IC_SPEED_MODE_STANDARD;

	/* to set speed cltr must be disabled */
	dw_i2c_enable(i2c_base, false);

	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));

	switch (i2c_spd) {
#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
	case IC_SPEED_MODE_MAX:
		cntl |= IC_CON_SPD_SS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->fs_hcnt;
			lcnt = scl_sda_cfg->fs_lcnt;
		} else {
			hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
			lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
		}
		writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
		writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
		break;
#endif

	case IC_SPEED_MODE_STANDARD:
		cntl |= IC_CON_SPD_SS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->ss_hcnt;
			lcnt = scl_sda_cfg->ss_lcnt;
		} else {
			hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
			lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
		}
		writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
		writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
		break;

	case IC_SPEED_MODE_FAST:
	default:
		cntl |= IC_CON_SPD_FS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->fs_hcnt;
			lcnt = scl_sda_cfg->fs_lcnt;
		} else {
			hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
			lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
		}
		writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
		writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
		break;
	}

	writel(cntl, &i2c_base->ic_con);

	/* Configure SDA Hold Time if required */
	if (scl_sda_cfg)
		writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);

	/* Enable back i2c now speed set */
	dw_i2c_enable(i2c_base, true);

	return 0;
}

/*
 * i2c_setaddress - Sets the target slave address
 * @i2c_addr:	target i2c address
 *
 * Sets the target slave address.
 */
static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
{
	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel(i2c_addr, &i2c_base->ic_tar);

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 *
 * Flushes the i2c RX FIFO
 */
static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
{
	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
		readl(&i2c_base->ic_cmd_data);
}

/*
 * i2c_wait_for_bb - Waits for bus busy
 *
 * Waits for bus busy
 */
static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
{
	unsigned long start_time_bb = get_timer(0);

	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
	       !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {

		/* Evaluate timeout */
		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
			return 1;
	}

	return 0;
}

static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
			 int alen)
{
	if (i2c_wait_for_bb(i2c_base))
		return 1;

	i2c_setaddress(i2c_base, chip);
	while (alen) {
		alen--;
		/* high byte address going out first */
		writel((addr >> (alen * 8)) & 0xff,
		       &i2c_base->ic_cmd_data);
	}
	return 0;
}

static int i2c_xfer_finish(struct i2c_regs *i2c_base)
{
	ulong start_stop_det = get_timer(0);

	while (1) {
		if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
			readl(&i2c_base->ic_clr_stop_det);
			break;
		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
			break;
		}
	}

	if (i2c_wait_for_bb(i2c_base)) {
		printf("Timed out waiting for bus\n");
		return 1;
	}

	i2c_flush_rxfifo(i2c_base);

	return 0;
}

/*
 * i2c_read - Read from i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Read from i2c memory.
 */
static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
			 int alen, u8 *buffer, int len)
{
	unsigned long start_time_rx;
	unsigned int active = 0;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(i2c_base, dev, addr, alen))
		return 1;

	start_time_rx = get_timer(0);
	while (len) {
		if (!active) {
			/*
			 * Avoid writing to ic_cmd_data multiple times
			 * in case this loop spins too quickly and the
			 * ic_status RFNE bit isn't set after the first
			 * write. Subsequent writes to ic_cmd_data can
			 * trigger spurious i2c transfer.
			 */
			if (len == 1)
				writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
			else
				writel(IC_CMD, &i2c_base->ic_cmd_data);
			active = 1;
		}

		if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
			*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
			len--;
			start_time_rx = get_timer(0);
			active = 0;
		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
			return 1;
		}
	}

	return i2c_xfer_finish(i2c_base);
}

/*
 * i2c_write - Write to i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Write to i2c memory.
 */
static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
			  int alen, u8 *buffer, int len)
{
	int nb = len;
	unsigned long start_time_tx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(i2c_base, dev, addr, alen))
		return 1;

	start_time_tx = get_timer(0);
	while (len) {
		if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
			if (--len == 0) {
				writel(*buffer | IC_STOP,
				       &i2c_base->ic_cmd_data);
			} else {
				writel(*buffer, &i2c_base->ic_cmd_data);
			}
			buffer++;
			start_time_tx = get_timer(0);

		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
				printf("Timed out. i2c write Failed\n");
				return 1;
		}
	}

	return i2c_xfer_finish(i2c_base);
}

/*
 * __dw_i2c_init - Init function
 * @speed:	required i2c speed
 * @slaveaddr:	slave address for the device
 *
 * Initialization function.
 */
static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
{
	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
#ifndef CONFIG_DM_I2C
	__dw_i2c_set_bus_speed(i2c_base, NULL, speed);
	writel(slaveaddr, &i2c_base->ic_sar);
#endif

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

#ifndef CONFIG_DM_I2C
/*
 * The legacy I2C functions. These need to get removed once
 * all users of this driver are converted to DM.
 */
static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 4
	case 3:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
#endif
	case 0:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	default:
		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	}

	return NULL;
}

static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
					 unsigned int speed)
{
	adap->speed = speed;
	return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
}

static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
}

static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
		       int alen, u8 *buffer, int len)
{
	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
}

static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			int alen, u8 *buffer, int len)
{
	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
}

/* dw_i2c_probe - Probe the i2c chip */
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	u32 tmp;
	int ret;

	/*
	 * Try to read the first location of the chip.
	 */
	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		dw_i2c_init(adap, adap->speed, adap->slaveaddr);

	return ret;
}

U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)

#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 4
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif

#else /* CONFIG_DM_I2C */
/* The DM I2C functions */

static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			       int nmsgs)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	int ret;

	debug("i2c_xfer: %d messages\n", nmsgs);
	for (; nmsgs > 0; nmsgs--, msg++) {
		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD) {
			ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
					    msg->buf, msg->len);
		} else {
			ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
					     msg->buf, msg->len);
		}
		if (ret) {
			debug("i2c_write: error sending\n");
			return -EREMOTEIO;
		}
	}

	return 0;
}

static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	struct dw_i2c *i2c = dev_get_priv(bus);

	return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
}

static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
				     uint chip_flags)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	struct i2c_regs *i2c_base = i2c->regs;
	u32 tmp;
	int ret;

	/* Try to read the first location of the chip */
	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		__dw_i2c_init(i2c_base, 0, 0);

	return ret;
}

static int designware_i2c_probe(struct udevice *bus)
{
	struct dw_i2c *priv = dev_get_priv(bus);

	if (device_is_on_pci_bus(bus)) {
#ifdef CONFIG_DM_PCI
		/* Save base address from PCI BAR */
		priv->regs = (struct i2c_regs *)
			dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
#ifdef CONFIG_X86
		/* Use BayTrail specific timing values */
		priv->scl_sda_cfg = &byt_config;
#endif
#endif
	} else {
		priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
	}

	__dw_i2c_init(priv->regs, 0, 0);

	return 0;
}

static int designware_i2c_bind(struct udevice *dev)
{
	static int num_cards;
	char name[20];

	/* Create a unique device name for PCI type devices */
	if (device_is_on_pci_bus(dev)) {
		/*
		 * ToDo:
		 * Setting req_seq in the driver is probably not recommended.
		 * But without a DT alias the number is not configured. And
		 * using this driver is impossible for PCIe I2C devices.
		 * This can be removed, once a better (correct) way for this
		 * is found and implemented.
		 */
		dev->req_seq = num_cards;
		sprintf(name, "i2c_designware#%u", num_cards++);
		device_set_name(dev, name);
	}

	return 0;
}

static const struct dm_i2c_ops designware_i2c_ops = {
	.xfer		= designware_i2c_xfer,
	.probe_chip	= designware_i2c_probe_chip,
	.set_bus_speed	= designware_i2c_set_bus_speed,
};

static const struct udevice_id designware_i2c_ids[] = {
	{ .compatible = "snps,designware-i2c" },
	{ }
};

U_BOOT_DRIVER(i2c_designware) = {
	.name	= "i2c_designware",
	.id	= UCLASS_I2C,
	.of_match = designware_i2c_ids,
	.bind	= designware_i2c_bind,
	.probe	= designware_i2c_probe,
	.priv_auto_alloc_size = sizeof(struct dw_i2c),
	.ops	= &designware_i2c_ops,
};

#ifdef CONFIG_X86
static struct pci_device_id designware_pci_supported[] = {
	/* Intel BayTrail has 7 I2C controller located on the PCI bus */
	{ PCI_VDEVICE(INTEL, 0x0f41) },
	{ PCI_VDEVICE(INTEL, 0x0f42) },
	{ PCI_VDEVICE(INTEL, 0x0f43) },
	{ PCI_VDEVICE(INTEL, 0x0f44) },
	{ PCI_VDEVICE(INTEL, 0x0f45) },
	{ PCI_VDEVICE(INTEL, 0x0f46) },
	{ PCI_VDEVICE(INTEL, 0x0f47) },
	{},
};

U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
#endif

#endif /* CONFIG_DM_I2C */
Commit	Line	Data
2403f8f4 VK	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
2403f8f4 VK	6	*/
	7
	8	#include <common.h>
334b9b00	9	#include <dm.h>
678398b1	10	#include <i2c.h>
ba5da550	11	#include <pci.h>
2403f8f4	12	#include <asm/io.h>
031ed2fa	13	#include "designware_i2c.h"
2403f8f4	14
ba5da550 SR	15	struct dw_scl_sda_cfg {
	16	u32 ss_hcnt;
	17	u32 fs_hcnt;
	18	u32 ss_lcnt;
	19	u32 fs_lcnt;
	20	u32 sda_hold;
	21	};
	22
	23	#ifdef CONFIG_X86
	24	/* BayTrail HCNT/LCNT/SDA hold time */
	25	static struct dw_scl_sda_cfg byt_config = {
	26	.ss_hcnt = 0x200,
	27	.fs_hcnt = 0x55,
	28	.ss_lcnt = 0x200,
	29	.fs_lcnt = 0x99,
	30	.sda_hold = 0x6,
	31	};
	32	#endif
	33
334b9b00 SR	34	struct dw_i2c {
334b9b00 SR	35	struct i2c_regs *regs;
ba5da550	36	struct dw_scl_sda_cfg *scl_sda_cfg;
334b9b00 SR	37	};
334b9b00 SR	38
b6a77b0c SR	39	#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
	40	static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
	41	{
	42	u32 ena = enable ? IC_ENABLE_0B : 0;
	43
	44	writel(ena, &i2c_base->ic_enable);
	45	}
	46	#else
1c8b089b SR	47	static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
	48	{
	49	u32 ena = enable ? IC_ENABLE_0B : 0;
	50	int timeout = 100;
	51
	52	do {
	53	writel(ena, &i2c_base->ic_enable);
	54	if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
	55	return;
	56
	57	/*
	58	* Wait 10 times the signaling period of the highest I2C
	59	* transfer supported by the driver (for 400KHz this is
	60	* 25us) as described in the DesignWare I2C databook.
	61	*/
	62	udelay(25);
	63	} while (timeout--);
	64
	65	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
	66	}
b6a77b0c	67	#endif
1c8b089b	68
2403f8f4	69	/*
11b544ab SR	70	* i2c_set_bus_speed - Set the i2c speed
11b544ab SR	71	* @speed: required i2c speed
2403f8f4	72	*
11b544ab	73	* Set the i2c speed.
2403f8f4	74	*/
3f4358da	75	static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
ba5da550	76	struct dw_scl_sda_cfg *scl_sda_cfg,
3f4358da	77	unsigned int speed)
2403f8f4 VK	78	{
	79	unsigned int cntl;
	80	unsigned int hcnt, lcnt;
11b544ab SR	81	int i2c_spd;
	82
	83	if (speed >= I2C_MAX_SPEED)
	84	i2c_spd = IC_SPEED_MODE_MAX;
	85	else if (speed >= I2C_FAST_SPEED)
	86	i2c_spd = IC_SPEED_MODE_FAST;
	87	else
	88	i2c_spd = IC_SPEED_MODE_STANDARD;
5e3e8dda AV	89
5e3e8dda AV	90	/* to set speed cltr must be disabled */
1c8b089b	91	dw_i2c_enable(i2c_base, false);
5e3e8dda	92
678398b1	93	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
2403f8f4 VK	94
2403f8f4 VK	95	switch (i2c_spd) {
ba5da550	96	#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
2403f8f4	97	case IC_SPEED_MODE_MAX:
ba5da550 SR	98	cntl \|= IC_CON_SPD_SS;
	99	if (scl_sda_cfg) {
	100	hcnt = scl_sda_cfg->fs_hcnt;
	101	lcnt = scl_sda_cfg->fs_lcnt;
	102	} else {
	103	hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
	104	lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
	105	}
678398b1	106	writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
678398b1	107	writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
2403f8f4	108	break;
ba5da550	109	#endif
2403f8f4 VK	110
	111	case IC_SPEED_MODE_STANDARD:
	112	cntl \|= IC_CON_SPD_SS;
ba5da550 SR	113	if (scl_sda_cfg) {
	114	hcnt = scl_sda_cfg->ss_hcnt;
	115	lcnt = scl_sda_cfg->ss_lcnt;
	116	} else {
	117	hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
	118	lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
	119	}
678398b1	120	writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
678398b1	121	writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
2403f8f4 VK	122	break;
	123
	124	case IC_SPEED_MODE_FAST:
	125	default:
	126	cntl \|= IC_CON_SPD_FS;
ba5da550 SR	127	if (scl_sda_cfg) {
	128	hcnt = scl_sda_cfg->fs_hcnt;
	129	lcnt = scl_sda_cfg->fs_lcnt;
	130	} else {
	131	hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
	132	lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
	133	}
678398b1	134	writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
678398b1	135	writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
2403f8f4 VK	136	break;
	137	}
	138
678398b1	139	writel(cntl, &i2c_base->ic_con);
2403f8f4	140
ba5da550 SR	141	/* Configure SDA Hold Time if required */
	142	if (scl_sda_cfg)
	143	writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
	144
5b8439bb	145	/* Enable back i2c now speed set */
1c8b089b	146	dw_i2c_enable(i2c_base, true);
496ba48f	147
2403f8f4 VK	148	return 0;
	149	}
	150
2403f8f4 VK	151	/*
	152	* i2c_setaddress - Sets the target slave address
	153	* @i2c_addr: target i2c address
	154	*
	155	* Sets the target slave address.
	156	*/
3f4358da	157	static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
2403f8f4	158	{
8b7c8725	159	/* Disable i2c */
1c8b089b	160	dw_i2c_enable(i2c_base, false);
8b7c8725	161
678398b1	162	writel(i2c_addr, &i2c_base->ic_tar);
8b7c8725 AB	163
8b7c8725 AB	164	/* Enable i2c */
1c8b089b	165	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	166	}
	167
	168	/*
	169	* i2c_flush_rxfifo - Flushes the i2c RX FIFO
	170	*
	171	* Flushes the i2c RX FIFO
	172	*/
3f4358da	173	static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
2403f8f4	174	{
678398b1 SR	175	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
678398b1 SR	176	readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	177	}
	178
	179	/*
	180	* i2c_wait_for_bb - Waits for bus busy
	181	*
	182	* Waits for bus busy
	183	*/
3f4358da	184	static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
2403f8f4 VK	185	{
	186	unsigned long start_time_bb = get_timer(0);
	187
678398b1 SR	188	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) \|\|
678398b1 SR	189	!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
2403f8f4 VK	190
	191	/* Evaluate timeout */
	192	if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
	193	return 1;
	194	}
	195
	196	return 0;
	197	}
	198
3f4358da	199	static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
678398b1	200	int alen)
2403f8f4	201	{
3f4358da	202	if (i2c_wait_for_bb(i2c_base))
2403f8f4	203	return 1;
2403f8f4	204
3f4358da	205	i2c_setaddress(i2c_base, chip);
070cbaf8 CLS	206	while (alen) {
	207	alen--;
	208	/* high byte address going out first */
	209	writel((addr >> (alen * 8)) & 0xff,
678398b1	210	&i2c_base->ic_cmd_data);
070cbaf8	211	}
2403f8f4 VK	212	return 0;
	213	}
	214
3f4358da	215	static int i2c_xfer_finish(struct i2c_regs *i2c_base)
2403f8f4 VK	216	{
	217	ulong start_stop_det = get_timer(0);
	218
	219	while (1) {
678398b1 SR	220	if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
678398b1 SR	221	readl(&i2c_base->ic_clr_stop_det);
2403f8f4 VK	222	break;
	223	} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
	224	break;
	225	}
	226	}
	227
3f4358da	228	if (i2c_wait_for_bb(i2c_base)) {
2403f8f4 VK	229	printf("Timed out waiting for bus\n");
	230	return 1;
	231	}
	232
3f4358da	233	i2c_flush_rxfifo(i2c_base);
2403f8f4	234
2403f8f4 VK	235	return 0;
	236	}
	237
	238	/*
	239	* i2c_read - Read from i2c memory
	240	* @chip: target i2c address
	241	* @addr: address to read from
	242	* @alen:
	243	* @buffer: buffer for read data
	244	* @len: no of bytes to be read
	245	*
	246	* Read from i2c memory.
	247	*/
3f4358da SR	248	static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
3f4358da SR	249	int alen, u8 *buffer, int len)
2403f8f4 VK	250	{
2403f8f4 VK	251	unsigned long start_time_rx;
b0338080	252	unsigned int active = 0;
2403f8f4	253
32d041e2 AB	254	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	255	/*
	256	* EEPROM chips that implement "address overflow" are ones
	257	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	258	* address and the extra bits end up in the "chip address"
	259	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	260	* four 256 byte chips.
	261	*
	262	* Note that we consider the length of the address field to
	263	* still be one byte because the extra address bits are
	264	* hidden in the chip address.
	265	*/
678398b1	266	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	267	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	268
678398b1	269	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	270	addr);
	271	#endif
	272
3f4358da	273	if (i2c_xfer_init(i2c_base, dev, addr, alen))
2403f8f4 VK	274	return 1;
	275
	276	start_time_rx = get_timer(0);
	277	while (len) {
b0338080 MV	278	if (!active) {
	279	/*
	280	* Avoid writing to ic_cmd_data multiple times
	281	* in case this loop spins too quickly and the
	282	* ic_status RFNE bit isn't set after the first
	283	* write. Subsequent writes to ic_cmd_data can
	284	* trigger spurious i2c transfer.
	285	*/
	286	if (len == 1)
	287	writel(IC_CMD \| IC_STOP, &i2c_base->ic_cmd_data);
	288	else
	289	writel(IC_CMD, &i2c_base->ic_cmd_data);
	290	active = 1;
	291	}
2403f8f4	292
678398b1 SR	293	if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
678398b1 SR	294	*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	295	len--;
2403f8f4 VK	296	start_time_rx = get_timer(0);
b0338080	297	active = 0;
2403f8f4	298	} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
b0338080	299	return 1;
2403f8f4 VK	300	}
	301	}
	302
3f4358da	303	return i2c_xfer_finish(i2c_base);
2403f8f4 VK	304	}
	305
	306	/*
	307	* i2c_write - Write to i2c memory
	308	* @chip: target i2c address
	309	* @addr: address to read from
	310	* @alen:
	311	* @buffer: buffer for read data
	312	* @len: no of bytes to be read
	313	*
	314	* Write to i2c memory.
	315	*/
3f4358da SR	316	static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
3f4358da SR	317	int alen, u8 *buffer, int len)
2403f8f4 VK	318	{
	319	int nb = len;
	320	unsigned long start_time_tx;
	321
32d041e2 AB	322	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	323	/*
	324	* EEPROM chips that implement "address overflow" are ones
	325	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	326	* address and the extra bits end up in the "chip address"
	327	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	328	* four 256 byte chips.
	329	*
	330	* Note that we consider the length of the address field to
	331	* still be one byte because the extra address bits are
	332	* hidden in the chip address.
	333	*/
678398b1	334	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	335	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	336
678398b1	337	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	338	addr);
	339	#endif
	340
3f4358da	341	if (i2c_xfer_init(i2c_base, dev, addr, alen))
2403f8f4 VK	342	return 1;
	343
	344	start_time_tx = get_timer(0);
	345	while (len) {
678398b1 SR	346	if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
	347	if (--len == 0) {
	348	writel(*buffer \| IC_STOP,
	349	&i2c_base->ic_cmd_data);
	350	} else {
	351	writel(*buffer, &i2c_base->ic_cmd_data);
	352	}
2403f8f4	353	buffer++;
2403f8f4 VK	354	start_time_tx = get_timer(0);
	355
	356	} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
	357	printf("Timed out. i2c write Failed\n");
	358	return 1;
	359	}
	360	}
	361
3f4358da SR	362	return i2c_xfer_finish(i2c_base);
	363	}
	364
334b9b00 SR	365	/*
	366	* __dw_i2c_init - Init function
	367	* @speed: required i2c speed
	368	* @slaveaddr: slave address for the device
	369	*
	370	* Initialization function.
	371	*/
	372	static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
	373	{
	374	/* Disable i2c */
	375	dw_i2c_enable(i2c_base, false);
	376
	377	writel((IC_CON_SD \| IC_CON_SPD_FS \| IC_CON_MM), &i2c_base->ic_con);
	378	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	379	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	380	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	381	#ifndef CONFIG_DM_I2C
ba5da550	382	__dw_i2c_set_bus_speed(i2c_base, NULL, speed);
334b9b00 SR	383	writel(slaveaddr, &i2c_base->ic_sar);
	384	#endif
	385
	386	/* Enable i2c */
	387	dw_i2c_enable(i2c_base, true);
	388	}
	389
	390	#ifndef CONFIG_DM_I2C
	391	/*
	392	* The legacy I2C functions. These need to get removed once
	393	* all users of this driver are converted to DM.
	394	*/
3f4358da SR	395	static struct i2c_regs i2c_get_base(struct i2c_adapter adap)
	396	{
	397	switch (adap->hwadapnr) {
	398	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	399	case 3:
	400	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
	401	#endif
	402	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	403	case 2:
	404	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
	405	#endif
	406	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	407	case 1:
	408	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
	409	#endif
	410	case 0:
	411	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	412	default:
	413	printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	414	}
	415
	416	return NULL;
	417	}
	418
	419	static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
	420	unsigned int speed)
	421	{
	422	adap->speed = speed;
ba5da550	423	return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
3f4358da SR	424	}
3f4358da SR	425
334b9b00	426	static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
3f4358da	427	{
334b9b00	428	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
3f4358da SR	429	}
	430
	431	static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
	432	int alen, u8 *buffer, int len)
	433	{
	434	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
	435	}
	436
	437	static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
	438	int alen, u8 *buffer, int len)
	439	{
	440	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
2403f8f4 VK	441	}
2403f8f4 VK	442
334b9b00	443	/* dw_i2c_probe - Probe the i2c chip */
678398b1	444	static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
2403f8f4	445	{
3f4358da	446	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4	447	u32 tmp;
496ba48f	448	int ret;
2403f8f4 VK	449
	450	/*
	451	* Try to read the first location of the chip.
	452	*/
3f4358da	453	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
496ba48f	454	if (ret)
678398b1	455	dw_i2c_init(adap, adap->speed, adap->slaveaddr);
496ba48f SR	456
496ba48f SR	457	return ret;
2403f8f4	458	}
ac6e2fe6	459
678398b1 SR	460	U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	461	dw_i2c_write, dw_i2c_set_bus_speed,
	462	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
ac6e2fe6	463
678398b1 SR	464	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	465	U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	466	dw_i2c_write, dw_i2c_set_bus_speed,
	467	CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
	468	#endif
ac6e2fe6	469
678398b1 SR	470	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	471	U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	472	dw_i2c_write, dw_i2c_set_bus_speed,
	473	CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
	474	#endif
ac6e2fe6	475
678398b1 SR	476	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	477	U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	478	dw_i2c_write, dw_i2c_set_bus_speed,
	479	CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
ac6e2fe6	480	#endif
334b9b00 SR	481
	482	#else /* CONFIG_DM_I2C */
	483	/* The DM I2C functions */
	484
	485	static int designware_i2c_xfer(struct udevice bus, struct i2c_msg msg,
	486	int nmsgs)
	487	{
	488	struct dw_i2c *i2c = dev_get_priv(bus);
	489	int ret;
	490
	491	debug("i2c_xfer: %d messages\n", nmsgs);
	492	for (; nmsgs > 0; nmsgs--, msg++) {
	493	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	494	if (msg->flags & I2C_M_RD) {
	495	ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
	496	msg->buf, msg->len);
	497	} else {
	498	ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
	499	msg->buf, msg->len);
	500	}
	501	if (ret) {
	502	debug("i2c_write: error sending\n");
	503	return -EREMOTEIO;
	504	}
	505	}
	506
	507	return 0;
	508	}
	509
	510	static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	511	{
	512	struct dw_i2c *i2c = dev_get_priv(bus);
	513
ba5da550	514	return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
334b9b00 SR	515	}
	516
	517	static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
	518	uint chip_flags)
	519	{
	520	struct dw_i2c *i2c = dev_get_priv(bus);
	521	struct i2c_regs *i2c_base = i2c->regs;
	522	u32 tmp;
	523	int ret;
	524
	525	/* Try to read the first location of the chip */
	526	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
	527	if (ret)
	528	__dw_i2c_init(i2c_base, 0, 0);
	529
	530	return ret;
	531	}
	532
	533	static int designware_i2c_probe(struct udevice *bus)
	534	{
	535	struct dw_i2c *priv = dev_get_priv(bus);
	536
ba5da550 SR	537	if (device_is_on_pci_bus(bus)) {
	538	#ifdef CONFIG_DM_PCI
	539	/* Save base address from PCI BAR */
	540	priv->regs = (struct i2c_regs *)
	541	dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
	542	#ifdef CONFIG_X86
	543	/* Use BayTrail specific timing values */
	544	priv->scl_sda_cfg = &byt_config;
	545	#endif
	546	#endif
	547	} else {
	548	priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
	549	}
334b9b00 SR	550
	551	__dw_i2c_init(priv->regs, 0, 0);
	552
	553	return 0;
	554	}
	555
ba5da550 SR	556	static int designware_i2c_bind(struct udevice *dev)
	557	{
	558	static int num_cards;
	559	char name[20];
	560
	561	/* Create a unique device name for PCI type devices */
	562	if (device_is_on_pci_bus(dev)) {
	563	/*
	564	* ToDo:
	565	* Setting req_seq in the driver is probably not recommended.
	566	* But without a DT alias the number is not configured. And
	567	* using this driver is impossible for PCIe I2C devices.
	568	* This can be removed, once a better (correct) way for this
	569	* is found and implemented.
	570	*/
	571	dev->req_seq = num_cards;
	572	sprintf(name, "i2c_designware#%u", num_cards++);
	573	device_set_name(dev, name);
	574	}
	575
	576	return 0;
	577	}
	578
334b9b00 SR	579	static const struct dm_i2c_ops designware_i2c_ops = {
	580	.xfer = designware_i2c_xfer,
	581	.probe_chip = designware_i2c_probe_chip,
	582	.set_bus_speed = designware_i2c_set_bus_speed,
	583	};
	584
	585	static const struct udevice_id designware_i2c_ids[] = {
	586	{ .compatible = "snps,designware-i2c" },
	587	{ }
	588	};
	589
	590	U_BOOT_DRIVER(i2c_designware) = {
	591	.name = "i2c_designware",
	592	.id = UCLASS_I2C,
	593	.of_match = designware_i2c_ids,
ba5da550	594	.bind = designware_i2c_bind,
334b9b00 SR	595	.probe = designware_i2c_probe,
	596	.priv_auto_alloc_size = sizeof(struct dw_i2c),
	597	.ops = &designware_i2c_ops,
	598	};
	599
ba5da550 SR	600	#ifdef CONFIG_X86
	601	static struct pci_device_id designware_pci_supported[] = {
	602	/* Intel BayTrail has 7 I2C controller located on the PCI bus */
	603	{ PCI_VDEVICE(INTEL, 0x0f41) },
	604	{ PCI_VDEVICE(INTEL, 0x0f42) },
	605	{ PCI_VDEVICE(INTEL, 0x0f43) },
	606	{ PCI_VDEVICE(INTEL, 0x0f44) },
	607	{ PCI_VDEVICE(INTEL, 0x0f45) },
	608	{ PCI_VDEVICE(INTEL, 0x0f46) },
	609	{ PCI_VDEVICE(INTEL, 0x0f47) },
	610	{},
	611	};
	612
	613	U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
	614	#endif
	615
334b9b00	616	#endif /* CONFIG_DM_I2C */