[people/ms/u-boot.git] / drivers / i2c / designware_i2c.c

/*
 * (C) Copyright 2009
 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <pci.h>
#include <asm/io.h>
#include "designware_i2c.h"

struct dw_scl_sda_cfg {
	u32 ss_hcnt;
	u32 fs_hcnt;
	u32 ss_lcnt;
	u32 fs_lcnt;
	u32 sda_hold;
};

#ifdef CONFIG_X86
/* BayTrail HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg byt_config = {
	.ss_hcnt = 0x200,
	.fs_hcnt = 0x55,
	.ss_lcnt = 0x200,
	.fs_lcnt = 0x99,
	.sda_hold = 0x6,
};
#endif

struct dw_i2c {
	struct i2c_regs *regs;
	struct dw_scl_sda_cfg *scl_sda_cfg;
};

static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;
	int timeout = 100;

	do {
		writel(ena, &i2c_base->ic_enable);
		if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
			return;

		/*
		 * Wait 10 times the signaling period of the highest I2C
		 * transfer supported by the driver (for 400KHz this is
		 * 25us) as described in the DesignWare I2C databook.
		 */
		udelay(25);
	} while (timeout--);

	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
}

/*
 * i2c_set_bus_speed - Set the i2c speed
 * @speed:	required i2c speed
 *
 * Set the i2c speed.
 */
static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
					   struct dw_scl_sda_cfg *scl_sda_cfg,
					   unsigned int speed)
{
	unsigned int cntl;
	unsigned int hcnt, lcnt;
	int i2c_spd;

	if (speed >= I2C_MAX_SPEED)
		i2c_spd = IC_SPEED_MODE_MAX;
	else if (speed >= I2C_FAST_SPEED)
		i2c_spd = IC_SPEED_MODE_FAST;
	else
		i2c_spd = IC_SPEED_MODE_STANDARD;

	/* to set speed cltr must be disabled */
	dw_i2c_enable(i2c_base, false);

	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));

	switch (i2c_spd) {
#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
	case IC_SPEED_MODE_MAX:
		cntl |= IC_CON_SPD_SS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->fs_hcnt;
			lcnt = scl_sda_cfg->fs_lcnt;
		} else {
			hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
			lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
		}
		writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
		writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
		break;
#endif

	case IC_SPEED_MODE_STANDARD:
		cntl |= IC_CON_SPD_SS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->ss_hcnt;
			lcnt = scl_sda_cfg->ss_lcnt;
		} else {
			hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
			lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
		}
		writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
		writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
		break;

	case IC_SPEED_MODE_FAST:
	default:
		cntl |= IC_CON_SPD_FS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->fs_hcnt;
			lcnt = scl_sda_cfg->fs_lcnt;
		} else {
			hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
			lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
		}
		writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
		writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
		break;
	}

	writel(cntl, &i2c_base->ic_con);

	/* Configure SDA Hold Time if required */
	if (scl_sda_cfg)
		writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);

	/* Enable back i2c now speed set */
	dw_i2c_enable(i2c_base, true);

	return 0;
}

/*
 * i2c_setaddress - Sets the target slave address
 * @i2c_addr:	target i2c address
 *
 * Sets the target slave address.
 */
static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
{
	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel(i2c_addr, &i2c_base->ic_tar);

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 *
 * Flushes the i2c RX FIFO
 */
static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
{
	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
		readl(&i2c_base->ic_cmd_data);
}

/*
 * i2c_wait_for_bb - Waits for bus busy
 *
 * Waits for bus busy
 */
static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
{
	unsigned long start_time_bb = get_timer(0);

	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
	       !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {

		/* Evaluate timeout */
		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
			return 1;
	}

	return 0;
}

static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
			 int alen)
{
	if (i2c_wait_for_bb(i2c_base))
		return 1;

	i2c_setaddress(i2c_base, chip);
	while (alen) {
		alen--;
		/* high byte address going out first */
		writel((addr >> (alen * 8)) & 0xff,
		       &i2c_base->ic_cmd_data);
	}
	return 0;
}

static int i2c_xfer_finish(struct i2c_regs *i2c_base)
{
	ulong start_stop_det = get_timer(0);

	while (1) {
		if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
			readl(&i2c_base->ic_clr_stop_det);
			break;
		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
			break;
		}
	}

	if (i2c_wait_for_bb(i2c_base)) {
		printf("Timed out waiting for bus\n");
		return 1;
	}

	i2c_flush_rxfifo(i2c_base);

	return 0;
}

/*
 * i2c_read - Read from i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Read from i2c memory.
 */
static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
			 int alen, u8 *buffer, int len)
{
	unsigned long start_time_rx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(i2c_base, dev, addr, alen))
		return 1;

	start_time_rx = get_timer(0);
	while (len) {
		if (len == 1)
			writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
		else
			writel(IC_CMD, &i2c_base->ic_cmd_data);

		if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
			*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
			len--;
			start_time_rx = get_timer(0);

		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
				return 1;
		}
	}

	return i2c_xfer_finish(i2c_base);
}

/*
 * i2c_write - Write to i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Write to i2c memory.
 */
static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
			  int alen, u8 *buffer, int len)
{
	int nb = len;
	unsigned long start_time_tx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(i2c_base, dev, addr, alen))
		return 1;

	start_time_tx = get_timer(0);
	while (len) {
		if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
			if (--len == 0) {
				writel(*buffer | IC_STOP,
				       &i2c_base->ic_cmd_data);
			} else {
				writel(*buffer, &i2c_base->ic_cmd_data);
			}
			buffer++;
			start_time_tx = get_timer(0);

		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
				printf("Timed out. i2c write Failed\n");
				return 1;
		}
	}

	return i2c_xfer_finish(i2c_base);
}

/*
 * __dw_i2c_init - Init function
 * @speed:	required i2c speed
 * @slaveaddr:	slave address for the device
 *
 * Initialization function.
 */
static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
{
	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
#ifndef CONFIG_DM_I2C
	__dw_i2c_set_bus_speed(i2c_base, NULL, speed);
	writel(slaveaddr, &i2c_base->ic_sar);
#endif

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

#ifndef CONFIG_DM_I2C
/*
 * The legacy I2C functions. These need to get removed once
 * all users of this driver are converted to DM.
 */
static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 4
	case 3:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
#endif
	case 0:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	default:
		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	}

	return NULL;
}

static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
					 unsigned int speed)
{
	adap->speed = speed;
	return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
}

static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
}

static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
		       int alen, u8 *buffer, int len)
{
	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
}

static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			int alen, u8 *buffer, int len)
{
	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
}

/* dw_i2c_probe - Probe the i2c chip */
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	u32 tmp;
	int ret;

	/*
	 * Try to read the first location of the chip.
	 */
	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		dw_i2c_init(adap, adap->speed, adap->slaveaddr);

	return ret;
}

U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)

#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 4
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif

#else /* CONFIG_DM_I2C */
/* The DM I2C functions */

static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			       int nmsgs)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	int ret;

	debug("i2c_xfer: %d messages\n", nmsgs);
	for (; nmsgs > 0; nmsgs--, msg++) {
		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD) {
			ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
					    msg->buf, msg->len);
		} else {
			ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
					     msg->buf, msg->len);
		}
		if (ret) {
			debug("i2c_write: error sending\n");
			return -EREMOTEIO;
		}
	}

	return 0;
}

static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	struct dw_i2c *i2c = dev_get_priv(bus);

	return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
}

static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
				     uint chip_flags)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	struct i2c_regs *i2c_base = i2c->regs;
	u32 tmp;
	int ret;

	/* Try to read the first location of the chip */
	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		__dw_i2c_init(i2c_base, 0, 0);

	return ret;
}

static int designware_i2c_probe(struct udevice *bus)
{
	struct dw_i2c *priv = dev_get_priv(bus);

	if (device_is_on_pci_bus(bus)) {
#ifdef CONFIG_DM_PCI
		/* Save base address from PCI BAR */
		priv->regs = (struct i2c_regs *)
			dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
#ifdef CONFIG_X86
		/* Use BayTrail specific timing values */
		priv->scl_sda_cfg = &byt_config;
#endif
#endif
	} else {
		priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
	}

	__dw_i2c_init(priv->regs, 0, 0);

	return 0;
}

static int designware_i2c_bind(struct udevice *dev)
{
	static int num_cards;
	char name[20];

	/* Create a unique device name for PCI type devices */
	if (device_is_on_pci_bus(dev)) {
		/*
		 * ToDo:
		 * Setting req_seq in the driver is probably not recommended.
		 * But without a DT alias the number is not configured. And
		 * using this driver is impossible for PCIe I2C devices.
		 * This can be removed, once a better (correct) way for this
		 * is found and implemented.
		 */
		dev->req_seq = num_cards;
		sprintf(name, "i2c_designware#%u", num_cards++);
		device_set_name(dev, name);
	}

	return 0;
}

static const struct dm_i2c_ops designware_i2c_ops = {
	.xfer		= designware_i2c_xfer,
	.probe_chip	= designware_i2c_probe_chip,
	.set_bus_speed	= designware_i2c_set_bus_speed,
};

static const struct udevice_id designware_i2c_ids[] = {
	{ .compatible = "snps,designware-i2c" },
	{ }
};

U_BOOT_DRIVER(i2c_designware) = {
	.name	= "i2c_designware",
	.id	= UCLASS_I2C,
	.of_match = designware_i2c_ids,
	.bind	= designware_i2c_bind,
	.probe	= designware_i2c_probe,
	.priv_auto_alloc_size = sizeof(struct dw_i2c),
	.ops	= &designware_i2c_ops,
};

#ifdef CONFIG_X86
static struct pci_device_id designware_pci_supported[] = {
	/* Intel BayTrail has 7 I2C controller located on the PCI bus */
	{ PCI_VDEVICE(INTEL, 0x0f41) },
	{ PCI_VDEVICE(INTEL, 0x0f42) },
	{ PCI_VDEVICE(INTEL, 0x0f43) },
	{ PCI_VDEVICE(INTEL, 0x0f44) },
	{ PCI_VDEVICE(INTEL, 0x0f45) },
	{ PCI_VDEVICE(INTEL, 0x0f46) },
	{ PCI_VDEVICE(INTEL, 0x0f47) },
	{},
};

U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
#endif

#endif /* CONFIG_DM_I2C */
Commit	Line	Data
2403f8f4 VK	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
2403f8f4 VK	6	*/
	7
	8	#include <common.h>
334b9b00	9	#include <dm.h>
678398b1	10	#include <i2c.h>
ba5da550	11	#include <pci.h>
2403f8f4	12	#include <asm/io.h>
031ed2fa	13	#include "designware_i2c.h"
2403f8f4	14
ba5da550 SR	15	struct dw_scl_sda_cfg {
	16	u32 ss_hcnt;
	17	u32 fs_hcnt;
	18	u32 ss_lcnt;
	19	u32 fs_lcnt;
	20	u32 sda_hold;
	21	};
	22
	23	#ifdef CONFIG_X86
	24	/* BayTrail HCNT/LCNT/SDA hold time */
	25	static struct dw_scl_sda_cfg byt_config = {
	26	.ss_hcnt = 0x200,
	27	.fs_hcnt = 0x55,
	28	.ss_lcnt = 0x200,
	29	.fs_lcnt = 0x99,
	30	.sda_hold = 0x6,
	31	};
	32	#endif
	33
334b9b00 SR	34	struct dw_i2c {
334b9b00 SR	35	struct i2c_regs *regs;
ba5da550	36	struct dw_scl_sda_cfg *scl_sda_cfg;
334b9b00 SR	37	};
334b9b00 SR	38
1c8b089b SR	39	static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
	40	{
	41	u32 ena = enable ? IC_ENABLE_0B : 0;
	42	int timeout = 100;
	43
	44	do {
	45	writel(ena, &i2c_base->ic_enable);
	46	if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
	47	return;
	48
	49	/*
	50	* Wait 10 times the signaling period of the highest I2C
	51	* transfer supported by the driver (for 400KHz this is
	52	* 25us) as described in the DesignWare I2C databook.
	53	*/
	54	udelay(25);
	55	} while (timeout--);
	56
	57	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
	58	}
	59
2403f8f4	60	/*
11b544ab SR	61	* i2c_set_bus_speed - Set the i2c speed
11b544ab SR	62	* @speed: required i2c speed
2403f8f4	63	*
11b544ab	64	* Set the i2c speed.
2403f8f4	65	*/
3f4358da	66	static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
ba5da550	67	struct dw_scl_sda_cfg *scl_sda_cfg,
3f4358da	68	unsigned int speed)
2403f8f4 VK	69	{
	70	unsigned int cntl;
	71	unsigned int hcnt, lcnt;
11b544ab SR	72	int i2c_spd;
	73
	74	if (speed >= I2C_MAX_SPEED)
	75	i2c_spd = IC_SPEED_MODE_MAX;
	76	else if (speed >= I2C_FAST_SPEED)
	77	i2c_spd = IC_SPEED_MODE_FAST;
	78	else
	79	i2c_spd = IC_SPEED_MODE_STANDARD;
5e3e8dda AV	80
5e3e8dda AV	81	/* to set speed cltr must be disabled */
1c8b089b	82	dw_i2c_enable(i2c_base, false);
5e3e8dda	83
678398b1	84	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
2403f8f4 VK	85
2403f8f4 VK	86	switch (i2c_spd) {
ba5da550	87	#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
2403f8f4	88	case IC_SPEED_MODE_MAX:
ba5da550 SR	89	cntl \|= IC_CON_SPD_SS;
	90	if (scl_sda_cfg) {
	91	hcnt = scl_sda_cfg->fs_hcnt;
	92	lcnt = scl_sda_cfg->fs_lcnt;
	93	} else {
	94	hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
	95	lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
	96	}
678398b1	97	writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
678398b1	98	writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
2403f8f4	99	break;
ba5da550	100	#endif
2403f8f4 VK	101
	102	case IC_SPEED_MODE_STANDARD:
	103	cntl \|= IC_CON_SPD_SS;
ba5da550 SR	104	if (scl_sda_cfg) {
	105	hcnt = scl_sda_cfg->ss_hcnt;
	106	lcnt = scl_sda_cfg->ss_lcnt;
	107	} else {
	108	hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
	109	lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
	110	}
678398b1	111	writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
678398b1	112	writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
2403f8f4 VK	113	break;
	114
	115	case IC_SPEED_MODE_FAST:
	116	default:
	117	cntl \|= IC_CON_SPD_FS;
ba5da550 SR	118	if (scl_sda_cfg) {
	119	hcnt = scl_sda_cfg->fs_hcnt;
	120	lcnt = scl_sda_cfg->fs_lcnt;
	121	} else {
	122	hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
	123	lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
	124	}
678398b1	125	writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
678398b1	126	writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
2403f8f4 VK	127	break;
	128	}
	129
678398b1	130	writel(cntl, &i2c_base->ic_con);
2403f8f4	131
ba5da550 SR	132	/* Configure SDA Hold Time if required */
	133	if (scl_sda_cfg)
	134	writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
	135
5b8439bb	136	/* Enable back i2c now speed set */
1c8b089b	137	dw_i2c_enable(i2c_base, true);
496ba48f	138
2403f8f4 VK	139	return 0;
	140	}
	141
2403f8f4 VK	142	/*
	143	* i2c_setaddress - Sets the target slave address
	144	* @i2c_addr: target i2c address
	145	*
	146	* Sets the target slave address.
	147	*/
3f4358da	148	static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
2403f8f4	149	{
8b7c8725	150	/* Disable i2c */
1c8b089b	151	dw_i2c_enable(i2c_base, false);
8b7c8725	152
678398b1	153	writel(i2c_addr, &i2c_base->ic_tar);
8b7c8725 AB	154
8b7c8725 AB	155	/* Enable i2c */
1c8b089b	156	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	157	}
	158
	159	/*
	160	* i2c_flush_rxfifo - Flushes the i2c RX FIFO
	161	*
	162	* Flushes the i2c RX FIFO
	163	*/
3f4358da	164	static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
2403f8f4	165	{
678398b1 SR	166	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
678398b1 SR	167	readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	168	}
	169
	170	/*
	171	* i2c_wait_for_bb - Waits for bus busy
	172	*
	173	* Waits for bus busy
	174	*/
3f4358da	175	static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
2403f8f4 VK	176	{
	177	unsigned long start_time_bb = get_timer(0);
	178
678398b1 SR	179	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) \|\|
678398b1 SR	180	!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
2403f8f4 VK	181
	182	/* Evaluate timeout */
	183	if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
	184	return 1;
	185	}
	186
	187	return 0;
	188	}
	189
3f4358da	190	static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
678398b1	191	int alen)
2403f8f4	192	{
3f4358da	193	if (i2c_wait_for_bb(i2c_base))
2403f8f4	194	return 1;
2403f8f4	195
3f4358da	196	i2c_setaddress(i2c_base, chip);
070cbaf8 CLS	197	while (alen) {
	198	alen--;
	199	/* high byte address going out first */
	200	writel((addr >> (alen * 8)) & 0xff,
678398b1	201	&i2c_base->ic_cmd_data);
070cbaf8	202	}
2403f8f4 VK	203	return 0;
	204	}
	205
3f4358da	206	static int i2c_xfer_finish(struct i2c_regs *i2c_base)
2403f8f4 VK	207	{
	208	ulong start_stop_det = get_timer(0);
	209
	210	while (1) {
678398b1 SR	211	if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
678398b1 SR	212	readl(&i2c_base->ic_clr_stop_det);
2403f8f4 VK	213	break;
	214	} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
	215	break;
	216	}
	217	}
	218
3f4358da	219	if (i2c_wait_for_bb(i2c_base)) {
2403f8f4 VK	220	printf("Timed out waiting for bus\n");
	221	return 1;
	222	}
	223
3f4358da	224	i2c_flush_rxfifo(i2c_base);
2403f8f4	225
2403f8f4 VK	226	return 0;
	227	}
	228
	229	/*
	230	* i2c_read - Read from i2c memory
	231	* @chip: target i2c address
	232	* @addr: address to read from
	233	* @alen:
	234	* @buffer: buffer for read data
	235	* @len: no of bytes to be read
	236	*
	237	* Read from i2c memory.
	238	*/
3f4358da SR	239	static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
3f4358da SR	240	int alen, u8 *buffer, int len)
2403f8f4 VK	241	{
	242	unsigned long start_time_rx;
	243
32d041e2 AB	244	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	245	/*
	246	* EEPROM chips that implement "address overflow" are ones
	247	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	248	* address and the extra bits end up in the "chip address"
	249	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	250	* four 256 byte chips.
	251	*
	252	* Note that we consider the length of the address field to
	253	* still be one byte because the extra address bits are
	254	* hidden in the chip address.
	255	*/
678398b1	256	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	257	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	258
678398b1	259	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	260	addr);
	261	#endif
	262
3f4358da	263	if (i2c_xfer_init(i2c_base, dev, addr, alen))
2403f8f4 VK	264	return 1;
	265
	266	start_time_rx = get_timer(0);
	267	while (len) {
491739bb	268	if (len == 1)
678398b1	269	writel(IC_CMD \| IC_STOP, &i2c_base->ic_cmd_data);
491739bb	270	else
678398b1	271	writel(IC_CMD, &i2c_base->ic_cmd_data);
2403f8f4	272
678398b1 SR	273	if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
678398b1 SR	274	*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	275	len--;
	276	start_time_rx = get_timer(0);
	277
	278	} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
2403f8f4 VK	279	return 1;
	280	}
	281	}
	282
3f4358da	283	return i2c_xfer_finish(i2c_base);
2403f8f4 VK	284	}
	285
	286	/*
	287	* i2c_write - Write to i2c memory
	288	* @chip: target i2c address
	289	* @addr: address to read from
	290	* @alen:
	291	* @buffer: buffer for read data
	292	* @len: no of bytes to be read
	293	*
	294	* Write to i2c memory.
	295	*/
3f4358da SR	296	static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
3f4358da SR	297	int alen, u8 *buffer, int len)
2403f8f4 VK	298	{
	299	int nb = len;
	300	unsigned long start_time_tx;
	301
32d041e2 AB	302	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	303	/*
	304	* EEPROM chips that implement "address overflow" are ones
	305	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	306	* address and the extra bits end up in the "chip address"
	307	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	308	* four 256 byte chips.
	309	*
	310	* Note that we consider the length of the address field to
	311	* still be one byte because the extra address bits are
	312	* hidden in the chip address.
	313	*/
678398b1	314	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	315	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	316
678398b1	317	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	318	addr);
	319	#endif
	320
3f4358da	321	if (i2c_xfer_init(i2c_base, dev, addr, alen))
2403f8f4 VK	322	return 1;
	323
	324	start_time_tx = get_timer(0);
	325	while (len) {
678398b1 SR	326	if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
	327	if (--len == 0) {
	328	writel(*buffer \| IC_STOP,
	329	&i2c_base->ic_cmd_data);
	330	} else {
	331	writel(*buffer, &i2c_base->ic_cmd_data);
	332	}
2403f8f4	333	buffer++;
2403f8f4 VK	334	start_time_tx = get_timer(0);
	335
	336	} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
	337	printf("Timed out. i2c write Failed\n");
	338	return 1;
	339	}
	340	}
	341
3f4358da SR	342	return i2c_xfer_finish(i2c_base);
	343	}
	344
334b9b00 SR	345	/*
	346	* __dw_i2c_init - Init function
	347	* @speed: required i2c speed
	348	* @slaveaddr: slave address for the device
	349	*
	350	* Initialization function.
	351	*/
	352	static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
	353	{
	354	/* Disable i2c */
	355	dw_i2c_enable(i2c_base, false);
	356
	357	writel((IC_CON_SD \| IC_CON_SPD_FS \| IC_CON_MM), &i2c_base->ic_con);
	358	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	359	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	360	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	361	#ifndef CONFIG_DM_I2C
ba5da550	362	__dw_i2c_set_bus_speed(i2c_base, NULL, speed);
334b9b00 SR	363	writel(slaveaddr, &i2c_base->ic_sar);
	364	#endif
	365
	366	/* Enable i2c */
	367	dw_i2c_enable(i2c_base, true);
	368	}
	369
	370	#ifndef CONFIG_DM_I2C
	371	/*
	372	* The legacy I2C functions. These need to get removed once
	373	* all users of this driver are converted to DM.
	374	*/
3f4358da SR	375	static struct i2c_regs i2c_get_base(struct i2c_adapter adap)
	376	{
	377	switch (adap->hwadapnr) {
	378	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	379	case 3:
	380	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
	381	#endif
	382	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	383	case 2:
	384	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
	385	#endif
	386	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	387	case 1:
	388	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
	389	#endif
	390	case 0:
	391	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	392	default:
	393	printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	394	}
	395
	396	return NULL;
	397	}
	398
	399	static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
	400	unsigned int speed)
	401	{
	402	adap->speed = speed;
ba5da550	403	return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
3f4358da SR	404	}
3f4358da SR	405
334b9b00	406	static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
3f4358da	407	{
334b9b00	408	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
3f4358da SR	409	}
	410
	411	static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
	412	int alen, u8 *buffer, int len)
	413	{
	414	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
	415	}
	416
	417	static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
	418	int alen, u8 *buffer, int len)
	419	{
	420	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
2403f8f4 VK	421	}
2403f8f4 VK	422
334b9b00	423	/* dw_i2c_probe - Probe the i2c chip */
678398b1	424	static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
2403f8f4	425	{
3f4358da	426	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4	427	u32 tmp;
496ba48f	428	int ret;
2403f8f4 VK	429
	430	/*
	431	* Try to read the first location of the chip.
	432	*/
3f4358da	433	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
496ba48f	434	if (ret)
678398b1	435	dw_i2c_init(adap, adap->speed, adap->slaveaddr);
496ba48f SR	436
496ba48f SR	437	return ret;
2403f8f4	438	}
ac6e2fe6	439
678398b1 SR	440	U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	441	dw_i2c_write, dw_i2c_set_bus_speed,
	442	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
ac6e2fe6	443
678398b1 SR	444	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	445	U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	446	dw_i2c_write, dw_i2c_set_bus_speed,
	447	CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
	448	#endif
ac6e2fe6	449
678398b1 SR	450	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	451	U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	452	dw_i2c_write, dw_i2c_set_bus_speed,
	453	CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
	454	#endif
ac6e2fe6	455
678398b1 SR	456	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	457	U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	458	dw_i2c_write, dw_i2c_set_bus_speed,
	459	CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
ac6e2fe6	460	#endif
334b9b00 SR	461
	462	#else /* CONFIG_DM_I2C */
	463	/* The DM I2C functions */
	464
	465	static int designware_i2c_xfer(struct udevice bus, struct i2c_msg msg,
	466	int nmsgs)
	467	{
	468	struct dw_i2c *i2c = dev_get_priv(bus);
	469	int ret;
	470
	471	debug("i2c_xfer: %d messages\n", nmsgs);
	472	for (; nmsgs > 0; nmsgs--, msg++) {
	473	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	474	if (msg->flags & I2C_M_RD) {
	475	ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
	476	msg->buf, msg->len);
	477	} else {
	478	ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
	479	msg->buf, msg->len);
	480	}
	481	if (ret) {
	482	debug("i2c_write: error sending\n");
	483	return -EREMOTEIO;
	484	}
	485	}
	486
	487	return 0;
	488	}
	489
	490	static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	491	{
	492	struct dw_i2c *i2c = dev_get_priv(bus);
	493
ba5da550	494	return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
334b9b00 SR	495	}
	496
	497	static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
	498	uint chip_flags)
	499	{
	500	struct dw_i2c *i2c = dev_get_priv(bus);
	501	struct i2c_regs *i2c_base = i2c->regs;
	502	u32 tmp;
	503	int ret;
	504
	505	/* Try to read the first location of the chip */
	506	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
	507	if (ret)
	508	__dw_i2c_init(i2c_base, 0, 0);
	509
	510	return ret;
	511	}
	512
	513	static int designware_i2c_probe(struct udevice *bus)
	514	{
	515	struct dw_i2c *priv = dev_get_priv(bus);
	516
ba5da550 SR	517	if (device_is_on_pci_bus(bus)) {
	518	#ifdef CONFIG_DM_PCI
	519	/* Save base address from PCI BAR */
	520	priv->regs = (struct i2c_regs *)
	521	dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
	522	#ifdef CONFIG_X86
	523	/* Use BayTrail specific timing values */
	524	priv->scl_sda_cfg = &byt_config;
	525	#endif
	526	#endif
	527	} else {
	528	priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
	529	}
334b9b00 SR	530
	531	__dw_i2c_init(priv->regs, 0, 0);
	532
	533	return 0;
	534	}
	535
ba5da550 SR	536	static int designware_i2c_bind(struct udevice *dev)
	537	{
	538	static int num_cards;
	539	char name[20];
	540
	541	/* Create a unique device name for PCI type devices */
	542	if (device_is_on_pci_bus(dev)) {
	543	/*
	544	* ToDo:
	545	* Setting req_seq in the driver is probably not recommended.
	546	* But without a DT alias the number is not configured. And
	547	* using this driver is impossible for PCIe I2C devices.
	548	* This can be removed, once a better (correct) way for this
	549	* is found and implemented.
	550	*/
	551	dev->req_seq = num_cards;
	552	sprintf(name, "i2c_designware#%u", num_cards++);
	553	device_set_name(dev, name);
	554	}
	555
	556	return 0;
	557	}
	558
334b9b00 SR	559	static const struct dm_i2c_ops designware_i2c_ops = {
	560	.xfer = designware_i2c_xfer,
	561	.probe_chip = designware_i2c_probe_chip,
	562	.set_bus_speed = designware_i2c_set_bus_speed,
	563	};
	564
	565	static const struct udevice_id designware_i2c_ids[] = {
	566	{ .compatible = "snps,designware-i2c" },
	567	{ }
	568	};
	569
	570	U_BOOT_DRIVER(i2c_designware) = {
	571	.name = "i2c_designware",
	572	.id = UCLASS_I2C,
	573	.of_match = designware_i2c_ids,
ba5da550	574	.bind = designware_i2c_bind,
334b9b00 SR	575	.probe = designware_i2c_probe,
	576	.priv_auto_alloc_size = sizeof(struct dw_i2c),
	577	.ops = &designware_i2c_ops,
	578	};
	579
ba5da550 SR	580	#ifdef CONFIG_X86
	581	static struct pci_device_id designware_pci_supported[] = {
	582	/* Intel BayTrail has 7 I2C controller located on the PCI bus */
	583	{ PCI_VDEVICE(INTEL, 0x0f41) },
	584	{ PCI_VDEVICE(INTEL, 0x0f42) },
	585	{ PCI_VDEVICE(INTEL, 0x0f43) },
	586	{ PCI_VDEVICE(INTEL, 0x0f44) },
	587	{ PCI_VDEVICE(INTEL, 0x0f45) },
	588	{ PCI_VDEVICE(INTEL, 0x0f46) },
	589	{ PCI_VDEVICE(INTEL, 0x0f47) },
	590	{},
	591	};
	592
	593	U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
	594	#endif
	595
334b9b00	596	#endif /* CONFIG_DM_I2C */