[people/ms/u-boot.git] / drivers / i2c / fsl_i2c.c

/*
 * Copyright 2006,2009 Freescale Semiconductor, Inc.
 *
 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
 * Changes for multibus/multiadapter I2C support.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <i2c.h>		/* Functional interface */
#include <asm/io.h>
#include <asm/fsl_i2c.h>	/* HW definitions */

/* The maximum number of microseconds we will wait until another master has
 * released the bus.  If not defined in the board header file, then use a
 * generic value.
 */
#ifndef CONFIG_I2C_MBB_TIMEOUT
#define CONFIG_I2C_MBB_TIMEOUT	100000
#endif

/* The maximum number of microseconds we will wait for a read or write
 * operation to complete.  If not defined in the board header file, then use a
 * generic value.
 */
#ifndef CONFIG_I2C_TIMEOUT
#define CONFIG_I2C_TIMEOUT	10000
#endif

#define I2C_READ_BIT  1
#define I2C_WRITE_BIT 0

DECLARE_GLOBAL_DATA_PTR;

static const struct fsl_i2c *i2c_dev[2] = {
	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
#endif
};

/* I2C speed map for a DFSR value of 1 */

/*
 * Map I2C frequency dividers to FDR and DFSR values
 *
 * This structure is used to define the elements of a table that maps I2C
 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
 * Sampling Rate (DFSR) registers.
 *
 * The actual table should be defined in the board file, and it must be called
 * fsl_i2c_speed_map[].
 *
 * The last entry of the table must have a value of {-1, X}, where X is same
 * FDR/DFSR values as the second-to-last entry.  This guarantees that any
 * search through the array will always find a match.
 *
 * The values of the divider must be in increasing numerical order, i.e.
 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
 *
 * For this table, the values are based on a value of 1 for the DFSR
 * register.  See the application note AN2919 "Determining the I2C Frequency
 * Divider Ratio for SCL"
 *
 * ColdFire I2C frequency dividers for FDR values are different from
 * PowerPC. The protocol to use the I2C module is still the same.
 * A different table is defined and are based on MCF5xxx user manual.
 *
 */
static const struct {
	unsigned short divider;
	u8 fdr;
} fsl_i2c_speed_map[] = {
#ifdef __M68K__
	{20, 32}, {22, 33}, {24, 34}, {26, 35},
	{28, 0}, {28, 36}, {30, 1}, {32, 37},
	{34, 2}, {36, 38}, {40, 3}, {40, 39},
	{44, 4}, {48, 5}, {48, 40}, {56, 6},
	{56, 41}, {64, 42}, {68, 7}, {72, 43},
	{80, 8}, {80, 44}, {88, 9}, {96, 41},
	{104, 10}, {112, 42}, {128, 11}, {128, 43},
	{144, 12}, {160, 13}, {160, 48}, {192, 14},
	{192, 49}, {224, 50}, {240, 15}, {256, 51},
	{288, 16}, {320, 17}, {320, 52}, {384, 18},
	{384, 53}, {448, 54}, {480, 19}, {512, 55},
	{576, 20}, {640, 21}, {640, 56}, {768, 22},
	{768, 57}, {960, 23}, {896, 58}, {1024, 59},
	{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
	{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
	{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
	{-1, 31}
#endif
};

/**
 * Set the I2C bus speed for a given I2C device
 *
 * @param dev: the I2C device
 * @i2c_clk: I2C bus clock frequency
 * @speed: the desired speed of the bus
 *
 * The I2C device must be stopped before calling this function.
 *
 * The return value is the actual bus speed that is set.
 */
static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
	unsigned int i2c_clk, unsigned int speed)
{
	unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);

	/*
	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
	 * is equal to or lower than the requested speed.  That means that we
	 * want the first divider that is equal to or greater than the
	 * calculated divider.
	 */
#ifdef __PPC__
	u8 dfsr, fdr = 0x31; /* Default if no FDR found */
	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
	unsigned short a, b, ga, gb;
	unsigned long c_div, est_div;

#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
	dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
#else
	/* Condition 1: dfsr <= 50/T */
	dfsr = (5 * (i2c_clk / 1000)) / 100000;
#endif
#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
	fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
	speed = i2c_clk / divider; /* Fake something */
#else
	debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
	if (!dfsr)
		dfsr = 1;

	est_div = ~0;
	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
		for (gb = 0; gb < 8; gb++) {
			b = 16 << gb;
			c_div = b * (a + ((3*dfsr)/b)*2);
			if ((c_div > divider) && (c_div < est_div)) {
				unsigned short bin_gb, bin_ga;

				est_div = c_div;
				bin_gb = gb << 2;
				bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
				fdr = bin_gb | bin_ga;
				speed = i2c_clk / est_div;
				debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
				      "a:%d, b:%d, speed:%d\n",
				      fdr, est_div, ga, gb, a, b, speed);
				/* Condition 2 not accounted for */
				debug("Tr <= %d ns\n",
				      (b - 3 * dfsr) * 1000000 /
				      (i2c_clk / 1000));
			}
		}
		if (a == 20)
			a += 2;
		if (a == 24)
			a += 4;
	}
	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
#endif
	writeb(dfsr, &dev->dfsrr);	/* set default filter */
	writeb(fdr, &dev->fdr);		/* set bus speed */
#else
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
		if (fsl_i2c_speed_map[i].divider >= divider) {
			u8 fdr;

			fdr = fsl_i2c_speed_map[i].fdr;
			speed = i2c_clk / fsl_i2c_speed_map[i].divider;
			writeb(fdr, &dev->fdr);		/* set bus speed */

			break;
		}
#endif
	return speed;
}

static unsigned int get_i2c_clock(int bus)
{
	if (bus)
		return gd->arch.i2c2_clk;	/* I2C2 clock */
	else
		return gd->arch.i2c1_clk;	/* I2C1 clock */
}

static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
	const struct fsl_i2c *dev;

#ifdef CONFIG_SYS_I2C_INIT_BOARD
	/* Call board specific i2c bus reset routine before accessing the
	 * environment, which might be in a chip on that bus. For details
	 * about this problem see doc/I2C_Edge_Conditions.
	*/
	i2c_init_board();
#endif
	dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

	writeb(0, &dev->cr);		/* stop I2C controller */
	udelay(5);			/* let it shutdown in peace */
	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
	writeb(slaveadd << 1, &dev->adr);/* write slave address */
	writeb(0x0, &dev->sr);		/* clear status register */
	writeb(I2C_CR_MEN, &dev->cr);	/* start I2C controller */

#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
	/* Call board specific i2c bus reset routine AFTER the bus has been
	 * initialized. Use either this callpoint or i2c_init_board;
	 * which is called before i2c_init operations.
	 * For details about this problem see doc/I2C_Edge_Conditions.
	*/
	i2c_board_late_init();
#endif
}

static int
i2c_wait4bus(struct i2c_adapter *adap)
{
	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
	unsigned long long timeval = get_ticks();
	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

	while (readb(&dev->sr) & I2C_SR_MBB) {
		if ((get_ticks() - timeval) > timeout)
			return -1;
	}

	return 0;
}

static __inline__ int
i2c_wait(struct i2c_adapter *adap, int write)
{
	u32 csr;
	unsigned long long timeval = get_ticks();
	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

	do {
		csr = readb(&dev->sr);
		if (!(csr & I2C_SR_MIF))
			continue;
		/* Read again to allow register to stabilise */
		csr = readb(&dev->sr);

		writeb(0x0, &dev->sr);

		if (csr & I2C_SR_MAL) {
			debug("i2c_wait: MAL\n");
			return -1;
		}

		if (!(csr & I2C_SR_MCF))	{
			debug("i2c_wait: unfinished\n");
			return -1;
		}

		if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
			debug("i2c_wait: No RXACK\n");
			return -1;
		}

		return 0;
	} while ((get_ticks() - timeval) < timeout);

	debug("i2c_wait: timed out\n");
	return -1;
}

static __inline__ int
i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
{
	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
	       | (rsta ? I2C_CR_RSTA : 0),
	       &device->cr);

	writeb((dev << 1) | dir, &device->dr);

	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
		return 0;

	return 1;
}

static __inline__ int
__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
{
	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
	int i;

	for (i = 0; i < length; i++) {
		writeb(data[i], &dev->dr);

		if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
			break;
	}

	return i;
}

static __inline__ int
__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
{
	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
	int i;

	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
	       &dev->cr);

	/* dummy read */
	readb(&dev->dr);

	for (i = 0; i < length; i++) {
		if (i2c_wait(adap, I2C_READ_BIT) < 0)
			break;

		/* Generate ack on last next to last byte */
		if (i == length - 2)
			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
			       &dev->cr);

		/* Do not generate stop on last byte */
		if (i == length - 1)
			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
			       &dev->cr);

		data[i] = readb(&dev->dr);
	}

	return i;
}

static int
fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
	     int length)
{
	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
	int i = -1; /* signal error */
	u8 *a = (u8*)&addr;

	if (i2c_wait4bus(adap) < 0)
		return -1;

	if ((!length || alen > 0)
	    && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
	    && __i2c_write(adap, &a[4 - alen], alen) == alen)
		i = 0; /* No error so far */

	if (length &&
	    i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
		i = __i2c_read(adap, data, length);

	writeb(I2C_CR_MEN, &device->cr);

	if (i2c_wait4bus(adap)) /* Wait until STOP */
		debug("i2c_read: wait4bus timed out\n");

	if (i == length)
	    return 0;

	return -1;
}

static int
fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
	      u8 *data, int length)
{
	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
	int i = -1; /* signal error */
	u8 *a = (u8*)&addr;

	if (i2c_wait4bus(adap) >= 0 &&
	    i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
	    __i2c_write(adap, &a[4 - alen], alen) == alen) {
		i = __i2c_write(adap, data, length);
	}

	writeb(I2C_CR_MEN, &device->cr);
	if (i2c_wait4bus(adap)) /* Wait until STOP */
		debug("i2c_write: wait4bus timed out\n");

	if (i == length)
	    return 0;

	return -1;
}

static int
fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
	/* For unknow reason the controller will ACK when
	 * probing for a slave with the same address, so skip
	 * it.
	 */
	if (chip == (readb(&dev->adr) >> 1))
		return -1;

	return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
}

static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
			unsigned int speed)
{
	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

	writeb(0, &dev->cr);		/* stop controller */
	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
	writeb(I2C_CR_MEN, &dev->cr);	/* start controller */

	return 0;
}

/*
 * Register fsl i2c adapters
 */
U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
			 fsl_i2c_write, fsl_i2c_set_bus_speed,
			 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
			 0)
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
			 fsl_i2c_write, fsl_i2c_set_bus_speed,
			 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
			 1)
#endif
Commit	Line	Data
debb7354	1	/*
92477a63	2	* Copyright 2006,2009 Freescale Semiconductor, Inc.
debb7354	3	*
00f792e0 HS	4	* 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
	5	* Changes for multibus/multiadapter I2C support.
	6	*
debb7354	7	* This program is free software; you can redistribute it and/or
7237c033 JL	8	* modify it under the terms of the GNU General Public License
7237c033 JL	9	* Version 2 as published by the Free Software Foundation.
debb7354 JL	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <common.h>
4d45f69e	23	#include <command.h>
20476726	24	#include <i2c.h> /* Functional interface */
7237c033	25	#include <asm/io.h>
20476726	26	#include <asm/fsl_i2c.h> /* HW definitions */
debb7354	27
92477a63 TT	28	/* The maximum number of microseconds we will wait until another master has
	29	* released the bus. If not defined in the board header file, then use a
	30	* generic value.
	31	*/
	32	#ifndef CONFIG_I2C_MBB_TIMEOUT
	33	#define CONFIG_I2C_MBB_TIMEOUT 100000
	34	#endif
	35
	36	/* The maximum number of microseconds we will wait for a read or write
	37	* operation to complete. If not defined in the board header file, then use a
	38	* generic value.
	39	*/
	40	#ifndef CONFIG_I2C_TIMEOUT
	41	#define CONFIG_I2C_TIMEOUT 10000
	42	#endif
debb7354	43
1939d969 JT	44	#define I2C_READ_BIT 1
	45	#define I2C_WRITE_BIT 0
	46
d8c82db4 TT	47	DECLARE_GLOBAL_DATA_PTR;
d8c82db4 TT	48
d8c82db4	49	static const struct fsl_i2c *i2c_dev[2] = {
00f792e0 HS	50	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
	51	#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
	52	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
be5e6181 TT	53	#endif
be5e6181 TT	54	};
debb7354	55
d8c82db4 TT	56	/* I2C speed map for a DFSR value of 1 */
	57
	58	/*
	59	* Map I2C frequency dividers to FDR and DFSR values
	60	*
	61	* This structure is used to define the elements of a table that maps I2C
	62	* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
	63	* programmed into the Frequency Divider Ratio (FDR) and Digital Filter
	64	* Sampling Rate (DFSR) registers.
	65	*
	66	* The actual table should be defined in the board file, and it must be called
	67	* fsl_i2c_speed_map[].
	68	*
	69	* The last entry of the table must have a value of {-1, X}, where X is same
	70	* FDR/DFSR values as the second-to-last entry. This guarantees that any
	71	* search through the array will always find a match.
	72	*
	73	* The values of the divider must be in increasing numerical order, i.e.
	74	* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
	75	*
	76	* For this table, the values are based on a value of 1 for the DFSR
	77	* register. See the application note AN2919 "Determining the I2C Frequency
	78	* Divider Ratio for SCL"
5d9a5efa TL	79	*
	80	* ColdFire I2C frequency dividers for FDR values are different from
	81	* PowerPC. The protocol to use the I2C module is still the same.
	82	* A different table is defined and are based on MCF5xxx user manual.
	83	*
d8c82db4 TT	84	*/
	85	static const struct {
	86	unsigned short divider;
d8c82db4 TT	87	u8 fdr;
d8c82db4 TT	88	} fsl_i2c_speed_map[] = {
99404202	89	#ifdef __M68K__
5d9a5efa TL	90	{20, 32}, {22, 33}, {24, 34}, {26, 35},
	91	{28, 0}, {28, 36}, {30, 1}, {32, 37},
	92	{34, 2}, {36, 38}, {40, 3}, {40, 39},
	93	{44, 4}, {48, 5}, {48, 40}, {56, 6},
	94	{56, 41}, {64, 42}, {68, 7}, {72, 43},
	95	{80, 8}, {80, 44}, {88, 9}, {96, 41},
	96	{104, 10}, {112, 42}, {128, 11}, {128, 43},
	97	{144, 12}, {160, 13}, {160, 48}, {192, 14},
	98	{192, 49}, {224, 50}, {240, 15}, {256, 51},
	99	{288, 16}, {320, 17}, {320, 52}, {384, 18},
	100	{384, 53}, {448, 54}, {480, 19}, {512, 55},
	101	{576, 20}, {640, 21}, {640, 56}, {768, 22},
	102	{768, 57}, {960, 23}, {896, 58}, {1024, 59},
	103	{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
	104	{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
	105	{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
	106	{-1, 31}
	107	#endif
d8c82db4 TT	108	};
	109
	110	/**
	111	* Set the I2C bus speed for a given I2C device
	112	*
	113	* @param dev: the I2C device
	114	* @i2c_clk: I2C bus clock frequency
	115	* @speed: the desired speed of the bus
	116	*
	117	* The I2C device must be stopped before calling this function.
	118	*
	119	* The return value is the actual bus speed that is set.
	120	*/
	121	static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
	122	unsigned int i2c_clk, unsigned int speed)
	123	{
	124	unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
d8c82db4 TT	125
	126	/*
	127	* We want to choose an FDR/DFSR that generates an I2C bus speed that
	128	* is equal to or lower than the requested speed. That means that we
	129	* want the first divider that is equal to or greater than the
	130	* calculated divider.
	131	*/
5d9a5efa	132	#ifdef __PPC__
99404202 JT	133	u8 dfsr, fdr = 0x31; /* Default if no FDR found */
	134	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
	135	unsigned short a, b, ga, gb;
	136	unsigned long c_div, est_div;
	137
d01ee4db	138	#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
99404202	139	dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
d01ee4db	140	#else
99404202 JT	141	/* Condition 1: dfsr <= 50/T */
99404202 JT	142	dfsr = (5 * (i2c_clk / 1000)) / 100000;
d01ee4db JT	143	#endif
d01ee4db JT	144	#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
99404202 JT	145	fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
	146	speed = i2c_clk / divider; /* Fake something */
	147	#else
	148	debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
	149	if (!dfsr)
	150	dfsr = 1;
	151
	152	est_div = ~0;
	153	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
	154	for (gb = 0; gb < 8; gb++) {
	155	b = 16 << gb;
	156	c_div = b * (a + ((3dfsr)/b)2);
	157	if ((c_div > divider) && (c_div < est_div)) {
	158	unsigned short bin_gb, bin_ga;
	159
	160	est_div = c_div;
	161	bin_gb = gb << 2;
	162	bin_ga = (ga & 0x3) \| ((ga & 0x4) << 3);
	163	fdr = bin_gb \| bin_ga;
	164	speed = i2c_clk / est_div;
	165	debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
	166	"a:%d, b:%d, speed:%d\n",
	167	fdr, est_div, ga, gb, a, b, speed);
	168	/* Condition 2 not accounted for */
	169	debug("Tr <= %d ns\n",
	170	(b - 3 * dfsr) * 1000000 /
	171	(i2c_clk / 1000));
	172	}
	173	}
	174	if (a == 20)
	175	a += 2;
	176	if (a == 24)
	177	a += 4;
	178	}
	179	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
	180	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
	181	#endif
	182	writeb(dfsr, &dev->dfsrr); /* set default filter */
	183	writeb(fdr, &dev->fdr); /* set bus speed */
d01ee4db	184	#else
99404202 JT	185	unsigned int i;
	186
	187	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
	188	if (fsl_i2c_speed_map[i].divider >= divider) {
	189	u8 fdr;
	190
d8c82db4 TT	191	fdr = fsl_i2c_speed_map[i].fdr;
d8c82db4 TT	192	speed = i2c_clk / fsl_i2c_speed_map[i].divider;
d01ee4db JT	193	writeb(fdr, &dev->fdr); /* set bus speed */
d01ee4db JT	194
d8c82db4 TT	195	break;
d8c82db4 TT	196	}
99404202	197	#endif
d8c82db4 TT	198	return speed;
	199	}
	200
62f730ff	201	static unsigned int get_i2c_clock(int bus)
c9a8b25e JH	202	{
c9a8b25e JH	203	if (bus)
609e6ec3	204	return gd->arch.i2c2_clk; /* I2C2 clock */
c9a8b25e	205	else
609e6ec3	206	return gd->arch.i2c1_clk; /* I2C1 clock */
c9a8b25e JH	207	}
c9a8b25e JH	208
00f792e0	209	static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
debb7354	210	{
aa551215	211	const struct fsl_i2c *dev;
be5e6181	212
39df00d9	213	#ifdef CONFIG_SYS_I2C_INIT_BOARD
26a33504 RR	214	/* Call board specific i2c bus reset routine before accessing the
	215	* environment, which might be in a chip on that bus. For details
	216	* about this problem see doc/I2C_Edge_Conditions.
	217	*/
39df00d9 HS	218	i2c_init_board();
39df00d9 HS	219	#endif
00f792e0 HS	220	dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
	221
	222	writeb(0, &dev->cr); /* stop I2C controller */
	223	udelay(5); /* let it shutdown in peace */
	224	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
	225	writeb(slaveadd << 1, &dev->adr);/* write slave address */
	226	writeb(0x0, &dev->sr); /* clear status register */
	227	writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
26a33504 RR	228
	229	#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
	230	/* Call board specific i2c bus reset routine AFTER the bus has been
	231	* initialized. Use either this callpoint or i2c_init_board;
	232	* which is called before i2c_init operations.
	233	* For details about this problem see doc/I2C_Edge_Conditions.
	234	*/
	235	i2c_board_late_init();
	236	#endif
debb7354 JL	237	}
debb7354 JL	238
21f4cbb7	239	static int
00f792e0	240	i2c_wait4bus(struct i2c_adapter *adap)
debb7354	241	{
00f792e0	242	struct fsl_i2c dev = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
f2302d44	243	unsigned long long timeval = get_ticks();
92477a63	244	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
debb7354	245
00f792e0	246	while (readb(&dev->sr) & I2C_SR_MBB) {
92477a63	247	if ((get_ticks() - timeval) > timeout)
debb7354	248	return -1;
debb7354 JL	249	}
debb7354 JL	250
5c9efb36	251	return 0;
debb7354 JL	252	}
	253
	254	static __inline__ int
00f792e0	255	i2c_wait(struct i2c_adapter *adap, int write)
debb7354 JL	256	{
debb7354 JL	257	u32 csr;
f2302d44	258	unsigned long long timeval = get_ticks();
92477a63	259	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
00f792e0	260	struct fsl_i2c dev = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
debb7354 JL	261
debb7354 JL	262	do {
00f792e0	263	csr = readb(&dev->sr);
7237c033	264	if (!(csr & I2C_SR_MIF))
debb7354	265	continue;
21f4cbb7	266	/* Read again to allow register to stabilise */
00f792e0	267	csr = readb(&dev->sr);
debb7354	268
00f792e0	269	writeb(0x0, &dev->sr);
debb7354	270
7237c033	271	if (csr & I2C_SR_MAL) {
debb7354 JL	272	debug("i2c_wait: MAL\n");
	273	return -1;
	274	}
	275
7237c033	276	if (!(csr & I2C_SR_MCF)) {
debb7354 JL	277	debug("i2c_wait: unfinished\n");
	278	return -1;
	279	}
	280
1939d969	281	if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
debb7354 JL	282	debug("i2c_wait: No RXACK\n");
	283	return -1;
	284	}
	285
	286	return 0;
92477a63	287	} while ((get_ticks() - timeval) < timeout);
debb7354 JL	288
	289	debug("i2c_wait: timed out\n");
	290	return -1;
	291	}
	292
	293	static __inline__ int
00f792e0	294	i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
debb7354	295	{
00f792e0 HS	296	struct fsl_i2c device = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
00f792e0 HS	297
7237c033 JL	298	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_MTX
7237c033 JL	299	\| (rsta ? I2C_CR_RSTA : 0),
00f792e0	300	&device->cr);
debb7354	301
00f792e0	302	writeb((dev << 1) \| dir, &device->dr);
debb7354	303
00f792e0	304	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
debb7354 JL	305	return 0;
	306
	307	return 1;
	308	}
	309
	310	static __inline__ int
00f792e0	311	__i2c_write(struct i2c_adapter adap, u8 data, int length)
debb7354	312	{
00f792e0	313	struct fsl_i2c dev = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
debb7354	314	int i;
5c9efb36	315
5c9efb36	316	for (i = 0; i < length; i++) {
00f792e0	317	writeb(data[i], &dev->dr);
debb7354	318
00f792e0	319	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
debb7354 JL	320	break;
	321	}
	322
	323	return i;
	324	}
	325
	326	static __inline__ int
00f792e0	327	__i2c_read(struct i2c_adapter adap, u8 data, int length)
debb7354	328	{
00f792e0	329	struct fsl_i2c dev = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
debb7354 JL	330	int i;
debb7354 JL	331
7237c033	332	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| ((length == 1) ? I2C_CR_TXAK : 0),
00f792e0	333	&dev->cr);
debb7354 JL	334
debb7354 JL	335	/* dummy read */
00f792e0	336	readb(&dev->dr);
debb7354	337
5c9efb36	338	for (i = 0; i < length; i++) {
00f792e0	339	if (i2c_wait(adap, I2C_READ_BIT) < 0)
debb7354 JL	340	break;
	341
	342	/* Generate ack on last next to last byte */
	343	if (i == length - 2)
7237c033	344	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_TXAK,
00f792e0	345	&dev->cr);
debb7354	346
d1c9e5b3	347	/* Do not generate stop on last byte */
debb7354	348	if (i == length - 1)
d1c9e5b3	349	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_MTX,
00f792e0	350	&dev->cr);
debb7354	351
00f792e0	352	data[i] = readb(&dev->dr);
debb7354	353	}
5c9efb36	354
debb7354 JL	355	return i;
	356	}
	357
00f792e0 HS	358	static int
	359	fsl_i2c_read(struct i2c_adapter adap, u8 dev, uint addr, int alen, u8 data,
	360	int length)
debb7354	361	{
00f792e0	362	struct fsl_i2c device = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
f6f5f709	363	int i = -1; /* signal error */
7237c033	364	u8 a = (u8)&addr;
debb7354	365
00f792e0	366	if (i2c_wait4bus(adap) < 0)
b778c1b5 RP	367	return -1;
	368
	369	if ((!length \|\| alen > 0)
00f792e0 HS	370	&& i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
00f792e0 HS	371	&& __i2c_write(adap, &a[4 - alen], alen) == alen)
f6f5f709 JT	372	i = 0; /* No error so far */
f6f5f709 JT	373
b778c1b5	374	if (length &&
00f792e0 HS	375	i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
00f792e0 HS	376	i = __i2c_read(adap, data, length);
debb7354	377
00f792e0	378	writeb(I2C_CR_MEN, &device->cr);
debb7354	379
00f792e0	380	if (i2c_wait4bus(adap)) /* Wait until STOP */
d1c9e5b3 JT	381	debug("i2c_read: wait4bus timed out\n");
d1c9e5b3 JT	382
4d45f69e JL	383	if (i == length)
	384	return 0;
	385
	386	return -1;
debb7354 JL	387	}
debb7354 JL	388
00f792e0 HS	389	static int
	390	fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
	391	u8 *data, int length)
debb7354	392	{
00f792e0	393	struct fsl_i2c device = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
f6f5f709	394	int i = -1; /* signal error */
7237c033	395	u8 a = (u8)&addr;
debb7354	396
00f792e0 HS	397	if (i2c_wait4bus(adap) >= 0 &&
	398	i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
	399	__i2c_write(adap, &a[4 - alen], alen) == alen) {
	400	i = __i2c_write(adap, data, length);
4d45f69e	401	}
debb7354	402
00f792e0 HS	403	writeb(I2C_CR_MEN, &device->cr);
00f792e0 HS	404	if (i2c_wait4bus(adap)) /* Wait until STOP */
21f4cbb7	405	debug("i2c_write: wait4bus timed out\n");
debb7354	406
4d45f69e JL	407	if (i == length)
	408	return 0;
	409
	410	return -1;
debb7354 JL	411	}
debb7354 JL	412
00f792e0 HS	413	static int
00f792e0 HS	414	fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
debb7354	415	{
00f792e0	416	struct fsl_i2c dev = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
f6f5f709 JT	417	/* For unknow reason the controller will ACK when
	418	* probing for a slave with the same address, so skip
	419	* it.
debb7354	420	*/
00f792e0	421	if (chip == (readb(&dev->adr) >> 1))
be5e6181	422	return -1;
be5e6181	423
00f792e0	424	return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
be5e6181 TT	425	}
be5e6181 TT	426
00f792e0 HS	427	static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
00f792e0 HS	428	unsigned int speed)
be5e6181	429	{
00f792e0	430	struct fsl_i2c dev = (struct fsl_i2c )i2c_dev[adap->hwadapnr];
d8c82db4	431
00f792e0 HS	432	writeb(0, &dev->cr); /* stop controller */
	433	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
	434	writeb(I2C_CR_MEN, &dev->cr); /* start controller */
d8c82db4 TT	435
d8c82db4 TT	436	return 0;
be5e6181 TT	437	}
be5e6181 TT	438
00f792e0 HS	439	/*
	440	* Register fsl i2c adapters
	441	*/
	442	U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
	443	fsl_i2c_write, fsl_i2c_set_bus_speed,
	444	CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
	445	0)
	446	#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
	447	U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
	448	fsl_i2c_write, fsl_i2c_set_bus_speed,
	449	CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
	450	1)
c1bce4ff	451	#endif