[people/ms/u-boot.git] / drivers / i2c / fsl_i2c.c

/*
 * Copyright 2006 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_HARD_I2C

#include <command.h>
#include <i2c.h>		/* Functional interface */

#include <asm/io.h>
#include <asm/fsl_i2c.h>	/* HW definitions */

#define I2C_TIMEOUT	(CFG_HZ / 4)

#define I2C_READ_BIT  1
#define I2C_WRITE_BIT 0

DECLARE_GLOBAL_DATA_PTR;

/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
 * Default is bus 0.  This is necessary because the DDR initialization
 * runs from ROM, and we can't switch buses because we can't modify
 * the global variables.
 */
#ifdef CFG_SPD_BUS_NUM
static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
#else
static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
#endif

static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED};

static const struct fsl_i2c *i2c_dev[2] = {
	(struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
#ifdef CFG_I2C2_OFFSET
	(struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
#endif
};

/* I2C speed map for a DFSR value of 1 */

/*
 * Map I2C frequency dividers to FDR and DFSR values
 *
 * This structure is used to define the elements of a table that maps I2C
 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
 * Sampling Rate (DFSR) registers.
 *
 * The actual table should be defined in the board file, and it must be called
 * fsl_i2c_speed_map[].
 *
 * The last entry of the table must have a value of {-1, X}, where X is same
 * FDR/DFSR values as the second-to-last entry.  This guarantees that any
 * search through the array will always find a match.
 *
 * The values of the divider must be in increasing numerical order, i.e.
 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
 *
 * For this table, the values are based on a value of 1 for the DFSR
 * register.  See the application note AN2919 "Determining the I2C Frequency
 * Divider Ratio for SCL"
 */
static const struct {
	unsigned short divider;
	u8 dfsr;
	u8 fdr;
} fsl_i2c_speed_map[] = {
	{160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35},
	{288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2},
	{448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4},
	{608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3},
	{768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7},
	{1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9},
	{1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46},
	{1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12},
	{2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14},
	{3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16},
	{5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19},
	{8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22},
	{14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24},
	{20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27},
	{32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30},
	{61440, 1, 31}, {-1, 1, 31}
};

/**
 * Set the I2C bus speed for a given I2C device
 *
 * @param dev: the I2C device
 * @i2c_clk: I2C bus clock frequency
 * @speed: the desired speed of the bus
 *
 * The I2C device must be stopped before calling this function.
 *
 * The return value is the actual bus speed that is set.
 */
static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
	unsigned int i2c_clk, unsigned int speed)
{
	unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
	unsigned int i;

	/*
	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
	 * is equal to or lower than the requested speed.  That means that we
	 * want the first divider that is equal to or greater than the
	 * calculated divider.
	 */

	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
		if (fsl_i2c_speed_map[i].divider >= divider) {
			u8 fdr, dfsr;
			dfsr = fsl_i2c_speed_map[i].dfsr;
			fdr = fsl_i2c_speed_map[i].fdr;
			speed = i2c_clk / fsl_i2c_speed_map[i].divider;
			writeb(fdr, &dev->fdr);		/* set bus speed */
			writeb(dfsr, &dev->dfsrr);	/* set default filter */
			break;
		}

	return speed;
}

void
i2c_init(int speed, int slaveadd)
{
	struct fsl_i2c *dev;
	unsigned int temp;

	dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);

	writeb(0, &dev->cr);			/* stop I2C controller */
	udelay(5);				/* let it shutdown in peace */
	temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
	if (gd->flags & GD_FLG_RELOC)
		i2c_bus_speed[0] = temp;
	writeb(slaveadd << 1, &dev->adr);	/* write slave address */
	writeb(0x0, &dev->sr);			/* clear status register */
	writeb(I2C_CR_MEN, &dev->cr);		/* start I2C controller */

#ifdef	CFG_I2C2_OFFSET
	dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);

	writeb(0, &dev->cr);			/* stop I2C controller */
	udelay(5);				/* let it shutdown in peace */
	temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
	if (gd->flags & GD_FLG_RELOC)
		i2c_bus_speed[1] = temp;
	writeb(slaveadd << 1, &dev->adr);	/* write slave address */
	writeb(0x0, &dev->sr);			/* clear status register */
	writeb(I2C_CR_MEN, &dev->cr);		/* start I2C controller */
#endif
}

static __inline__ int
i2c_wait4bus(void)
{
	unsigned long long timeval = get_ticks();

	while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
		if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT))
			return -1;
	}

	return 0;
}

static __inline__ int
i2c_wait(int write)
{
	u32 csr;
	unsigned long long timeval = get_ticks();

	do {
		csr = readb(&i2c_dev[i2c_bus_num]->sr);
		if (!(csr & I2C_SR_MIF))
			continue;

		writeb(0x0, &i2c_dev[i2c_bus_num]->sr);

		if (csr & I2C_SR_MAL) {
			debug("i2c_wait: MAL\n");
			return -1;
		}

		if (!(csr & I2C_SR_MCF))	{
			debug("i2c_wait: unfinished\n");
			return -1;
		}

		if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
			debug("i2c_wait: No RXACK\n");
			return -1;
		}

		return 0;
	} while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT));

	debug("i2c_wait: timed out\n");
	return -1;
}

static __inline__ int
i2c_write_addr (u8 dev, u8 dir, int rsta)
{
	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
	       | (rsta ? I2C_CR_RSTA : 0),
	       &i2c_dev[i2c_bus_num]->cr);

	writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);

	if (i2c_wait(I2C_WRITE_BIT) < 0)
		return 0;

	return 1;
}

static __inline__ int
__i2c_write(u8 *data, int length)
{
	int i;

	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
	       &i2c_dev[i2c_bus_num]->cr);

	for (i = 0; i < length; i++) {
		writeb(data[i], &i2c_dev[i2c_bus_num]->dr);

		if (i2c_wait(I2C_WRITE_BIT) < 0)
			break;
	}

	return i;
}

static __inline__ int
__i2c_read(u8 *data, int length)
{
	int i;

	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
	       &i2c_dev[i2c_bus_num]->cr);

	/* dummy read */
	readb(&i2c_dev[i2c_bus_num]->dr);

	for (i = 0; i < length; i++) {
		if (i2c_wait(I2C_READ_BIT) < 0)
			break;

		/* Generate ack on last next to last byte */
		if (i == length - 2)
			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
			       &i2c_dev[i2c_bus_num]->cr);

		/* Generate stop on last byte */
		if (i == length - 1)
			writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);

		data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
	}

	return i;
}

int
i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
{
	int i = -1; /* signal error */
	u8 *a = (u8*)&addr;

	if (i2c_wait4bus() >= 0
	    && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
	    && __i2c_write(&a[4 - alen], alen) == alen)
		i = 0; /* No error so far */

	if (length
	    && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
		i = __i2c_read(data, length);

	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);

	if (i == length)
	    return 0;

	return -1;
}

int
i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
{
	int i = -1; /* signal error */
	u8 *a = (u8*)&addr;

	if (i2c_wait4bus() >= 0
	    && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
	    && __i2c_write(&a[4 - alen], alen) == alen) {
		i = __i2c_write(data, length);
	}

	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);

	if (i == length)
	    return 0;

	return -1;
}

int
i2c_probe(uchar chip)
{
	/* For unknow reason the controller will ACK when
	 * probing for a slave with the same address, so skip
	 * it.
	 */
	if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
		return -1;

	return i2c_read(chip, 0, 0, NULL, 0);
}

uchar
i2c_reg_read(uchar i2c_addr, uchar reg)
{
	uchar buf[1];

	i2c_read(i2c_addr, reg, 1, buf, 1);

	return buf[0];
}

void
i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
	i2c_write(i2c_addr, reg, 1, &val, 1);
}

int i2c_set_bus_num(unsigned int bus)
{
#ifdef CFG_I2C2_OFFSET
	if (bus > 1) {
#else
	if (bus > 0) {
#endif
		return -1;
	}

	i2c_bus_num = bus;

	return 0;
}

int i2c_set_bus_speed(unsigned int speed)
{
	unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;

	writeb(0, &i2c_dev[i2c_bus_num]->cr);		/* stop controller */
	i2c_bus_speed[i2c_bus_num] =
		set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);	/* start controller */

	return 0;
}

unsigned int i2c_get_bus_num(void)
{
	return i2c_bus_num;
}

unsigned int i2c_get_bus_speed(void)
{
	return i2c_bus_speed[i2c_bus_num];
}

#endif /* CONFIG_HARD_I2C */
#endif /* CONFIG_FSL_I2C */
Commit	Line	Data
debb7354	1	/*
7237c033	2	* Copyright 2006 Freescale Semiconductor, Inc.
debb7354 JL	3	*
debb7354 JL	4	* This program is free software; you can redistribute it and/or
7237c033 JL	5	* modify it under the terms of the GNU General Public License
7237c033 JL	6	* Version 2 as published by the Free Software Foundation.
debb7354 JL	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	16	* MA 02111-1307 USA
	17	*/
	18
	19	#include <common.h>
debb7354	20
20476726	21	#ifdef CONFIG_FSL_I2C
debb7354	22	#ifdef CONFIG_HARD_I2C
debb7354	23
4d45f69e	24	#include <command.h>
20476726 JL	25	#include <i2c.h> /* Functional interface */
20476726 JL	26
7237c033	27	#include <asm/io.h>
20476726	28	#include <asm/fsl_i2c.h> /* HW definitions */
debb7354	29
7237c033	30	#define I2C_TIMEOUT (CFG_HZ / 4)
debb7354	31
1939d969 JT	32	#define I2C_READ_BIT 1
	33	#define I2C_WRITE_BIT 0
	34
d8c82db4 TT	35	DECLARE_GLOBAL_DATA_PTR;
d8c82db4 TT	36
be5e6181 TT	37	/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
	38	* Default is bus 0. This is necessary because the DDR initialization
	39	* runs from ROM, and we can't switch buses because we can't modify
	40	* the global variables.
	41	*/
	42	#ifdef CFG_SPD_BUS_NUM
	43	static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
	44	#else
	45	static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
	46	#endif
	47
d8c82db4 TT	48	static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED};
	49
	50	static const struct fsl_i2c *i2c_dev[2] = {
be5e6181 TT	51	(struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
	52	#ifdef CFG_I2C2_OFFSET
	53	(struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
	54	#endif
	55	};
debb7354	56
d8c82db4 TT	57	/* I2C speed map for a DFSR value of 1 */
	58
	59	/*
	60	* Map I2C frequency dividers to FDR and DFSR values
	61	*
	62	* This structure is used to define the elements of a table that maps I2C
	63	* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
	64	* programmed into the Frequency Divider Ratio (FDR) and Digital Filter
	65	* Sampling Rate (DFSR) registers.
	66	*
	67	* The actual table should be defined in the board file, and it must be called
	68	* fsl_i2c_speed_map[].
	69	*
	70	* The last entry of the table must have a value of {-1, X}, where X is same
	71	* FDR/DFSR values as the second-to-last entry. This guarantees that any
	72	* search through the array will always find a match.
	73	*
	74	* The values of the divider must be in increasing numerical order, i.e.
	75	* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
	76	*
	77	* For this table, the values are based on a value of 1 for the DFSR
	78	* register. See the application note AN2919 "Determining the I2C Frequency
	79	* Divider Ratio for SCL"
	80	*/
	81	static const struct {
	82	unsigned short divider;
	83	u8 dfsr;
	84	u8 fdr;
	85	} fsl_i2c_speed_map[] = {
	86	{160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35},
	87	{288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2},
	88	{448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4},
	89	{608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3},
	90	{768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7},
	91	{1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9},
	92	{1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46},
	93	{1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12},
	94	{2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14},
	95	{3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16},
	96	{5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19},
	97	{8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22},
	98	{14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24},
	99	{20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27},
	100	{32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30},
	101	{61440, 1, 31}, {-1, 1, 31}
	102	};
	103
	104	/**
	105	* Set the I2C bus speed for a given I2C device
	106	*
	107	* @param dev: the I2C device
	108	* @i2c_clk: I2C bus clock frequency
	109	* @speed: the desired speed of the bus
	110	*
	111	* The I2C device must be stopped before calling this function.
	112	*
	113	* The return value is the actual bus speed that is set.
	114	*/
	115	static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
	116	unsigned int i2c_clk, unsigned int speed)
	117	{
	118	unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
	119	unsigned int i;
d8c82db4 TT	120
	121	/*
	122	* We want to choose an FDR/DFSR that generates an I2C bus speed that
	123	* is equal to or lower than the requested speed. That means that we
	124	* want the first divider that is equal to or greater than the
	125	* calculated divider.
	126	*/
	127
	128	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
	129	if (fsl_i2c_speed_map[i].divider >= divider) {
3e3f766a	130	u8 fdr, dfsr;
d8c82db4 TT	131	dfsr = fsl_i2c_speed_map[i].dfsr;
	132	fdr = fsl_i2c_speed_map[i].fdr;
	133	speed = i2c_clk / fsl_i2c_speed_map[i].divider;
3e3f766a KG	134	writeb(fdr, &dev->fdr); /* set bus speed */
3e3f766a KG	135	writeb(dfsr, &dev->dfsrr); /* set default filter */
d8c82db4 TT	136	break;
	137	}
	138
d8c82db4 TT	139	return speed;
	140	}
	141
debb7354 JL	142	void
	143	i2c_init(int speed, int slaveadd)
	144	{
d8c82db4	145	struct fsl_i2c *dev;
f2302d44	146	unsigned int temp;
be5e6181 TT	147
	148	dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
	149
	150	writeb(0, &dev->cr); /* stop I2C controller */
f6f5f709	151	udelay(5); /* let it shutdown in peace */
f2302d44 SR	152	temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
	153	if (gd->flags & GD_FLG_RELOC)
	154	i2c_bus_speed[0] = temp;
14198bf7	155	writeb(slaveadd << 1, &dev->adr); /* write slave address */
be5e6181 TT	156	writeb(0x0, &dev->sr); /* clear status register */
	157	writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
	158
	159	#ifdef CFG_I2C2_OFFSET
	160	dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
	161
	162	writeb(0, &dev->cr); /* stop I2C controller */
e739bc95	163	udelay(5); /* let it shutdown in peace */
f2302d44 SR	164	temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
	165	if (gd->flags & GD_FLG_RELOC)
	166	i2c_bus_speed[1] = temp;
e739bc95	167	writeb(slaveadd << 1, &dev->adr); /* write slave address */
be5e6181 TT	168	writeb(0x0, &dev->sr); /* clear status register */
be5e6181 TT	169	writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
d8c82db4	170	#endif
debb7354 JL	171	}
	172
	173	static __inline__ int
5c9efb36	174	i2c_wait4bus(void)
debb7354	175	{
f2302d44	176	unsigned long long timeval = get_ticks();
debb7354	177
be5e6181	178	while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
f2302d44	179	if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT))
debb7354	180	return -1;
debb7354 JL	181	}
debb7354 JL	182
5c9efb36	183	return 0;
debb7354 JL	184	}
	185
	186	static __inline__ int
5c9efb36	187	i2c_wait(int write)
debb7354 JL	188	{
debb7354 JL	189	u32 csr;
f2302d44	190	unsigned long long timeval = get_ticks();
debb7354 JL	191
debb7354 JL	192	do {
be5e6181	193	csr = readb(&i2c_dev[i2c_bus_num]->sr);
7237c033	194	if (!(csr & I2C_SR_MIF))
debb7354 JL	195	continue;
debb7354 JL	196
be5e6181	197	writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
debb7354	198
7237c033	199	if (csr & I2C_SR_MAL) {
debb7354 JL	200	debug("i2c_wait: MAL\n");
	201	return -1;
	202	}
	203
7237c033	204	if (!(csr & I2C_SR_MCF)) {
debb7354 JL	205	debug("i2c_wait: unfinished\n");
	206	return -1;
	207	}
	208
1939d969	209	if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
debb7354 JL	210	debug("i2c_wait: No RXACK\n");
	211	return -1;
	212	}
	213
	214	return 0;
f2302d44	215	} while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT));
debb7354 JL	216
	217	debug("i2c_wait: timed out\n");
	218	return -1;
	219	}
	220
	221	static __inline__ int
7237c033	222	i2c_write_addr (u8 dev, u8 dir, int rsta)
debb7354	223	{
7237c033 JL	224	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_MTX
7237c033 JL	225	\| (rsta ? I2C_CR_RSTA : 0),
be5e6181	226	&i2c_dev[i2c_bus_num]->cr);
debb7354	227
be5e6181	228	writeb((dev << 1) \| dir, &i2c_dev[i2c_bus_num]->dr);
debb7354	229
1939d969	230	if (i2c_wait(I2C_WRITE_BIT) < 0)
debb7354 JL	231	return 0;
	232
	233	return 1;
	234	}
	235
	236	static __inline__ int
ffff3ae5	237	__i2c_write(u8 *data, int length)
debb7354 JL	238	{
debb7354 JL	239	int i;
5c9efb36	240
7237c033	241	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_MTX,
be5e6181	242	&i2c_dev[i2c_bus_num]->cr);
debb7354	243
5c9efb36	244	for (i = 0; i < length; i++) {
be5e6181	245	writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
debb7354	246
1939d969	247	if (i2c_wait(I2C_WRITE_BIT) < 0)
debb7354 JL	248	break;
	249	}
	250
	251	return i;
	252	}
	253
	254	static __inline__ int
ffff3ae5	255	__i2c_read(u8 *data, int length)
debb7354 JL	256	{
	257	int i;
	258
7237c033	259	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| ((length == 1) ? I2C_CR_TXAK : 0),
be5e6181	260	&i2c_dev[i2c_bus_num]->cr);
debb7354 JL	261
debb7354 JL	262	/* dummy read */
be5e6181	263	readb(&i2c_dev[i2c_bus_num]->dr);
debb7354	264
5c9efb36	265	for (i = 0; i < length; i++) {
1939d969	266	if (i2c_wait(I2C_READ_BIT) < 0)
debb7354 JL	267	break;
	268
	269	/* Generate ack on last next to last byte */
	270	if (i == length - 2)
7237c033	271	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_TXAK,
be5e6181	272	&i2c_dev[i2c_bus_num]->cr);
debb7354 JL	273
	274	/* Generate stop on last byte */
	275	if (i == length - 1)
be5e6181	276	writeb(I2C_CR_MEN \| I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
debb7354	277
be5e6181	278	data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
debb7354	279	}
5c9efb36	280
debb7354 JL	281	return i;
	282	}
	283
	284	int
ffff3ae5	285	i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
debb7354	286	{
f6f5f709	287	int i = -1; /* signal error */
7237c033	288	u8 a = (u8)&addr;
debb7354	289
4d45f69e	290	if (i2c_wait4bus() >= 0
1939d969	291	&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
f6f5f709 JT	292	&& __i2c_write(&a[4 - alen], alen) == alen)
	293	i = 0; /* No error so far */
	294
	295	if (length
	296	&& i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
4d45f69e	297	i = __i2c_read(data, length);
debb7354	298
be5e6181	299	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
debb7354	300
4d45f69e JL	301	if (i == length)
	302	return 0;
	303
	304	return -1;
debb7354 JL	305	}
	306
	307	int
ffff3ae5	308	i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
debb7354	309	{
f6f5f709	310	int i = -1; /* signal error */
7237c033	311	u8 a = (u8)&addr;
debb7354	312
4d45f69e	313	if (i2c_wait4bus() >= 0
1939d969	314	&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
4d45f69e JL	315	&& __i2c_write(&a[4 - alen], alen) == alen) {
	316	i = __i2c_write(data, length);
	317	}
debb7354	318
be5e6181	319	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
debb7354	320
4d45f69e JL	321	if (i == length)
	322	return 0;
	323
	324	return -1;
debb7354 JL	325	}
debb7354 JL	326
ffff3ae5 JL	327	int
ffff3ae5 JL	328	i2c_probe(uchar chip)
debb7354	329	{
f6f5f709 JT	330	/* For unknow reason the controller will ACK when
	331	* probing for a slave with the same address, so skip
	332	* it.
debb7354	333	*/
f6f5f709 JT	334	if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
f6f5f709 JT	335	return -1;
debb7354	336
f6f5f709	337	return i2c_read(chip, 0, 0, NULL, 0);
debb7354 JL	338	}
debb7354 JL	339
ffff3ae5 JL	340	uchar
ffff3ae5 JL	341	i2c_reg_read(uchar i2c_addr, uchar reg)
debb7354	342	{
7237c033	343	uchar buf[1];
debb7354	344
5c9efb36	345	i2c_read(i2c_addr, reg, 1, buf, 1);
debb7354	346
5c9efb36	347	return buf[0];
debb7354 JL	348	}
debb7354 JL	349
ffff3ae5 JL	350	void
ffff3ae5 JL	351	i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
debb7354	352	{
5c9efb36	353	i2c_write(i2c_addr, reg, 1, &val, 1);
debb7354 JL	354	}
debb7354 JL	355
be5e6181 TT	356	int i2c_set_bus_num(unsigned int bus)
	357	{
	358	#ifdef CFG_I2C2_OFFSET
	359	if (bus > 1) {
	360	#else
	361	if (bus > 0) {
	362	#endif
	363	return -1;
	364	}
	365
	366	i2c_bus_num = bus;
	367
	368	return 0;
	369	}
	370
	371	int i2c_set_bus_speed(unsigned int speed)
	372	{
d8c82db4 TT	373	unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
	374
	375	writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
	376	i2c_bus_speed[i2c_bus_num] =
	377	set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
	378	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
	379
	380	return 0;
be5e6181 TT	381	}
	382
	383	unsigned int i2c_get_bus_num(void)
	384	{
	385	return i2c_bus_num;
	386	}
	387
	388	unsigned int i2c_get_bus_speed(void)
	389	{
d8c82db4	390	return i2c_bus_speed[i2c_bus_num];
be5e6181	391	}
d8c82db4	392
debb7354	393	#endif /* CONFIG_HARD_I2C */
20476726	394	#endif /* CONFIG_FSL_I2C */