projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cff842b KJS |
1 | /* |
| 2 | * Faraday I2C Controller | |
| 3 | * | |
| 4 | * (C) Copyright 2010 Faraday Technology | |
| 5 | * Dante Su <dantesu@faraday-tech.com> | |
| 6 | * | |
| 8dde4ca9 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 3cff842b KJS |
8 | */ |
| 9 | ||
| 10 | #ifndef __FTI2C010_H | |
| 11 | #define __FTI2C010_H | |
| 12 | ||
| 13 | /* | |
| 14 | * FTI2C010 registers | |
| 15 | */ | |
| 16 | struct fti2c010_regs { | |
| 17 | uint32_t cr; /* 0x00: control register */ | |
| 18 | uint32_t sr; /* 0x04: status register */ | |
| 19 | uint32_t cdr; /* 0x08: clock division register */ | |
| 20 | uint32_t dr; /* 0x0c: data register */ | |
| 21 | uint32_t sar; /* 0x10: slave address register */ | |
| 22 | uint32_t tgsr;/* 0x14: time & glitch suppression register */ | |
| 23 | uint32_t bmr; /* 0x18: bus monitor register */ | |
| 24 | uint32_t rsvd[5]; | |
| 25 | uint32_t revr;/* 0x30: revision register */ | |
| 26 | }; | |
| 27 | ||
| 28 | /* | |
| 29 | * control register | |
| 30 | */ | |
| 31 | #define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */ | |
| 32 | #define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */ | |
| 33 | #define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */ | |
| 34 | #define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */ | |
| 35 | #define CR_DRIRQ 0x200 /* rx interrupt (both) */ | |
| 36 | #define CR_DTIRQ 0x100 /* tx interrupt (both) */ | |
| 37 | #define CR_TBEN 0x80 /* tx enable (both) */ | |
| 38 | #define CR_NAK 0x40 /* NACK (both) */ | |
| 39 | #define CR_STOP 0x20 /* stop (master) */ | |
| 40 | #define CR_START 0x10 /* start (master) */ | |
| 41 | #define CR_GCEN 0x8 /* general call support (slave) */ | |
| 42 | #define CR_SCLEN 0x4 /* enable clock out (master) */ | |
| 43 | #define CR_I2CEN 0x2 /* enable I2C (both) */ | |
| 44 | #define CR_I2CRST 0x1 /* reset I2C (both) */ | |
| 45 | #define CR_ENABLE \ | |
| 46 | (CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN) | |
| 47 | ||
| 48 | /* | |
| 49 | * status register | |
| 50 | */ | |
| 51 | #define SR_CLRAL 0x400 /* clear arbitration lost */ | |
| 52 | #define SR_CLRGC 0x200 /* clear general call */ | |
| 53 | #define SR_CLRSAM 0x100 /* clear slave address match */ | |
| 54 | #define SR_CLRSTOP 0x80 /* clear stop */ | |
| 55 | #define SR_CLRNAKR 0x40 /* clear NACK respond */ | |
| 56 | #define SR_DR 0x20 /* rx ready */ | |
| 57 | #define SR_DT 0x10 /* tx done */ | |
| 58 | #define SR_BB 0x8 /* bus busy */ | |
| 59 | #define SR_BUSY 0x4 /* chip busy */ | |
| 60 | #define SR_ACK 0x2 /* ACK/NACK received */ | |
| 61 | #define SR_RW 0x1 /* set when master-rx or slave-tx mode */ | |
| 62 | ||
| 63 | /* | |
| 64 | * clock division register | |
| 65 | */ | |
| 66 | #define CDR_DIV(n) ((n) & 0x3ffff) | |
| 67 | ||
| 68 | /* | |
| 69 | * time & glitch suppression register | |
| 70 | */ | |
| 71 | #define TGSR_GSR(n) (((n) & 0x7) << 10) | |
| 72 | #define TGSR_TSR(n) ((n) & 0x3ff) | |
| 73 | ||
| 74 | /* | |
| 75 | * bus monitor register | |
| 76 | */ | |
| 77 | #define BMR_SCL 0x2 /* SCL is pull-up */ | |
| 78 | #define BMR_SDA 0x1 /* SDA is pull-up */ | |
| 79 | ||
| 80 | #endif /* __FTI2C010_H */ |