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eeprom: fix eeprom write procedure
[people/ms/u-boot.git] / drivers / i2c / mxc_i2c.c
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cdace066 1/*
db84140b 2 * i2c driver for Freescale i.MX series
cdace066
SH		 3 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
db84140b
MV		 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
12 *
cdace066 13 *
1a459660 14 * SPDX-License-Identifier: GPL-2.0+
cdace066
SH		 15 */
16
17#include <common.h>
127cec18 18#include <asm/arch/clock.h>
86271115 19#include <asm/arch/imx-regs.h>
cea60b0c 20#include <asm/errno.h>
71204e95 21#include <asm/imx-common/mxc_i2c.h>
24cd738b 22#include <asm/io.h>
bf0783df 23#include <i2c.h>
7aa57a01 24#include <watchdog.h>
71204e95
PF		 25#include <dm.h>
26#include <fdtdec.h>
cdace066 27
dec1861b
YS		 28DECLARE_GLOBAL_DATA_PTR;
29
71204e95
PF		 30#define I2C_QUIRK_FLAG (1 << 0)
31
32#define IMX_I2C_REGSHIFT 2
33#define VF610_I2C_REGSHIFT 0
34/* Register index */
35#define IADR 0
36#define IFDR 1
37#define I2CR 2
38#define I2SR 3
39#define I2DR 4
cdace066 40
cdace066
SH		 41#define I2CR_IIEN (1 << 6)
42#define I2CR_MSTA (1 << 5)
43#define I2CR_MTX (1 << 4)
44#define I2CR_TX_NO_AK (1 << 3)
45#define I2CR_RSTA (1 << 2)
46
47#define I2SR_ICF (1 << 7)
48#define I2SR_IBB (1 << 5)
d5383a63 49#define I2SR_IAL (1 << 4)
cdace066
SH		 50#define I2SR_IIF (1 << 1)
51#define I2SR_RX_NO_AK (1 << 0)
52
30ea41a4
AW		 53#ifdef I2C_QUIRK_REG
54#define I2CR_IEN (0 << 7)
55#define I2CR_IDIS (1 << 7)
56#define I2SR_IIF_CLEAR (1 << 1)
57#else
58#define I2CR_IEN (1 << 7)
59#define I2CR_IDIS (0 << 7)
60#define I2SR_IIF_CLEAR (0 << 1)
61#endif
62
e4ff525f 63#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
de6f604d 64#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
cdace066
SH		 65#endif
66
30ea41a4
AW		 67#ifdef I2C_QUIRK_REG
68static u16 i2c_clk_div[60][2] = {
69 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
70 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
71 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
72 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
73 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
74 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
75 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
76 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
77 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
78 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
79 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
80 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
81 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
82 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
83 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
84};
85#else
db84140b
MV		 86static u16 i2c_clk_div[50][2] = {
87 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
88 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
89 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
90 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
91 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
92 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
93 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
94 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
95 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
96 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
97 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
98 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
99 { 3072, 0x1E }, { 3840, 0x1F }
100};
30ea41a4 101#endif
db84140b 102
fac96408 103#ifndef CONFIG_SYS_MXC_I2C1_SPEED
104#define CONFIG_SYS_MXC_I2C1_SPEED 100000
105#endif
106#ifndef CONFIG_SYS_MXC_I2C2_SPEED
107#define CONFIG_SYS_MXC_I2C2_SPEED 100000
108#endif
109#ifndef CONFIG_SYS_MXC_I2C3_SPEED
110#define CONFIG_SYS_MXC_I2C3_SPEED 100000
111#endif
f8cb101e
YS		 112#ifndef CONFIG_SYS_MXC_I2C4_SPEED
113#define CONFIG_SYS_MXC_I2C4_SPEED 100000
114#endif
fac96408 115
116#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
117#define CONFIG_SYS_MXC_I2C1_SLAVE 0
118#endif
119#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
120#define CONFIG_SYS_MXC_I2C2_SLAVE 0
121#endif
122#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
123#define CONFIG_SYS_MXC_I2C3_SLAVE 0
124#endif
f8cb101e
YS		 125#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
126#define CONFIG_SYS_MXC_I2C4_SLAVE 0
127#endif
fac96408 128
db84140b
MV		 129/*
130 * Calculate and set proper clock divider
131 */
71204e95 132static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
cdace066 133{
db84140b
MV		 134 unsigned int i2c_clk_rate;
135 unsigned int div;
bf0783df 136 u8 clk_div;
cdace066 137
127cec18 138#if defined(CONFIG_MX31)
1d549ade
SB		 139 struct clock_control_regs *sc_regs =
140 (struct clock_control_regs *)CCM_BASE;
db84140b 141
e7de18af 142 /* start the required I2C clock */
de6f604d 143 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
1d549ade 144 &sc_regs->cgr0);
127cec18 145#endif
e7de18af 146
db84140b 147 /* Divider value calculation */
e7bed5c2 148 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
db84140b
MV		 149 div = (i2c_clk_rate + rate - 1) / rate;
150 if (div < i2c_clk_div[0][0])
b567b8ff 151 clk_div = 0;
db84140b 152 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
b567b8ff 153 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
db84140b 154 else
b567b8ff 155 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
db84140b
MV		 156 ;
157
158 /* Store divider value */
bf0783df 159 return clk_div;
db84140b 160}
cdace066 161
db84140b 162/*
e4ff525f 163 * Set I2C Bus speed
db84140b 164 */
71204e95 165static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
db84140b 166{
71204e95
PF		 167 ulong base = i2c_bus->base;
168 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
169 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
bf0783df 170 u8 idx = i2c_clk_div[clk_idx][1];
71204e95 171 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
bf0783df 172
e6c8b716
HS		 173 if (!base)
174 return -ENODEV;
175
bf0783df 176 /* Store divider value */
71204e95 177 writeb(idx, base + (IFDR << reg_shift));
bf0783df 178
83a1a190 179 /* Reset module */
71204e95
PF		 180 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
181 writeb(0, base + (I2SR << reg_shift));
b567b8ff
MV		 182 return 0;
183}
184
7aa57a01
TK		 185#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
186#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
187#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
81687212 188
71204e95 189static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
cdace066 190{
7aa57a01
TK		 191 unsigned sr;
192 ulong elapsed;
71204e95
PF		 193 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
194 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
195 ulong base = i2c_bus->base;
7aa57a01
TK		 196 ulong start_time = get_timer(0);
197 for (;;) {
71204e95 198 sr = readb(base + (I2SR << reg_shift));
d5383a63 199 if (sr & I2SR_IAL) {
71204e95
PF		 200 if (quirk)
201 writeb(sr | I2SR_IAL, base +
202 (I2SR << reg_shift));
203 else
204 writeb(sr & ~I2SR_IAL, base +
205 (I2SR << reg_shift));
d5383a63 206 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
71204e95
PF		 207 __func__, sr, readb(base + (I2CR << reg_shift)),
208 state);
d5383a63
TK		 209 return -ERESTART;
210 }
7aa57a01
TK		 211 if ((sr & (state >> 8)) == (unsigned char)state)
212 return sr;
213 WATCHDOG_RESET();
214 elapsed = get_timer(start_time);
215 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
216 break;
db84140b 217 }
7aa57a01 218 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
71204e95 219 sr, readb(base + (I2CR << reg_shift)), state);
cea60b0c 220 return -ETIMEDOUT;
cdace066
SH		 221}
222
71204e95 223static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
81687212 224{
cea60b0c 225 int ret;
71204e95
PF		 226 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
227 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
228 ulong base = i2c_bus->base;
81687212 229
71204e95
PF		 230 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
231 writeb(byte, base + (I2DR << reg_shift));
232
233 ret = wait_for_sr_state(i2c_bus, ST_IIF);
cea60b0c
TK		 234 if (ret < 0)
235 return ret;
cea60b0c
TK		 236 if (ret & I2SR_RX_NO_AK)
237 return -ENODEV;
238 return 0;
db84140b 239}
81687212 240
71204e95
PF		 241/*
242 * Stub implementations for outer i2c slave operations.
243 */
244void __i2c_force_reset_slave(void)
245{
246}
247void i2c_force_reset_slave(void)
248 __attribute__((weak, alias("__i2c_force_reset_slave")));
249
db84140b 250/*
90a5b70f 251 * Stop I2C transaction
db84140b 252 */
71204e95 253static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
cdace066 254{
7aa57a01 255 int ret;
71204e95
PF		 256 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
257 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
258 ulong base = i2c_bus->base;
259 unsigned int temp = readb(base + (I2CR << reg_shift));
db84140b 260
1c076dba 261 temp &= ~(I2CR_MSTA | I2CR_MTX);
71204e95
PF		 262 writeb(temp, base + (I2CR << reg_shift));
263 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
7aa57a01
TK		 264 if (ret < 0)
265 printf("%s:trigger stop failed\n", __func__);
cdace066
SH		 266}
267
db84140b 268/*
b230ddc2
TK		 269 * Send start signal, chip address and
270 * write register address
db84140b 271 */
71204e95
PF		 272static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
273 u32 addr, int alen)
cdace066 274{
71e9f3cb
TK		 275 unsigned int temp;
276 int ret;
71204e95
PF		 277 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
278 ulong base = i2c_bus->base;
279 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
280
281 /* Reset i2c slave */
282 i2c_force_reset_slave();
71e9f3cb
TK		 283
284 /* Enable I2C controller */
71204e95
PF		 285 if (quirk)
286 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
287 else
288 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
289
290 if (ret) {
291 writeb(I2CR_IEN, base + (I2CR << reg_shift));
90a5b70f
TK		 292 /* Wait for controller to be stable */
293 udelay(50);
294 }
71204e95
PF		 295
296 if (readb(base + (IADR << reg_shift)) == (chip << 1))
297 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
298 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
299 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
90a5b70f 300 if (ret < 0)
a7f1a005 301 return ret;
71e9f3cb
TK		 302
303 /* Start I2C transaction */
71204e95 304 temp = readb(base + (I2CR << reg_shift));
71e9f3cb 305 temp |= I2CR_MSTA;
71204e95 306 writeb(temp, base + (I2CR << reg_shift));
71e9f3cb 307
71204e95 308 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
71e9f3cb 309 if (ret < 0)
a7f1a005 310 return ret;
b230ddc2 311
71e9f3cb 312 temp |= I2CR_MTX | I2CR_TX_NO_AK;
71204e95 313 writeb(temp, base + (I2CR << reg_shift));
71e9f3cb 314
b230ddc2 315 /* write slave address */
71204e95 316 ret = tx_byte(i2c_bus, chip << 1);
b230ddc2 317 if (ret < 0)
a7f1a005 318 return ret;
db84140b 319
bf0783df 320 while (alen--) {
71204e95 321 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
cea60b0c 322 if (ret < 0)
a7f1a005 323 return ret;
81687212 324 }
b230ddc2 325 return 0;
a7f1a005
TK		 326}
327
71204e95
PF		 328#ifndef CONFIG_DM_I2C
329int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
330{
331 if (i2c_bus && i2c_bus->idle_bus_fn)
332 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
333 return 0;
334}
335#else
336/*
337 * Since pinmux is not supported, implement a weak function here.
338 * You can implement your i2c_bus_idle in board file. When pinctrl
339 * is supported, this can be removed.
340 */
341int __i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
342{
343 return 0;
344}
96c19bd3 345
71204e95
PF		 346int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
347 __attribute__((weak, alias("__i2c_idle_bus")));
348#endif
349
350static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
351 u32 addr, int alen)
a7f1a005
TK		 352{
353 int retry;
354 int ret;
71204e95
PF		 355 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
356 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
e6c8b716
HS		 357
358 if (!i2c_bus->base)
359 return -ENODEV;
360
a7f1a005 361 for (retry = 0; retry < 3; retry++) {
71204e95 362 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
a7f1a005
TK		 363 if (ret >= 0)
364 return 0;
71204e95 365 i2c_imx_stop(i2c_bus);
a7f1a005
TK		 366 if (ret == -ENODEV)
367 return ret;
368
369 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
370 retry);
371 if (ret != -ERESTART)
30ea41a4 372 /* Disable controller */
71204e95 373 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
a7f1a005 374 udelay(100);
71204e95 375 if (i2c_idle_bus(i2c_bus) < 0)
96c19bd3 376 break;
a7f1a005 377 }
71204e95 378 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
db84140b 379 return ret;
cdace066
SH		 380}
381
71204e95
PF		 382
383static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
384 int len)
385{
386 int i, ret = 0;
387
388 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
389 debug("write_data: ");
390 /* use rc for counter */
391 for (i = 0; i < len; ++i)
392 debug(" 0x%02x", buf[i]);
393 debug("\n");
394
395 for (i = 0; i < len; i++) {
396 ret = tx_byte(i2c_bus, buf[i]);
397 if (ret < 0) {
398 debug("i2c_write_data(): rc=%d\n", ret);
399 break;
400 }
401 }
402
403 return ret;
404}
405
406static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
407 int len)
db84140b 408{
db84140b
MV		 409 int ret;
410 unsigned int temp;
411 int i;
71204e95
PF		 412 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
413 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
414 ulong base = i2c_bus->base;
db84140b 415
71204e95 416 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
db84140b
MV		 417
418 /* setup bus to read data */
71204e95 419 temp = readb(base + (I2CR << reg_shift));
db84140b
MV		 420 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
421 if (len == 1)
422 temp |= I2CR_TX_NO_AK;
71204e95
PF		 423 writeb(temp, base + (I2CR << reg_shift));
424 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
425 /* dummy read to clear ICF */
426 readb(base + (I2DR << reg_shift));
db84140b
MV		 427
428 /* read data */
429 for (i = 0; i < len; i++) {
71204e95 430 ret = wait_for_sr_state(i2c_bus, ST_IIF);
7aa57a01 431 if (ret < 0) {
71204e95
PF		 432 debug("i2c_read_data(): ret=%d\n", ret);
433 i2c_imx_stop(i2c_bus);
db84140b 434 return ret;
c4330d28 435 }
db84140b
MV		 436
437 /*
438 * It must generate STOP before read I2DR to prevent
439 * controller from generating another clock cycle
440 */
441 if (i == (len - 1)) {
71204e95 442 i2c_imx_stop(i2c_bus);
db84140b 443 } else if (i == (len - 2)) {
71204e95 444 temp = readb(base + (I2CR << reg_shift));
db84140b 445 temp |= I2CR_TX_NO_AK;
71204e95 446 writeb(temp, base + (I2CR << reg_shift));
db84140b 447 }
71204e95
PF		 448 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
449 buf[i] = readb(base + (I2DR << reg_shift));
cdace066 450 }
71204e95
PF		 451
452 /* reuse ret for counter*/
453 for (ret = 0; ret < len; ++ret)
454 debug(" 0x%02x", buf[ret]);
455 debug("\n");
456
457 i2c_imx_stop(i2c_bus);
7aa57a01 458 return 0;
cdace066
SH		 459}
460
71204e95 461#ifndef CONFIG_DM_I2C
db84140b 462/*
71204e95 463 * Read data from I2C device
db84140b 464 */
71204e95
PF		 465static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
466 int alen, u8 *buf, int len)
cdace066 467{
71204e95
PF		 468 int ret = 0;
469 u32 temp;
470 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
471 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
472 ulong base = i2c_bus->base;
cdace066 473
71204e95 474 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
cea60b0c 475 if (ret < 0)
db84140b 476 return ret;
cdace066 477
71204e95
PF		 478 temp = readb(base + (I2CR << reg_shift));
479 temp |= I2CR_RSTA;
480 writeb(temp, base + (I2CR << reg_shift));
481
482 ret = tx_byte(i2c_bus, (chip << 1) | 1);
483 if (ret < 0) {
484 i2c_imx_stop(i2c_bus);
485 return ret;
db84140b 486 }
71204e95
PF		 487
488 ret = i2c_read_data(i2c_bus, chip, buf, len);
489
490 i2c_imx_stop(i2c_bus);
491 return ret;
492}
493
494/*
495 * Write data to I2C device
496 */
497static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
498 int alen, const u8 *buf, int len)
499{
500 int ret = 0;
501
502 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
503 if (ret < 0)
504 return ret;
505
506 ret = i2c_write_data(i2c_bus, chip, buf, len);
507
508 i2c_imx_stop(i2c_bus);
509
db84140b
MV		 510 return ret;
511}
cfbb88d3 512
e6c8b716
HS		 513#if !defined(I2C2_BASE_ADDR)
514#define I2C2_BASE_ADDR 0
21a26940 515#endif
e6c8b716
HS		 516
517#if !defined(I2C3_BASE_ADDR)
518#define I2C3_BASE_ADDR 0
519#endif
520
521#if !defined(I2C4_BASE_ADDR)
522#define I2C4_BASE_ADDR 0
523#endif
524
525static struct mxc_i2c_bus mxc_i2c_buses[] = {
9f3183d2
MH		 526#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \
527 defined(CONFIG_FSL_LAYERSCAPE)
71204e95
PF		 528 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
529 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
530 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
531 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
e4ff525f 532#else
e6c8b716
HS		 533 { 0, I2C1_BASE_ADDR, 0 },
534 { 1, I2C2_BASE_ADDR, 0 },
535 { 2, I2C3_BASE_ADDR, 0 },
536 { 3, I2C4_BASE_ADDR, 0 },
e4ff525f 537#endif
fac96408 538};
539
71204e95 540struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
96c19bd3 541{
71204e95 542 return &mxc_i2c_buses[adap->hwadapnr];
96c19bd3
TK		 543}
544
fac96408 545static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
546 uint addr, int alen, uint8_t *buffer,
547 int len)
e4ff525f 548{
fac96408 549 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
e4ff525f
TK		 550}
551
fac96408 552static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
553 uint addr, int alen, uint8_t *buffer,
554 int len)
e4ff525f 555{
fac96408 556 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
e4ff525f
TK		 557}
558
cfbb88d3
TK		 559/*
560 * Test if a chip at a given address responds (probe the chip)
561 */
fac96408 562static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
cfbb88d3 563{
fac96408 564 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
e4ff525f
TK		 565}
566
71204e95
PF		 567int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
568{
569 return 1;
570}
571int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
572 __attribute__((weak, alias("__enable_i2c_clk")));
573
574void bus_i2c_init(int index, int speed, int unused,
575 int (*idle_bus_fn)(void *p), void *idle_bus_data)
e4ff525f 576{
71204e95
PF		 577 int ret;
578
579 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
580 debug("Error i2c index\n");
e4ff525f 581 return;
e4ff525f 582 }
71204e95
PF		 583
584 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
585 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
586
587 ret = enable_i2c_clk(1, index);
588 if (ret < 0) {
589 debug("I2C-%d clk fail to enable.\n", index);
590 return;
591 }
592
593 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
e4ff525f
TK		 594}
595
596/*
597 * Init I2C Bus
598 */
fac96408 599static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
e4ff525f 600{
71204e95 601 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
e4ff525f
TK		 602}
603
604/*
605 * Set I2C Speed
606 */
71204e95 607static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
e4ff525f 608{
fac96408 609 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
e4ff525f
TK		 610}
611
612/*
fac96408 613 * Register mxc i2c adapters
e4ff525f 614 */
03544c66 615#ifdef CONFIG_SYS_I2C_MXC_I2C1
fac96408 616U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
617 mxc_i2c_read, mxc_i2c_write,
618 mxc_i2c_set_bus_speed,
619 CONFIG_SYS_MXC_I2C1_SPEED,
620 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
03544c66
AA		 621#endif
622
623#ifdef CONFIG_SYS_I2C_MXC_I2C2
fac96408 624U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
625 mxc_i2c_read, mxc_i2c_write,
626 mxc_i2c_set_bus_speed,
627 CONFIG_SYS_MXC_I2C2_SPEED,
628 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
03544c66
AA		 629#endif
630
f8cb101e 631#ifdef CONFIG_SYS_I2C_MXC_I2C3
fac96408 632U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
633 mxc_i2c_read, mxc_i2c_write,
634 mxc_i2c_set_bus_speed,
635 CONFIG_SYS_MXC_I2C3_SPEED,
636 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
637#endif
71204e95 638
f8cb101e
YS		 639#ifdef CONFIG_SYS_I2C_MXC_I2C4
640U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
641 mxc_i2c_read, mxc_i2c_write,
642 mxc_i2c_set_bus_speed,
643 CONFIG_SYS_MXC_I2C4_SPEED,
644 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
645#endif
71204e95
PF		 646
647#else
648
649static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
650{
651 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
652
653 return bus_i2c_set_bus_speed(i2c_bus, speed);
654}
655
656static int mxc_i2c_probe(struct udevice *bus)
657{
658 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
659 fdt_addr_t addr;
660 int ret;
661
662 i2c_bus->driver_data = dev_get_driver_data(bus);
663
664 addr = dev_get_addr(bus);
665 if (addr == FDT_ADDR_T_NONE)
666 return -ENODEV;
667
668 i2c_bus->base = addr;
669 i2c_bus->index = bus->seq;
670
671 /* Enable clk */
672 ret = enable_i2c_clk(1, bus->seq);
673 if (ret < 0)
674 return ret;
675
676 ret = i2c_idle_bus(i2c_bus);
677 if (ret < 0) {
678 /* Disable clk */
679 enable_i2c_clk(0, bus->seq);
680 return ret;
681 }
682
683 /*
684 * Pinmux settings are in board file now, until pinmux is supported,
685 * we can set pinmux here in probe function.
686 */
687
688 debug("i2c : controller bus %d at %lu , speed %d: ",
689 bus->seq, i2c_bus->base,
690 i2c_bus->speed);
691
692 return 0;
693}
694
695static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
696 u32 chip_flags)
697{
698 int ret;
699 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
700
701 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
702 if (ret < 0) {
703 debug("%s failed, ret = %d\n", __func__, ret);
704 return ret;
705 }
706
707 i2c_imx_stop(i2c_bus);
708
709 return 0;
710}
711
712static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
713{
714 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
715 int ret = 0;
716 ulong base = i2c_bus->base;
717 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
718 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
719
720 /*
721 * Here the 3rd parameter addr and the 4th one alen are set to 0,
722 * because here we only want to send out chip address. The register
723 * address is wrapped in msg.
724 */
725 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
726 if (ret < 0) {
727 debug("i2c_init_transfer error: %d\n", ret);
728 return ret;
729 }
730
731 for (; nmsgs > 0; nmsgs--, msg++) {
732 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
733 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
734 if (msg->flags & I2C_M_RD)
735 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
736 msg->len);
737 else {
738 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
739 msg->len);
740 if (ret)
741 break;
742 if (next_is_read) {
743 /* Reuse ret */
744 ret = readb(base + (I2CR << reg_shift));
745 ret |= I2CR_RSTA;
746 writeb(ret, base + (I2CR << reg_shift));
747
748 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
749 if (ret < 0) {
750 i2c_imx_stop(i2c_bus);
751 break;
752 }
753 }
754 }
755 }
756
757 if (ret)
758 debug("i2c_write: error sending\n");
759
760 i2c_imx_stop(i2c_bus);
761
762 return ret;
763}
764
765static const struct dm_i2c_ops mxc_i2c_ops = {
766 .xfer = mxc_i2c_xfer,
767 .probe_chip = mxc_i2c_probe_chip,
768 .set_bus_speed = mxc_i2c_set_bus_speed,
769};
770
771static const struct udevice_id mxc_i2c_ids[] = {
772 { .compatible = "fsl,imx21-i2c", },
773 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
774 {}
775};
776
777U_BOOT_DRIVER(i2c_mxc) = {
778 .name = "i2c_mxc",
779 .id = UCLASS_I2C,
780 .of_match = mxc_i2c_ids,
781 .probe = mxc_i2c_probe,
782 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
783 .ops = &mxc_i2c_ops,
784};
785#endif
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