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[people/ms/u-boot.git] / drivers / i2c / stm32f7_i2c.c
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4fadcaf0
PC		 1/*
2 * (C) Copyright 2017 STMicroelectronics
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <dm.h>
10#include <i2c.h>
11#include <reset.h>
12
13#include <dm/device.h>
14#include <linux/io.h>
15
16/* STM32 I2C registers */
17struct stm32_i2c_regs {
18 u32 cr1; /* I2C control register 1 */
19 u32 cr2; /* I2C control register 2 */
20 u32 oar1; /* I2C own address 1 register */
21 u32 oar2; /* I2C own address 2 register */
22 u32 timingr; /* I2C timing register */
23 u32 timeoutr; /* I2C timeout register */
24 u32 isr; /* I2C interrupt and status register */
25 u32 icr; /* I2C interrupt clear register */
26 u32 pecr; /* I2C packet error checking register */
27 u32 rxdr; /* I2C receive data register */
28 u32 txdr; /* I2C transmit data register */
29};
30
31#define STM32_I2C_CR1 0x00
32#define STM32_I2C_CR2 0x04
33#define STM32_I2C_TIMINGR 0x10
34#define STM32_I2C_ISR 0x18
35#define STM32_I2C_ICR 0x1C
36#define STM32_I2C_RXDR 0x24
37#define STM32_I2C_TXDR 0x28
38
39/* STM32 I2C control 1 */
40#define STM32_I2C_CR1_ANFOFF BIT(12)
41#define STM32_I2C_CR1_ERRIE BIT(7)
42#define STM32_I2C_CR1_TCIE BIT(6)
43#define STM32_I2C_CR1_STOPIE BIT(5)
44#define STM32_I2C_CR1_NACKIE BIT(4)
45#define STM32_I2C_CR1_ADDRIE BIT(3)
46#define STM32_I2C_CR1_RXIE BIT(2)
47#define STM32_I2C_CR1_TXIE BIT(1)
48#define STM32_I2C_CR1_PE BIT(0)
49
50/* STM32 I2C control 2 */
51#define STM32_I2C_CR2_AUTOEND BIT(25)
52#define STM32_I2C_CR2_RELOAD BIT(24)
53#define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
54#define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
55#define STM32_I2C_CR2_NACK BIT(15)
56#define STM32_I2C_CR2_STOP BIT(14)
57#define STM32_I2C_CR2_START BIT(13)
58#define STM32_I2C_CR2_HEAD10R BIT(12)
59#define STM32_I2C_CR2_ADD10 BIT(11)
60#define STM32_I2C_CR2_RD_WRN BIT(10)
61#define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
62#define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK))
63#define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
64#define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
65#define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
66 | STM32_I2C_CR2_NBYTES_MASK \
67 | STM32_I2C_CR2_SADD7_MASK \
68 | STM32_I2C_CR2_RELOAD \
69 | STM32_I2C_CR2_RD_WRN)
70
71/* STM32 I2C Interrupt Status */
72#define STM32_I2C_ISR_BUSY BIT(15)
73#define STM32_I2C_ISR_ARLO BIT(9)
74#define STM32_I2C_ISR_BERR BIT(8)
75#define STM32_I2C_ISR_TCR BIT(7)
76#define STM32_I2C_ISR_TC BIT(6)
77#define STM32_I2C_ISR_STOPF BIT(5)
78#define STM32_I2C_ISR_NACKF BIT(4)
79#define STM32_I2C_ISR_ADDR BIT(3)
80#define STM32_I2C_ISR_RXNE BIT(2)
81#define STM32_I2C_ISR_TXIS BIT(1)
82#define STM32_I2C_ISR_TXE BIT(0)
83#define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
84 | STM32_I2C_ISR_ARLO)
85
86/* STM32 I2C Interrupt Clear */
87#define STM32_I2C_ICR_ARLOCF BIT(9)
88#define STM32_I2C_ICR_BERRCF BIT(8)
89#define STM32_I2C_ICR_STOPCF BIT(5)
90#define STM32_I2C_ICR_NACKCF BIT(4)
91
92/* STM32 I2C Timing */
93#define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
94#define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
95#define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
96#define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
97#define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
98
99#define STM32_I2C_MAX_LEN 0xff
100
101#define STM32_I2C_DNF_DEFAULT 0
102#define STM32_I2C_DNF_MAX 16
103
104#define STM32_I2C_ANALOG_FILTER_ENABLE 1
105#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
106#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
107
108#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
109#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
110
111#define STM32_PRESC_MAX BIT(4)
112#define STM32_SCLDEL_MAX BIT(4)
113#define STM32_SDADEL_MAX BIT(4)
114#define STM32_SCLH_MAX BIT(8)
115#define STM32_SCLL_MAX BIT(8)
116
117#define STM32_NSEC_PER_SEC 1000000000L
118
119#define STANDARD_RATE 100000
120#define FAST_RATE 400000
121#define FAST_PLUS_RATE 1000000
122
123enum stm32_i2c_speed {
124 STM32_I2C_SPEED_STANDARD, /* 100 kHz */
125 STM32_I2C_SPEED_FAST, /* 400 kHz */
126 STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */
127 STM32_I2C_SPEED_END,
128};
129
130/**
131 * struct stm32_i2c_spec - private i2c specification timing
132 * @rate: I2C bus speed (Hz)
133 * @rate_min: 80% of I2C bus speed (Hz)
134 * @rate_max: 120% of I2C bus speed (Hz)
135 * @fall_max: Max fall time of both SDA and SCL signals (ns)
136 * @rise_max: Max rise time of both SDA and SCL signals (ns)
137 * @hddat_min: Min data hold time (ns)
138 * @vddat_max: Max data valid time (ns)
139 * @sudat_min: Min data setup time (ns)
140 * @l_min: Min low period of the SCL clock (ns)
141 * @h_min: Min high period of the SCL clock (ns)
142 */
143
144struct stm32_i2c_spec {
145 u32 rate;
146 u32 rate_min;
147 u32 rate_max;
148 u32 fall_max;
149 u32 rise_max;
150 u32 hddat_min;
151 u32 vddat_max;
152 u32 sudat_min;
153 u32 l_min;
154 u32 h_min;
155};
156
157/**
158 * struct stm32_i2c_setup - private I2C timing setup parameters
159 * @speed: I2C speed mode (standard, Fast Plus)
160 * @speed_freq: I2C speed frequency (Hz)
161 * @clock_src: I2C clock source frequency (Hz)
162 * @rise_time: Rise time (ns)
163 * @fall_time: Fall time (ns)
164 * @dnf: Digital filter coefficient (0-16)
165 * @analog_filter: Analog filter delay (On/Off)
166 */
167struct stm32_i2c_setup {
168 enum stm32_i2c_speed speed;
169 u32 speed_freq;
170 u32 clock_src;
171 u32 rise_time;
172 u32 fall_time;
173 u8 dnf;
174 bool analog_filter;
175};
176
177/**
178 * struct stm32_i2c_timings - private I2C output parameters
179 * @prec: Prescaler value
180 * @scldel: Data setup time
181 * @sdadel: Data hold time
182 * @sclh: SCL high period (master mode)
183 * @sclh: SCL low period (master mode)
184 */
185struct stm32_i2c_timings {
186 struct list_head node;
187 u8 presc;
188 u8 scldel;
189 u8 sdadel;
190 u8 sclh;
191 u8 scll;
192};
193
194struct stm32_i2c_priv {
195 struct stm32_i2c_regs *regs;
196 struct clk clk;
197 struct stm32_i2c_setup *setup;
198 int speed;
199};
200
201static struct stm32_i2c_spec i2c_specs[] = {
202 [STM32_I2C_SPEED_STANDARD] = {
203 .rate = STANDARD_RATE,
204 .rate_min = 8000,
205 .rate_max = 120000,
206 .fall_max = 300,
207 .rise_max = 1000,
208 .hddat_min = 0,
209 .vddat_max = 3450,
210 .sudat_min = 250,
211 .l_min = 4700,
212 .h_min = 4000,
213 },
214 [STM32_I2C_SPEED_FAST] = {
215 .rate = FAST_RATE,
216 .rate_min = 320000,
217 .rate_max = 480000,
218 .fall_max = 300,
219 .rise_max = 300,
220 .hddat_min = 0,
221 .vddat_max = 900,
222 .sudat_min = 100,
223 .l_min = 1300,
224 .h_min = 600,
225 },
226 [STM32_I2C_SPEED_FAST_PLUS] = {
227 .rate = FAST_PLUS_RATE,
228 .rate_min = 800000,
229 .rate_max = 1200000,
230 .fall_max = 100,
231 .rise_max = 120,
232 .hddat_min = 0,
233 .vddat_max = 450,
234 .sudat_min = 50,
235 .l_min = 500,
236 .h_min = 260,
237 },
238};
239
240static struct stm32_i2c_setup stm32f7_setup = {
241 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
242 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
243 .dnf = STM32_I2C_DNF_DEFAULT,
244 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
245};
246
247DECLARE_GLOBAL_DATA_PTR;
248
249static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
250{
251 struct stm32_i2c_regs *regs = i2c_priv->regs;
252 u32 status = readl(&regs->isr);
253
254 if (status & STM32_I2C_ISR_BUSY)
255 return -EBUSY;
256
257 return 0;
258}
259
260static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
261 struct i2c_msg *msg, bool stop)
262{
263 struct stm32_i2c_regs *regs = i2c_priv->regs;
264 u32 cr2 = readl(&regs->cr2);
265
266 /* Set transfer direction */
267 cr2 &= ~STM32_I2C_CR2_RD_WRN;
268 if (msg->flags & I2C_M_RD)
269 cr2 |= STM32_I2C_CR2_RD_WRN;
270
271 /* Set slave address */
272 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
273 if (msg->flags & I2C_M_TEN) {
274 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
275 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
276 cr2 |= STM32_I2C_CR2_ADD10;
277 } else {
278 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
279 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
280 }
281
282 /* Set nb bytes to transfer and reload or autoend bits */
283 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
284 STM32_I2C_CR2_AUTOEND);
285 if (msg->len > STM32_I2C_MAX_LEN) {
286 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
287 cr2 |= STM32_I2C_CR2_RELOAD;
288 } else {
289 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
290 }
291
292 /* Write configurations register */
293 writel(cr2, &regs->cr2);
294
295 /* START/ReSTART generation */
296 setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
297}
298
299/*
300 * RELOAD mode must be selected if total number of data bytes to be
301 * sent is greater than MAX_LEN
302 */
303
304static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
305 struct i2c_msg *msg, bool stop)
306{
307 struct stm32_i2c_regs *regs = i2c_priv->regs;
308 u32 cr2 = readl(&regs->cr2);
309
310 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
311
312 if (msg->len > STM32_I2C_MAX_LEN) {
313 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
314 } else {
315 cr2 &= ~STM32_I2C_CR2_RELOAD;
316 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
317 }
318
319 writel(cr2, &regs->cr2);
320}
321
322static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
323 u32 flags, u32 *status)
324{
325 struct stm32_i2c_regs *regs = i2c_priv->regs;
326 u32 time_start = get_timer(0);
327
328 *status = readl(&regs->isr);
329 while (!(*status & flags)) {
330 if (get_timer(time_start) > CONFIG_SYS_HZ) {
331 debug("%s: i2c timeout\n", __func__);
332 return -ETIMEDOUT;
333 }
334
335 *status = readl(&regs->isr);
336 }
337
338 return 0;
339}
340
341static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
342{
343 struct stm32_i2c_regs *regs = i2c_priv->regs;
344 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
345 STM32_I2C_ISR_STOPF;
346 u32 status;
347 int ret;
348
349 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
350 if (ret)
351 return ret;
352
353 if (status & STM32_I2C_ISR_BERR) {
354 debug("%s: Bus error\n", __func__);
355
356 /* Clear BERR flag */
357 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
358
359 return -EIO;
360 }
361
362 if (status & STM32_I2C_ISR_ARLO) {
363 debug("%s: Arbitration lost\n", __func__);
364
365 /* Clear ARLO flag */
366 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
367
368 return -EAGAIN;
369 }
370
371 if (status & STM32_I2C_ISR_NACKF) {
372 debug("%s: Receive NACK\n", __func__);
373
374 /* Clear NACK flag */
375 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
376
377 /* Wait until STOPF flag is set */
378 mask = STM32_I2C_ISR_STOPF;
379 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
380 if (ret)
381 return ret;
382
383 ret = -EIO;
384 }
385
386 if (status & STM32_I2C_ISR_STOPF) {
387 /* Clear STOP flag */
388 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
389
390 /* Clear control register 2 */
391 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
392 }
393
394 return ret;
395}
396
397static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
398 struct i2c_msg *msg, bool stop)
399{
400 struct stm32_i2c_regs *regs = i2c_priv->regs;
401 u32 status;
402 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
403 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
404 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
405 STM32_I2C_MAX_LEN : msg->len;
406 int ret = 0;
407
408 /* Add errors */
409 mask |= STM32_I2C_ISR_ERRORS;
410
411 stm32_i2c_message_start(i2c_priv, msg, stop);
412
413 while (msg->len) {
414 /*
415 * Wait until TXIS/NACKF/BERR/ARLO flags or
416 * RXNE/BERR/ARLO flags are set
417 */
418 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
419 if (ret)
420 break;
421
422 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
423 break;
424
425 if (status & STM32_I2C_ISR_RXNE) {
426 *msg->buf++ = readb(&regs->rxdr);
427 msg->len--;
428 bytes_to_rw--;
429 }
430
431 if (status & STM32_I2C_ISR_TXIS) {
432 writeb(*msg->buf++, &regs->txdr);
433 msg->len--;
434 bytes_to_rw--;
435 }
436
437 if (!bytes_to_rw && msg->len) {
438 /* Wait until TCR flag is set */
439 mask = STM32_I2C_ISR_TCR;
440 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
441 if (ret)
442 break;
443
444 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
445 STM32_I2C_MAX_LEN : msg->len;
446 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
447 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
448
449 stm32_i2c_handle_reload(i2c_priv, msg, stop);
450 } else if (!bytes_to_rw) {
451 /* Wait until TC flag is set */
452 mask = STM32_I2C_ISR_TC;
453 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
454 if (ret)
455 break;
456
457 if (!stop)
458 /* Message sent, new message has to be sent */
459 return 0;
460 }
461 }
462
463 /* End of transfer, send stop condition */
464 mask = STM32_I2C_CR2_STOP;
465 setbits_le32(&regs->cr2, mask);
466
467 return stm32_i2c_check_end_of_message(i2c_priv);
468}
469
470static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
471 int nmsgs)
472{
473 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
474 int ret;
475
476 ret = stm32_i2c_check_device_busy(i2c_priv);
477 if (ret)
478 return ret;
479
480 for (; nmsgs > 0; nmsgs--, msg++) {
481 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
482 if (ret)
483 return ret;
484 }
485
486 return 0;
487}
488
489static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
490 struct list_head *solutions)
491{
492 struct stm32_i2c_timings *v;
493 u32 p_prev = STM32_PRESC_MAX;
494 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
495 setup->clock_src);
496 u32 af_delay_min, af_delay_max;
497 u16 p, l, a;
498 int sdadel_min, sdadel_max, scldel_min;
499 int ret = 0;
500
501 af_delay_min = setup->analog_filter ?
502 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
503 af_delay_max = setup->analog_filter ?
504 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
505
506 sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
507 af_delay_min - (setup->dnf + 3) * i2cclk;
508
509 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
510 af_delay_max - (setup->dnf + 4) * i2cclk;
511
512 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
513
514 if (sdadel_min < 0)
515 sdadel_min = 0;
516 if (sdadel_max < 0)
517 sdadel_max = 0;
518
519 debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
520 sdadel_min, sdadel_max, scldel_min);
521
522 /* Compute possible values for PRESC, SCLDEL and SDADEL */
523 for (p = 0; p < STM32_PRESC_MAX; p++) {
524 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
525 u32 scldel = (l + 1) * (p + 1) * i2cclk;
526
527 if (scldel < scldel_min)
528 continue;
529
530 for (a = 0; a < STM32_SDADEL_MAX; a++) {
531 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
532
533 if (((sdadel >= sdadel_min) &&
534 (sdadel <= sdadel_max)) &&
535 (p != p_prev)) {
536 v = kmalloc(sizeof(*v), GFP_KERNEL);
537 if (!v)
538 return -ENOMEM;
539
540 v->presc = p;
541 v->scldel = l;
542 v->sdadel = a;
543 p_prev = p;
544
545 list_add_tail(&v->node, solutions);
546 }
547 }
548 }
549 }
550
551 if (list_empty(solutions)) {
9b643e31 552 pr_err("%s: no Prescaler solution\n", __func__);
4fadcaf0
PC		 553 ret = -EPERM;
554 }
555
556 return ret;
557}
558
559static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
560 struct list_head *solutions,
561 struct stm32_i2c_timings *s)
562{
563 struct stm32_i2c_timings *v;
564 u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
565 setup->speed_freq);
566 u32 clk_error_prev = i2cbus;
567 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
568 setup->clock_src);
569 u32 clk_min, clk_max;
570 u32 af_delay_min;
571 u32 dnf_delay;
572 u32 tsync;
573 u16 l, h;
81c48437 574 bool sol_found = false;
4fadcaf0
PC		 575 int ret = 0;
576
577 af_delay_min = setup->analog_filter ?
578 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
579 dnf_delay = setup->dnf * i2cclk;
580
581 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
582 clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
583 clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
584
585 /*
586 * Among Prescaler possibilities discovered above figures out SCL Low
587 * and High Period. Provided:
588 * - SCL Low Period has to be higher than Low Period of the SCL Clock
589 * defined by I2C Specification. I2C Clock has to be lower than
590 * (SCL Low Period - Analog/Digital filters) / 4.
591 * - SCL High Period has to be lower than High Period of the SCL Clock
592 * defined by I2C Specification
593 * - I2C Clock has to be lower than SCL High Period
594 */
595 list_for_each_entry(v, solutions, node) {
596 u32 prescaler = (v->presc + 1) * i2cclk;
597
598 for (l = 0; l < STM32_SCLL_MAX; l++) {
599 u32 tscl_l = (l + 1) * prescaler + tsync;
600 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
601 (i2cclk >=
602 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
603 continue;
604 }
605
606 for (h = 0; h < STM32_SCLH_MAX; h++) {
607 u32 tscl_h = (h + 1) * prescaler + tsync;
608 u32 tscl = tscl_l + tscl_h +
609 setup->rise_time + setup->fall_time;
610
611 if ((tscl >= clk_min) && (tscl <= clk_max) &&
612 (tscl_h >= i2c_specs[setup->speed].h_min) &&
613 (i2cclk < tscl_h)) {
614 int clk_error = tscl - i2cbus;
615
616 if (clk_error < 0)
617 clk_error = -clk_error;
618
619 if (clk_error < clk_error_prev) {
620 clk_error_prev = clk_error;
621 v->scll = l;
622 v->sclh = h;
81c48437
CK		 623 sol_found = true;
624 memcpy(s, v, sizeof(*s));
4fadcaf0
PC		 625 }
626 }
627 }
628 }
629 }
630
81c48437 631 if (!sol_found) {
9b643e31 632 pr_err("%s: no solution at all\n", __func__);
4fadcaf0
PC		 633 ret = -EPERM;
634 }
635
636 return ret;
637}
638
639static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
640 struct stm32_i2c_setup *setup,
641 struct stm32_i2c_timings *output)
642{
d10bd6cf 643 struct stm32_i2c_timings *v, *_v;
4fadcaf0
PC		 644 struct list_head solutions;
645 int ret;
646
647 if (setup->speed >= STM32_I2C_SPEED_END) {
9b643e31 648 pr_err("%s: speed out of bound {%d/%d}\n", __func__,
4fadcaf0
PC		 649 setup->speed, STM32_I2C_SPEED_END - 1);
650 return -EINVAL;
651 }
652
653 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
654 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
9b643e31 655 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
4fadcaf0
PC		 656 __func__,
657 setup->rise_time, i2c_specs[setup->speed].rise_max,
658 setup->fall_time, i2c_specs[setup->speed].fall_max);
659 return -EINVAL;
660 }
661
662 if (setup->dnf > STM32_I2C_DNF_MAX) {
9b643e31 663 pr_err("%s: DNF out of bound %d/%d\n", __func__,
4fadcaf0
PC		 664 setup->dnf, STM32_I2C_DNF_MAX);
665 return -EINVAL;
666 }
667
668 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
9b643e31 669 pr_err("%s: Freq {%d/%d}\n", __func__,
4fadcaf0
PC		 670 setup->speed_freq, i2c_specs[setup->speed].rate);
671 return -EINVAL;
672 }
673
4fadcaf0
PC		 674 INIT_LIST_HEAD(&solutions);
675 ret = stm32_i2c_compute_solutions(setup, &solutions);
676 if (ret)
677 goto exit;
678
d10bd6cf 679 ret = stm32_i2c_choose_solution(setup, &solutions, output);
4fadcaf0
PC		 680 if (ret)
681 goto exit;
682
4fadcaf0
PC		 683 debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
684 __func__, output->presc,
685 output->scldel, output->sdadel,
686 output->scll, output->sclh);
687
688exit:
689 /* Release list and memory */
690 list_for_each_entry_safe(v, _v, &solutions, node) {
691 list_del(&v->node);
692 kfree(v);
693 }
694
695 return ret;
696}
697
698static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
699 struct stm32_i2c_timings *timing)
700{
701 struct stm32_i2c_setup *setup = i2c_priv->setup;
702 int ret = 0;
703
704 setup->speed = i2c_priv->speed;
705 setup->speed_freq = i2c_specs[setup->speed].rate;
706 setup->clock_src = clk_get_rate(&i2c_priv->clk);
707
708 if (!setup->clock_src) {
9b643e31 709 pr_err("%s: clock rate is 0\n", __func__);
4fadcaf0
PC		 710 return -EINVAL;
711 }
712
713 do {
714 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
715 if (ret) {
716 debug("%s: failed to compute I2C timings.\n",
717 __func__);
718 if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) {
719 i2c_priv->speed--;
720 setup->speed = i2c_priv->speed;
721 setup->speed_freq =
722 i2c_specs[setup->speed].rate;
723 debug("%s: downgrade I2C Speed Freq to (%i)\n",
724 __func__, i2c_specs[setup->speed].rate);
725 } else {
726 break;
727 }
728 }
729 } while (ret);
730
731 if (ret) {
9b643e31 732 pr_err("%s: impossible to compute I2C timings.\n", __func__);
4fadcaf0
PC		 733 return ret;
734 }
735
736 debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__,
737 setup->speed, setup->speed_freq, setup->clock_src);
738 debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
739 setup->rise_time, setup->fall_time);
740 debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
741 setup->analog_filter ? "On" : "Off", setup->dnf);
742
743 return 0;
744}
745
746static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
747{
748 struct stm32_i2c_regs *regs = i2c_priv->regs;
749 struct stm32_i2c_timings t;
750 int ret;
751 u32 timing = 0;
752
753 ret = stm32_i2c_setup_timing(i2c_priv, &t);
754 if (ret)
755 return ret;
756
757 /* Disable I2C */
758 clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
759
760 /* Timing settings */
761 timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
762 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
763 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
764 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
765 timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
766 writel(timing, &regs->timingr);
767
768 /* Enable I2C */
769 if (i2c_priv->setup->analog_filter)
770 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
771 else
772 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
773 setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
774
775 return 0;
776}
777
778static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
779{
780 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
781
782 switch (speed) {
783 case STANDARD_RATE:
784 i2c_priv->speed = STM32_I2C_SPEED_STANDARD;
785 break;
786 case FAST_RATE:
787 i2c_priv->speed = STM32_I2C_SPEED_FAST;
788 break;
789 case FAST_PLUS_RATE:
790 i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS;
791 break;
792 default:
793 debug("%s: Speed %d not supported\n", __func__, speed);
794 return -EINVAL;
795 }
796
797 return stm32_i2c_hw_config(i2c_priv);
798}
799
800static int stm32_i2c_probe(struct udevice *dev)
801{
802 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
803 struct reset_ctl reset_ctl;
804 fdt_addr_t addr;
805 int ret;
806
807 addr = dev_read_addr(dev);
808 if (addr == FDT_ADDR_T_NONE)
809 return -EINVAL;
810
811 i2c_priv->regs = (struct stm32_i2c_regs *)addr;
812
813 ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
814 if (ret)
815 return ret;
816
817 ret = clk_enable(&i2c_priv->clk);
818 if (ret)
819 goto clk_free;
820
821 ret = reset_get_by_index(dev, 0, &reset_ctl);
822 if (ret)
823 goto clk_disable;
824
825 reset_assert(&reset_ctl);
826 udelay(2);
827 reset_deassert(&reset_ctl);
828
829 return 0;
830
831clk_disable:
832 clk_disable(&i2c_priv->clk);
833clk_free:
834 clk_free(&i2c_priv->clk);
835
836 return ret;
837}
838
839static int stm32_ofdata_to_platdata(struct udevice *dev)
840{
841 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
842 u32 rise_time, fall_time;
843
844 i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
845 if (!i2c_priv->setup)
846 return -EINVAL;
847
848 rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
849 if (rise_time)
850 i2c_priv->setup->rise_time = rise_time;
851
852 fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
853 if (fall_time)
854 i2c_priv->setup->fall_time = fall_time;
855
856 return 0;
857}
858
859static const struct dm_i2c_ops stm32_i2c_ops = {
860 .xfer = stm32_i2c_xfer,
861 .set_bus_speed = stm32_i2c_set_bus_speed,
862};
863
864static const struct udevice_id stm32_i2c_of_match[] = {
865 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
866 {}
867};
868
869U_BOOT_DRIVER(stm32f7_i2c) = {
870 .name = "stm32f7-i2c",
871 .id = UCLASS_I2C,
872 .of_match = stm32_i2c_of_match,
873 .ofdata_to_platdata = stm32_ofdata_to_platdata,
874 .probe = stm32_i2c_probe,
875 .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
876 .ops = &stm32_i2c_ops,
877};
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