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96a78ac0 YL |
1 | /* |
2 | * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. | |
3 | * Copyright (c) 2010-2011 NVIDIA Corporation | |
4 | * NVIDIA Corporation <www.nvidia.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <fdtdec.h> | |
27 | #include <i2c.h> | |
28 | #include <asm/io.h> | |
96a78ac0 YL |
29 | #include <asm/arch/clock.h> |
30 | #include <asm/arch/funcmux.h> | |
31 | #include <asm/arch/gpio.h> | |
32 | #include <asm/arch/pinmux.h> | |
150c2493 TW |
33 | #include <asm/arch-tegra/clk_rst.h> |
34 | #include <asm/arch-tegra/tegra_i2c.h> | |
96a78ac0 YL |
35 | |
36 | DECLARE_GLOBAL_DATA_PTR; | |
37 | ||
96a78ac0 YL |
38 | /* Information about i2c controller */ |
39 | struct i2c_bus { | |
40 | int id; | |
41 | enum periph_id periph_id; | |
42 | int speed; | |
43 | int pinmux_config; | |
44 | struct i2c_control *control; | |
45 | struct i2c_ctlr *regs; | |
46 | int is_dvc; /* DVC type, rather than I2C */ | |
e32624ef | 47 | int is_scs; /* single clock source (T114+) */ |
96a78ac0 YL |
48 | int inited; /* bus is inited */ |
49 | }; | |
50 | ||
51 | static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS]; | |
52 | ||
53 | static void set_packet_mode(struct i2c_bus *i2c_bus) | |
54 | { | |
55 | u32 config; | |
56 | ||
57 | config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; | |
58 | ||
59 | if (i2c_bus->is_dvc) { | |
60 | struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; | |
61 | ||
62 | writel(config, &dvc->cnfg); | |
63 | } else { | |
64 | writel(config, &i2c_bus->regs->cnfg); | |
65 | /* | |
66 | * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe | |
67 | * issues, i.e., some slaves may be wrongly detected. | |
68 | */ | |
69 | setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); | |
70 | } | |
71 | } | |
72 | ||
73 | static void i2c_reset_controller(struct i2c_bus *i2c_bus) | |
74 | { | |
75 | /* Reset I2C controller. */ | |
76 | reset_periph(i2c_bus->periph_id, 1); | |
77 | ||
78 | /* re-program config register to packet mode */ | |
79 | set_packet_mode(i2c_bus); | |
80 | } | |
81 | ||
82 | static void i2c_init_controller(struct i2c_bus *i2c_bus) | |
83 | { | |
84 | /* | |
85 | * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 | |
86 | * here, in section 23.3.1, but in fact we seem to need a factor of | |
87 | * 16 to get the right frequency. | |
88 | */ | |
89 | clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, | |
e32624ef TW |
90 | i2c_bus->speed * 2 * 8); |
91 | ||
92 | if (i2c_bus->is_scs) { | |
93 | /* | |
94 | * T114 I2C went to a single clock source for standard/fast and | |
95 | * HS clock speeds. The new clock rate setting calculation is: | |
96 | * SCL = CLK_SOURCE.I2C / | |
97 | * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * | |
98 | * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). | |
99 | * | |
100 | * NOTE: We do this here, after the initial clock/pll start, | |
101 | * because if we read the clk_div reg before the controller | |
102 | * is running, we hang, and we need it for the new calc. | |
103 | */ | |
104 | int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; | |
105 | debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, | |
106 | clk_div_stdfst_mode); | |
107 | ||
108 | clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, | |
109 | CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * | |
110 | i2c_bus->speed * 2); | |
111 | } | |
96a78ac0 YL |
112 | |
113 | /* Reset I2C controller. */ | |
114 | i2c_reset_controller(i2c_bus); | |
115 | ||
116 | /* Configure I2C controller. */ | |
117 | if (i2c_bus->is_dvc) { /* only for DVC I2C */ | |
118 | struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; | |
119 | ||
120 | setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); | |
121 | } | |
122 | ||
123 | funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); | |
124 | } | |
125 | ||
126 | static void send_packet_headers( | |
127 | struct i2c_bus *i2c_bus, | |
128 | struct i2c_trans_info *trans, | |
129 | u32 packet_id) | |
130 | { | |
131 | u32 data; | |
132 | ||
133 | /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ | |
134 | data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; | |
135 | data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; | |
136 | data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; | |
137 | writel(data, &i2c_bus->control->tx_fifo); | |
138 | debug("pkt header 1 sent (0x%x)\n", data); | |
139 | ||
140 | /* prepare header2 */ | |
141 | data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; | |
142 | writel(data, &i2c_bus->control->tx_fifo); | |
143 | debug("pkt header 2 sent (0x%x)\n", data); | |
144 | ||
145 | /* prepare IO specific header: configure the slave address */ | |
146 | data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; | |
147 | ||
148 | /* Enable Read if it is not a write transaction */ | |
149 | if (!(trans->flags & I2C_IS_WRITE)) | |
150 | data |= PKT_HDR3_READ_MODE_MASK; | |
151 | ||
152 | /* Write I2C specific header */ | |
153 | writel(data, &i2c_bus->control->tx_fifo); | |
154 | debug("pkt header 3 sent (0x%x)\n", data); | |
155 | } | |
156 | ||
157 | static int wait_for_tx_fifo_empty(struct i2c_control *control) | |
158 | { | |
159 | u32 count; | |
160 | int timeout_us = I2C_TIMEOUT_USEC; | |
161 | ||
162 | while (timeout_us >= 0) { | |
163 | count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) | |
164 | >> TX_FIFO_EMPTY_CNT_SHIFT; | |
165 | if (count == I2C_FIFO_DEPTH) | |
166 | return 1; | |
167 | udelay(10); | |
168 | timeout_us -= 10; | |
169 | } | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | static int wait_for_rx_fifo_notempty(struct i2c_control *control) | |
175 | { | |
176 | u32 count; | |
177 | int timeout_us = I2C_TIMEOUT_USEC; | |
178 | ||
179 | while (timeout_us >= 0) { | |
180 | count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) | |
181 | >> TX_FIFO_FULL_CNT_SHIFT; | |
182 | if (count) | |
183 | return 1; | |
184 | udelay(10); | |
185 | timeout_us -= 10; | |
186 | } | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static int wait_for_transfer_complete(struct i2c_control *control) | |
192 | { | |
193 | int int_status; | |
194 | int timeout_us = I2C_TIMEOUT_USEC; | |
195 | ||
196 | while (timeout_us >= 0) { | |
197 | int_status = readl(&control->int_status); | |
198 | if (int_status & I2C_INT_NO_ACK_MASK) | |
199 | return -int_status; | |
200 | if (int_status & I2C_INT_ARBITRATION_LOST_MASK) | |
201 | return -int_status; | |
202 | if (int_status & I2C_INT_XFER_COMPLETE_MASK) | |
203 | return 0; | |
204 | ||
205 | udelay(10); | |
206 | timeout_us -= 10; | |
207 | } | |
208 | ||
209 | return -1; | |
210 | } | |
211 | ||
212 | static int send_recv_packets(struct i2c_bus *i2c_bus, | |
213 | struct i2c_trans_info *trans) | |
214 | { | |
215 | struct i2c_control *control = i2c_bus->control; | |
216 | u32 int_status; | |
217 | u32 words; | |
218 | u8 *dptr; | |
219 | u32 local; | |
220 | uchar last_bytes; | |
221 | int error = 0; | |
222 | int is_write = trans->flags & I2C_IS_WRITE; | |
223 | ||
224 | /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ | |
225 | int_status = readl(&control->int_status); | |
226 | writel(int_status, &control->int_status); | |
227 | ||
228 | send_packet_headers(i2c_bus, trans, 1); | |
229 | ||
230 | words = DIV_ROUND_UP(trans->num_bytes, 4); | |
231 | last_bytes = trans->num_bytes & 3; | |
232 | dptr = trans->buf; | |
233 | ||
234 | while (words) { | |
235 | u32 *wptr = (u32 *)dptr; | |
236 | ||
237 | if (is_write) { | |
238 | /* deal with word alignment */ | |
239 | if ((unsigned)dptr & 3) { | |
240 | memcpy(&local, dptr, sizeof(u32)); | |
241 | writel(local, &control->tx_fifo); | |
242 | debug("pkt data sent (0x%x)\n", local); | |
243 | } else { | |
244 | writel(*wptr, &control->tx_fifo); | |
245 | debug("pkt data sent (0x%x)\n", *wptr); | |
246 | } | |
247 | if (!wait_for_tx_fifo_empty(control)) { | |
248 | error = -1; | |
249 | goto exit; | |
250 | } | |
251 | } else { | |
252 | if (!wait_for_rx_fifo_notempty(control)) { | |
253 | error = -1; | |
254 | goto exit; | |
255 | } | |
256 | /* | |
257 | * for the last word, we read into our local buffer, | |
258 | * in case that caller did not provide enough buffer. | |
259 | */ | |
260 | local = readl(&control->rx_fifo); | |
261 | if ((words == 1) && last_bytes) | |
262 | memcpy(dptr, (char *)&local, last_bytes); | |
263 | else if ((unsigned)dptr & 3) | |
264 | memcpy(dptr, &local, sizeof(u32)); | |
265 | else | |
266 | *wptr = local; | |
267 | debug("pkt data received (0x%x)\n", local); | |
268 | } | |
269 | words--; | |
270 | dptr += sizeof(u32); | |
271 | } | |
272 | ||
273 | if (wait_for_transfer_complete(control)) { | |
274 | error = -1; | |
275 | goto exit; | |
276 | } | |
277 | return 0; | |
278 | exit: | |
279 | /* error, reset the controller. */ | |
280 | i2c_reset_controller(i2c_bus); | |
281 | ||
282 | return error; | |
283 | } | |
284 | ||
d84eb856 SG |
285 | static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data, |
286 | u32 len) | |
96a78ac0 YL |
287 | { |
288 | int error; | |
289 | struct i2c_trans_info trans_info; | |
290 | ||
291 | trans_info.address = addr; | |
292 | trans_info.buf = data; | |
293 | trans_info.flags = I2C_IS_WRITE; | |
294 | trans_info.num_bytes = len; | |
295 | trans_info.is_10bit_address = 0; | |
296 | ||
d84eb856 | 297 | error = send_recv_packets(bus, &trans_info); |
96a78ac0 | 298 | if (error) |
29f3e3f2 | 299 | debug("tegra_i2c_write_data: Error (%d) !!!\n", error); |
96a78ac0 YL |
300 | |
301 | return error; | |
302 | } | |
303 | ||
d84eb856 SG |
304 | static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data, |
305 | u32 len) | |
96a78ac0 YL |
306 | { |
307 | int error; | |
308 | struct i2c_trans_info trans_info; | |
309 | ||
310 | trans_info.address = addr | 1; | |
311 | trans_info.buf = data; | |
312 | trans_info.flags = 0; | |
313 | trans_info.num_bytes = len; | |
314 | trans_info.is_10bit_address = 0; | |
315 | ||
d84eb856 | 316 | error = send_recv_packets(bus, &trans_info); |
96a78ac0 | 317 | if (error) |
29f3e3f2 | 318 | debug("tegra_i2c_read_data: Error (%d) !!!\n", error); |
96a78ac0 YL |
319 | |
320 | return error; | |
321 | } | |
322 | ||
323 | #ifndef CONFIG_OF_CONTROL | |
324 | #error "Please enable device tree support to use this driver" | |
325 | #endif | |
326 | ||
d84eb856 SG |
327 | /** |
328 | * Check that a bus number is valid and return a pointer to it | |
329 | * | |
330 | * @param bus_num Bus number to check / return | |
331 | * @return pointer to bus, if valid, else NULL | |
332 | */ | |
1f2ba722 | 333 | static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap) |
d84eb856 SG |
334 | { |
335 | struct i2c_bus *bus; | |
336 | ||
1f2ba722 | 337 | bus = &i2c_controllers[adap->hwadapnr]; |
d84eb856 | 338 | if (!bus->inited) { |
1f2ba722 | 339 | debug("%s: Bus %u not available\n", __func__, adap->hwadapnr); |
d84eb856 SG |
340 | return NULL; |
341 | } | |
342 | ||
343 | return bus; | |
344 | } | |
345 | ||
1f2ba722 SG |
346 | static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap, |
347 | unsigned int speed) | |
96a78ac0 | 348 | { |
d84eb856 | 349 | struct i2c_bus *bus; |
96a78ac0 | 350 | |
1f2ba722 | 351 | bus = tegra_i2c_get_bus(adap); |
d84eb856 SG |
352 | if (!bus) |
353 | return 0; | |
354 | bus->speed = speed; | |
355 | i2c_init_controller(bus); | |
96a78ac0 YL |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
360 | static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) | |
361 | { | |
362 | i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg"); | |
363 | ||
364 | /* | |
365 | * We don't have a binding for pinmux yet. Leave it out for now. So | |
366 | * far no one needs anything other than the default. | |
367 | */ | |
368 | i2c_bus->pinmux_config = FUNCMUX_DEFAULT; | |
369 | i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0); | |
370 | i2c_bus->periph_id = clock_decode_periph_id(blob, node); | |
371 | ||
372 | /* | |
373 | * We can't specify the pinmux config in the fdt, so I2C2 will not | |
374 | * work on Seaboard. It normally has no devices on it anyway. | |
375 | * You could add in this little hack if you need to use it. | |
376 | * The correct solution is a pinmux binding in the fdt. | |
377 | * | |
378 | * if (i2c_bus->periph_id == PERIPH_ID_I2C2) | |
379 | * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; | |
380 | */ | |
381 | if (i2c_bus->periph_id == -1) | |
382 | return -FDT_ERR_NOTFOUND; | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | /* | |
388 | * Process a list of nodes, adding them to our list of I2C ports. | |
389 | * | |
390 | * @param blob fdt blob | |
391 | * @param node_list list of nodes to process (any <=0 are ignored) | |
392 | * @param count number of nodes to process | |
393 | * @param is_dvc 1 if these are DVC ports, 0 if standard I2C | |
e32624ef | 394 | * @param is_scs 1 if this HW uses a single clock source (T114+) |
96a78ac0 YL |
395 | * @return 0 if ok, -1 on error |
396 | */ | |
397 | static int process_nodes(const void *blob, int node_list[], int count, | |
e32624ef | 398 | int is_dvc, int is_scs) |
96a78ac0 YL |
399 | { |
400 | struct i2c_bus *i2c_bus; | |
401 | int i; | |
402 | ||
403 | /* build the i2c_controllers[] for each controller */ | |
404 | for (i = 0; i < count; i++) { | |
405 | int node = node_list[i]; | |
406 | ||
407 | if (node <= 0) | |
408 | continue; | |
409 | ||
410 | i2c_bus = &i2c_controllers[i]; | |
411 | i2c_bus->id = i; | |
412 | ||
413 | if (i2c_get_config(blob, node, i2c_bus)) { | |
414 | printf("i2c_init_board: failed to decode bus %d\n", i); | |
415 | return -1; | |
416 | } | |
417 | ||
e32624ef TW |
418 | i2c_bus->is_scs = is_scs; |
419 | ||
96a78ac0 YL |
420 | i2c_bus->is_dvc = is_dvc; |
421 | if (is_dvc) { | |
422 | i2c_bus->control = | |
423 | &((struct dvc_ctlr *)i2c_bus->regs)->control; | |
424 | } else { | |
425 | i2c_bus->control = &i2c_bus->regs->control; | |
426 | } | |
427 | debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", | |
428 | is_dvc ? "dvc" : "i2c", i, i2c_bus->regs, | |
429 | i2c_bus->periph_id, i2c_bus->speed); | |
430 | i2c_init_controller(i2c_bus); | |
431 | debug("ok\n"); | |
432 | i2c_bus->inited = 1; | |
433 | ||
434 | /* Mark position as used */ | |
435 | node_list[i] = -1; | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | /* Sadly there is no error return from this function */ | |
442 | void i2c_init_board(void) | |
443 | { | |
444 | int node_list[TEGRA_I2C_NUM_CONTROLLERS]; | |
445 | const void *blob = gd->fdt_blob; | |
446 | int count; | |
447 | ||
e32624ef TW |
448 | /* First check for newer (T114+) I2C ports */ |
449 | count = fdtdec_find_aliases_for_id(blob, "i2c", | |
450 | COMPAT_NVIDIA_TEGRA114_I2C, node_list, | |
451 | TEGRA_I2C_NUM_CONTROLLERS); | |
452 | if (process_nodes(blob, node_list, count, 0, 1)) | |
453 | return; | |
454 | ||
455 | /* Now get the older (T20/T30) normal I2C ports */ | |
96a78ac0 YL |
456 | count = fdtdec_find_aliases_for_id(blob, "i2c", |
457 | COMPAT_NVIDIA_TEGRA20_I2C, node_list, | |
458 | TEGRA_I2C_NUM_CONTROLLERS); | |
e32624ef | 459 | if (process_nodes(blob, node_list, count, 0, 0)) |
96a78ac0 YL |
460 | return; |
461 | ||
462 | /* Now look for dvc ports */ | |
463 | count = fdtdec_add_aliases_for_id(blob, "i2c", | |
464 | COMPAT_NVIDIA_TEGRA20_DVC, node_list, | |
465 | TEGRA_I2C_NUM_CONTROLLERS); | |
e32624ef | 466 | if (process_nodes(blob, node_list, count, 1, 0)) |
96a78ac0 YL |
467 | return; |
468 | } | |
469 | ||
1f2ba722 | 470 | static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) |
96a78ac0 YL |
471 | { |
472 | /* This will override the speed selected in the fdt for that port */ | |
473 | debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); | |
474 | i2c_set_bus_speed(speed); | |
475 | } | |
476 | ||
477 | /* i2c write version without the register address */ | |
d84eb856 | 478 | int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) |
96a78ac0 YL |
479 | { |
480 | int rc; | |
481 | ||
482 | debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); | |
483 | debug("write_data: "); | |
484 | /* use rc for counter */ | |
485 | for (rc = 0; rc < len; ++rc) | |
486 | debug(" 0x%02x", buffer[rc]); | |
487 | debug("\n"); | |
488 | ||
489 | /* Shift 7-bit address over for lower-level i2c functions */ | |
d84eb856 | 490 | rc = tegra_i2c_write_data(bus, chip << 1, buffer, len); |
96a78ac0 YL |
491 | if (rc) |
492 | debug("i2c_write_data(): rc=%d\n", rc); | |
493 | ||
494 | return rc; | |
495 | } | |
496 | ||
497 | /* i2c read version without the register address */ | |
d84eb856 | 498 | int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) |
96a78ac0 YL |
499 | { |
500 | int rc; | |
501 | ||
502 | debug("inside i2c_read_data():\n"); | |
503 | /* Shift 7-bit address over for lower-level i2c functions */ | |
d84eb856 | 504 | rc = tegra_i2c_read_data(bus, chip << 1, buffer, len); |
96a78ac0 YL |
505 | if (rc) { |
506 | debug("i2c_read_data(): rc=%d\n", rc); | |
507 | return rc; | |
508 | } | |
509 | ||
510 | debug("i2c_read_data: "); | |
511 | /* reuse rc for counter*/ | |
512 | for (rc = 0; rc < len; ++rc) | |
513 | debug(" 0x%02x", buffer[rc]); | |
514 | debug("\n"); | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | /* Probe to see if a chip is present. */ | |
1f2ba722 | 520 | static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip) |
96a78ac0 | 521 | { |
d84eb856 | 522 | struct i2c_bus *bus; |
96a78ac0 YL |
523 | int rc; |
524 | uchar reg; | |
525 | ||
526 | debug("i2c_probe: addr=0x%x\n", chip); | |
1f2ba722 | 527 | bus = tegra_i2c_get_bus(adap); |
d84eb856 SG |
528 | if (!bus) |
529 | return 1; | |
96a78ac0 | 530 | reg = 0; |
d84eb856 | 531 | rc = i2c_write_data(bus, chip, ®, 1); |
96a78ac0 YL |
532 | if (rc) { |
533 | debug("Error probing 0x%x.\n", chip); | |
534 | return 1; | |
535 | } | |
536 | return 0; | |
537 | } | |
538 | ||
539 | static int i2c_addr_ok(const uint addr, const int alen) | |
540 | { | |
541 | /* We support 7 or 10 bit addresses, so one or two bytes each */ | |
542 | return alen == 1 || alen == 2; | |
543 | } | |
544 | ||
545 | /* Read bytes */ | |
1f2ba722 SG |
546 | static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, |
547 | int alen, uchar *buffer, int len) | |
96a78ac0 | 548 | { |
d84eb856 | 549 | struct i2c_bus *bus; |
96a78ac0 YL |
550 | uint offset; |
551 | int i; | |
552 | ||
553 | debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n", | |
554 | chip, addr, len); | |
1f2ba722 | 555 | bus = tegra_i2c_get_bus(adap); |
d84eb856 SG |
556 | if (!bus) |
557 | return 1; | |
96a78ac0 YL |
558 | if (!i2c_addr_ok(addr, alen)) { |
559 | debug("i2c_read: Bad address %x.%d.\n", addr, alen); | |
560 | return 1; | |
561 | } | |
562 | for (offset = 0; offset < len; offset++) { | |
563 | if (alen) { | |
564 | uchar data[alen]; | |
565 | for (i = 0; i < alen; i++) { | |
566 | data[alen - i - 1] = | |
567 | (addr + offset) >> (8 * i); | |
568 | } | |
d84eb856 | 569 | if (i2c_write_data(bus, chip, data, alen)) { |
96a78ac0 YL |
570 | debug("i2c_read: error sending (0x%x)\n", |
571 | addr); | |
572 | return 1; | |
573 | } | |
574 | } | |
d84eb856 | 575 | if (i2c_read_data(bus, chip, buffer + offset, 1)) { |
96a78ac0 YL |
576 | debug("i2c_read: error reading (0x%x)\n", addr); |
577 | return 1; | |
578 | } | |
579 | } | |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
584 | /* Write bytes */ | |
1f2ba722 SG |
585 | static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, |
586 | int alen, uchar *buffer, int len) | |
96a78ac0 | 587 | { |
d84eb856 | 588 | struct i2c_bus *bus; |
96a78ac0 YL |
589 | uint offset; |
590 | int i; | |
591 | ||
592 | debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n", | |
593 | chip, addr, len); | |
1f2ba722 | 594 | bus = tegra_i2c_get_bus(adap); |
d84eb856 SG |
595 | if (!bus) |
596 | return 1; | |
96a78ac0 YL |
597 | if (!i2c_addr_ok(addr, alen)) { |
598 | debug("i2c_write: Bad address %x.%d.\n", addr, alen); | |
599 | return 1; | |
600 | } | |
601 | for (offset = 0; offset < len; offset++) { | |
602 | uchar data[alen + 1]; | |
603 | for (i = 0; i < alen; i++) | |
604 | data[alen - i - 1] = (addr + offset) >> (8 * i); | |
605 | data[alen] = buffer[offset]; | |
d84eb856 | 606 | if (i2c_write_data(bus, chip, data, alen + 1)) { |
96a78ac0 YL |
607 | debug("i2c_write: error sending (0x%x)\n", addr); |
608 | return 1; | |
609 | } | |
610 | } | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
e31c1e50 SG |
615 | int tegra_i2c_get_dvc_bus_num(void) |
616 | { | |
617 | int i; | |
618 | ||
1f2ba722 | 619 | for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) { |
e31c1e50 SG |
620 | struct i2c_bus *bus = &i2c_controllers[i]; |
621 | ||
622 | if (bus->inited && bus->is_dvc) | |
623 | return i; | |
624 | } | |
625 | ||
626 | return -1; | |
627 | } | |
1f2ba722 SG |
628 | |
629 | /* | |
630 | * Register soft i2c adapters | |
631 | */ | |
632 | U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe, | |
633 | tegra_i2c_read, tegra_i2c_write, | |
634 | tegra_i2c_set_bus_speed, 100000, 0, 0) | |
635 | U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe, | |
636 | tegra_i2c_read, tegra_i2c_write, | |
637 | tegra_i2c_set_bus_speed, 100000, 0, 1) | |
638 | U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe, | |
639 | tegra_i2c_read, tegra_i2c_write, | |
640 | tegra_i2c_set_bus_speed, 100000, 0, 2) | |
641 | U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe, | |
642 | tegra_i2c_read, tegra_i2c_write, | |
643 | tegra_i2c_set_bus_speed, 100000, 0, 3) |