[people/ms/u-boot.git] / drivers / i2c / tegra_i2c.c

/*
 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
 * Copyright (c) 2010-2011 NVIDIA Corporation
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/tegra_i2c.h>

DECLARE_GLOBAL_DATA_PTR;

/* Information about i2c controller */
struct i2c_bus {
	int			id;
	enum periph_id		periph_id;
	int			speed;
	int			pinmux_config;
	struct i2c_control	*control;
	struct i2c_ctlr		*regs;
	int			is_dvc;	/* DVC type, rather than I2C */
	int			is_scs;	/* single clock source (T114+) */
	int			inited;	/* bus is inited */
};

static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];

static void set_packet_mode(struct i2c_bus *i2c_bus)
{
	u32 config;

	config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;

	if (i2c_bus->is_dvc) {
		struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;

		writel(config, &dvc->cnfg);
	} else {
		writel(config, &i2c_bus->regs->cnfg);
		/*
		 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
		 * issues, i.e., some slaves may be wrongly detected.
		 */
		setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
	}
}

static void i2c_reset_controller(struct i2c_bus *i2c_bus)
{
	/* Reset I2C controller. */
	reset_periph(i2c_bus->periph_id, 1);

	/* re-program config register to packet mode */
	set_packet_mode(i2c_bus);
}

static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
	/*
	 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
	 * here, in section 23.3.1, but in fact we seem to need a factor of
	 * 16 to get the right frequency.
	 */
	clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
		i2c_bus->speed * 2 * 8);

	if (i2c_bus->is_scs) {
		/*
		 * T114 I2C went to a single clock source for standard/fast and
		 * HS clock speeds. The new clock rate setting calculation is:
		 *  SCL = CLK_SOURCE.I2C /
		 *   (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
		 *   I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
		 *
		 * NOTE: We do this here, after the initial clock/pll start,
		 * because if we read the clk_div reg before the controller
		 * is running, we hang, and we need it for the new calc.
		 */
		int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
		debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
			clk_div_stdfst_mode);

		clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
			CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
			i2c_bus->speed * 2);
	}

	/* Reset I2C controller. */
	i2c_reset_controller(i2c_bus);

	/* Configure I2C controller. */
	if (i2c_bus->is_dvc) {	/* only for DVC I2C */
		struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;

		setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
	}

	funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
}

static void send_packet_headers(
	struct i2c_bus *i2c_bus,
	struct i2c_trans_info *trans,
	u32 packet_id,
	bool end_with_repeated_start)
{
	u32 data;

	/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
	data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
	data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
	data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 1 sent (0x%x)\n", data);

	/* prepare header2 */
	data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 2 sent (0x%x)\n", data);

	/* prepare IO specific header: configure the slave address */
	data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;

	/* Enable Read if it is not a write transaction */
	if (!(trans->flags & I2C_IS_WRITE))
		data |= PKT_HDR3_READ_MODE_MASK;
	if (end_with_repeated_start)
		data |= PKT_HDR3_REPEAT_START_MASK;

	/* Write I2C specific header */
	writel(data, &i2c_bus->control->tx_fifo);
	debug("pkt header 3 sent (0x%x)\n", data);
}

static int wait_for_tx_fifo_empty(struct i2c_control *control)
{
	u32 count;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
				>> TX_FIFO_EMPTY_CNT_SHIFT;
		if (count == I2C_FIFO_DEPTH)
			return 1;
		udelay(10);
		timeout_us -= 10;
	}

	return 0;
}

static int wait_for_rx_fifo_notempty(struct i2c_control *control)
{
	u32 count;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
				>> TX_FIFO_FULL_CNT_SHIFT;
		if (count)
			return 1;
		udelay(10);
		timeout_us -= 10;
	}

	return 0;
}

static int wait_for_transfer_complete(struct i2c_control *control)
{
	int int_status;
	int timeout_us = I2C_TIMEOUT_USEC;

	while (timeout_us >= 0) {
		int_status = readl(&control->int_status);
		if (int_status & I2C_INT_NO_ACK_MASK)
			return -int_status;
		if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
			return -int_status;
		if (int_status & I2C_INT_XFER_COMPLETE_MASK)
			return 0;

		udelay(10);
		timeout_us -= 10;
	}

	return -1;
}

static int send_recv_packets(struct i2c_bus *i2c_bus,
			     struct i2c_trans_info *trans)
{
	struct i2c_control *control = i2c_bus->control;
	u32 int_status;
	u32 words;
	u8 *dptr;
	u32 local;
	uchar last_bytes;
	int error = 0;
	int is_write = trans->flags & I2C_IS_WRITE;

	/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
	int_status = readl(&control->int_status);
	writel(int_status, &control->int_status);

	send_packet_headers(i2c_bus, trans, 1,
			    trans->flags & I2C_USE_REPEATED_START);

	words = DIV_ROUND_UP(trans->num_bytes, 4);
	last_bytes = trans->num_bytes & 3;
	dptr = trans->buf;

	while (words) {
		u32 *wptr = (u32 *)dptr;

		if (is_write) {
			/* deal with word alignment */
			if ((words == 1) && last_bytes) {
				local = 0;
				memcpy(&local, dptr, last_bytes);
			} else if ((unsigned)dptr & 3) {
				memcpy(&local, dptr, sizeof(u32));
			} else {
				local = *wptr;
			}
			writel(local, &control->tx_fifo);
			debug("pkt data sent (0x%x)\n", local);
			if (!wait_for_tx_fifo_empty(control)) {
				error = -1;
				goto exit;
			}
		} else {
			if (!wait_for_rx_fifo_notempty(control)) {
				error = -1;
				goto exit;
			}
			/*
			 * for the last word, we read into our local buffer,
			 * in case that caller did not provide enough buffer.
			 */
			local = readl(&control->rx_fifo);
			if ((words == 1) && last_bytes)
				memcpy(dptr, (char *)&local, last_bytes);
			else if ((unsigned)dptr & 3)
				memcpy(dptr, &local, sizeof(u32));
			else
				*wptr = local;
			debug("pkt data received (0x%x)\n", local);
		}
		words--;
		dptr += sizeof(u32);
	}

	if (wait_for_transfer_complete(control)) {
		error = -1;
		goto exit;
	}
	return 0;
exit:
	/* error, reset the controller. */
	i2c_reset_controller(i2c_bus);

	return error;
}

static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
				u32 len, bool end_with_repeated_start)
{
	int error;
	struct i2c_trans_info trans_info;

	trans_info.address = addr;
	trans_info.buf = data;
	trans_info.flags = I2C_IS_WRITE;
	if (end_with_repeated_start)
		trans_info.flags |= I2C_USE_REPEATED_START;
	trans_info.num_bytes = len;
	trans_info.is_10bit_address = 0;

	error = send_recv_packets(bus, &trans_info);
	if (error)
		debug("tegra_i2c_write_data: Error (%d) !!!\n", error);

	return error;
}

static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data,
			       u32 len)
{
	int error;
	struct i2c_trans_info trans_info;

	trans_info.address = addr | 1;
	trans_info.buf = data;
	trans_info.flags = 0;
	trans_info.num_bytes = len;
	trans_info.is_10bit_address = 0;

	error = send_recv_packets(bus, &trans_info);
	if (error)
		debug("tegra_i2c_read_data: Error (%d) !!!\n", error);

	return error;
}

#ifndef CONFIG_OF_CONTROL
#error "Please enable device tree support to use this driver"
#endif

/**
 * Check that a bus number is valid and return a pointer to it
 *
 * @param bus_num	Bus number to check / return
 * @return pointer to bus, if valid, else NULL
 */
static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap)
{
	struct i2c_bus *bus;

	bus = &i2c_controllers[adap->hwadapnr];
	if (!bus->inited) {
		debug("%s: Bus %u not available\n", __func__, adap->hwadapnr);
		return NULL;
	}

	return bus;
}

static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap,
			unsigned int speed)
{
	struct i2c_bus *bus;

	bus = tegra_i2c_get_bus(adap);
	if (!bus)
		return 0;
	bus->speed = speed;
	i2c_init_controller(bus);

	return 0;
}

static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
{
	i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");

	/*
	 * We don't have a binding for pinmux yet. Leave it out for now. So
	 * far no one needs anything other than the default.
	 */
	i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
	i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
	i2c_bus->periph_id = clock_decode_periph_id(blob, node);

	/*
	 * We can't specify the pinmux config in the fdt, so I2C2 will not
	 * work on Seaboard. It normally has no devices on it anyway.
	 * You could add in this little hack if you need to use it.
	 * The correct solution is a pinmux binding in the fdt.
	 *
	 *	if (i2c_bus->periph_id == PERIPH_ID_I2C2)
	 *		i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
	 */
	if (i2c_bus->periph_id == -1)
		return -FDT_ERR_NOTFOUND;

	return 0;
}

/*
 * Process a list of nodes, adding them to our list of I2C ports.
 *
 * @param blob		fdt blob
 * @param node_list	list of nodes to process (any <=0 are ignored)
 * @param count		number of nodes to process
 * @param is_dvc	1 if these are DVC ports, 0 if standard I2C
 * @param is_scs	1 if this HW uses a single clock source (T114+)
 * @return 0 if ok, -1 on error
 */
static int process_nodes(const void *blob, int node_list[], int count,
			 int is_dvc, int is_scs)
{
	struct i2c_bus *i2c_bus;
	int i;

	/* build the i2c_controllers[] for each controller */
	for (i = 0; i < count; i++) {
		int node = node_list[i];

		if (node <= 0)
			continue;

		i2c_bus = &i2c_controllers[i];
		i2c_bus->id = i;

		if (i2c_get_config(blob, node, i2c_bus)) {
			printf("i2c_init_board: failed to decode bus %d\n", i);
			return -1;
		}

		i2c_bus->is_scs = is_scs;

		i2c_bus->is_dvc = is_dvc;
		if (is_dvc) {
			i2c_bus->control =
				&((struct dvc_ctlr *)i2c_bus->regs)->control;
		} else {
			i2c_bus->control = &i2c_bus->regs->control;
		}
		debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
		      is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
		      i2c_bus->periph_id, i2c_bus->speed);
		i2c_init_controller(i2c_bus);
		debug("ok\n");
		i2c_bus->inited = 1;

		/* Mark position as used */
		node_list[i] = -1;
	}

	return 0;
}

/* Sadly there is no error return from this function */
void i2c_init_board(void)
{
	int node_list[TEGRA_I2C_NUM_CONTROLLERS];
	const void *blob = gd->fdt_blob;
	int count;

	/* First check for newer (T114+) I2C ports */
	count = fdtdec_find_aliases_for_id(blob, "i2c",
			COMPAT_NVIDIA_TEGRA114_I2C, node_list,
			TEGRA_I2C_NUM_CONTROLLERS);
	if (process_nodes(blob, node_list, count, 0, 1))
		return;

	/* Now get the older (T20/T30) normal I2C ports */
	count = fdtdec_find_aliases_for_id(blob, "i2c",
			COMPAT_NVIDIA_TEGRA20_I2C, node_list,
			TEGRA_I2C_NUM_CONTROLLERS);
	if (process_nodes(blob, node_list, count, 0, 0))
		return;

	/* Now look for dvc ports */
	count = fdtdec_add_aliases_for_id(blob, "i2c",
			COMPAT_NVIDIA_TEGRA20_DVC, node_list,
			TEGRA_I2C_NUM_CONTROLLERS);
	if (process_nodes(blob, node_list, count, 1, 0))
		return;
}

static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	/* No i2c support prior to relocation */
	if (!(gd->flags & GD_FLG_RELOC))
		return;

	/* This will override the speed selected in the fdt for that port */
	debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
	i2c_set_bus_speed(speed);
}

/* i2c write version without the register address */
static int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
			  int len, bool end_with_repeated_start)
{
	int rc;

	debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
	debug("write_data: ");
	/* use rc for counter */
	for (rc = 0; rc < len; ++rc)
		debug(" 0x%02x", buffer[rc]);
	debug("\n");

	/* Shift 7-bit address over for lower-level i2c functions */
	rc = tegra_i2c_write_data(bus, chip << 1, buffer, len,
				  end_with_repeated_start);
	if (rc)
		debug("i2c_write_data(): rc=%d\n", rc);

	return rc;
}

/* i2c read version without the register address */
static int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
				int len)
{
	int rc;

	debug("inside i2c_read_data():\n");
	/* Shift 7-bit address over for lower-level i2c functions */
	rc = tegra_i2c_read_data(bus, chip << 1, buffer, len);
	if (rc) {
		debug("i2c_read_data(): rc=%d\n", rc);
		return rc;
	}

	debug("i2c_read_data: ");
	/* reuse rc for counter*/
	for (rc = 0; rc < len; ++rc)
		debug(" 0x%02x", buffer[rc]);
	debug("\n");

	return 0;
}

/* Probe to see if a chip is present. */
static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
	struct i2c_bus *bus;
	int rc;
	uchar reg;

	debug("i2c_probe: addr=0x%x\n", chip);
	bus = tegra_i2c_get_bus(adap);
	if (!bus)
		return 1;
	reg = 0;
	rc = i2c_write_data(bus, chip, &reg, 1, false);
	if (rc) {
		debug("Error probing 0x%x.\n", chip);
		return 1;
	}
	return 0;
}

static int i2c_addr_ok(const uint addr, const int alen)
{
	/* We support 7 or 10 bit addresses, so one or two bytes each */
	return alen == 1 || alen == 2;
}

/* Read bytes */
static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
			int alen, uchar *buffer, int len)
{
	struct i2c_bus *bus;
	uint offset;
	int i;

	debug("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
	      chip, addr, alen, len);
	bus = tegra_i2c_get_bus(adap);
	if (!bus)
		return 1;
	if (!i2c_addr_ok(addr, alen)) {
		debug("i2c_read: Bad address %x.%d.\n", addr, alen);
		return 1;
	}
	for (offset = 0; offset < len; offset++) {
		if (alen) {
			uchar data[alen];
			for (i = 0; i < alen; i++) {
				data[alen - i - 1] =
					(addr + offset) >> (8 * i);
			}
			if (i2c_write_data(bus, chip, data, alen, true)) {
				debug("i2c_read: error sending (0x%x)\n",
					addr);
				return 1;
			}
		}
		if (i2c_read_data(bus, chip, buffer + offset, 1)) {
			debug("i2c_read: error reading (0x%x)\n", addr);
			return 1;
		}
	}

	return 0;
}

/* Write bytes */
static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
			int alen, uchar *buffer, int len)
{
	struct i2c_bus *bus;
	uint offset;
	int i;

	debug("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
	      chip, addr, alen, len);
	bus = tegra_i2c_get_bus(adap);
	if (!bus)
		return 1;
	if (!i2c_addr_ok(addr, alen)) {
		debug("i2c_write: Bad address %x.%d.\n", addr, alen);
		return 1;
	}
	for (offset = 0; offset < len; offset++) {
		uchar data[alen + 1];
		for (i = 0; i < alen; i++)
			data[alen - i - 1] = (addr + offset) >> (8 * i);
		data[alen] = buffer[offset];
		if (i2c_write_data(bus, chip, data, alen + 1, false)) {
			debug("i2c_write: error sending (0x%x)\n", addr);
			return 1;
		}
	}

	return 0;
}

int tegra_i2c_get_dvc_bus_num(void)
{
	int i;

	for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) {
		struct i2c_bus *bus = &i2c_controllers[i];

		if (bus->inited && bus->is_dvc)
			return i;
	}

	return -1;
}

/*
 * Register soft i2c adapters
 */
U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe,
			 tegra_i2c_read, tegra_i2c_write,
			 tegra_i2c_set_bus_speed, 100000, 0, 0)
U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe,
			 tegra_i2c_read, tegra_i2c_write,
			 tegra_i2c_set_bus_speed, 100000, 0, 1)
U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
			 tegra_i2c_read, tegra_i2c_write,
			 tegra_i2c_set_bus_speed, 100000, 0, 2)
U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
			 tegra_i2c_read, tegra_i2c_write,
			 tegra_i2c_set_bus_speed, 100000, 0, 3)
#if TEGRA_I2C_NUM_CONTROLLERS > 4
U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe,
			 tegra_i2c_read, tegra_i2c_write,
			 tegra_i2c_set_bus_speed, 100000, 0, 4)
#endif
Commit	Line	Data
96a78ac0 YL	1	/*
	2	* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
	3	* Copyright (c) 2010-2011 NVIDIA Corporation
	4	* NVIDIA Corporation <www.nvidia.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
96a78ac0 YL	7	*/
	8
	9	#include <common.h>
	10	#include <fdtdec.h>
	11	#include <i2c.h>
	12	#include <asm/io.h>
96a78ac0 YL	13	#include <asm/arch/clock.h>
	14	#include <asm/arch/funcmux.h>
	15	#include <asm/arch/gpio.h>
	16	#include <asm/arch/pinmux.h>
150c2493 TW	17	#include <asm/arch-tegra/clk_rst.h>
150c2493 TW	18	#include <asm/arch-tegra/tegra_i2c.h>
96a78ac0 YL	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
96a78ac0 YL	22	/* Information about i2c controller */
	23	struct i2c_bus {
	24	int id;
	25	enum periph_id periph_id;
	26	int speed;
	27	int pinmux_config;
	28	struct i2c_control *control;
	29	struct i2c_ctlr *regs;
	30	int is_dvc; /* DVC type, rather than I2C */
e32624ef	31	int is_scs; /* single clock source (T114+) */
96a78ac0 YL	32	int inited; /* bus is inited */
	33	};
	34
	35	static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
	36
	37	static void set_packet_mode(struct i2c_bus *i2c_bus)
	38	{
	39	u32 config;
	40
	41	config = I2C_CNFG_NEW_MASTER_FSM_MASK \| I2C_CNFG_PACKET_MODE_MASK;
	42
	43	if (i2c_bus->is_dvc) {
	44	struct dvc_ctlr dvc = (struct dvc_ctlr )i2c_bus->regs;
	45
	46	writel(config, &dvc->cnfg);
	47	} else {
	48	writel(config, &i2c_bus->regs->cnfg);
	49	/*
	50	* program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
	51	* issues, i.e., some slaves may be wrongly detected.
	52	*/
	53	setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
	54	}
	55	}
	56
	57	static void i2c_reset_controller(struct i2c_bus *i2c_bus)
	58	{
	59	/* Reset I2C controller. */
	60	reset_periph(i2c_bus->periph_id, 1);
	61
	62	/* re-program config register to packet mode */
	63	set_packet_mode(i2c_bus);
	64	}
	65
	66	static void i2c_init_controller(struct i2c_bus *i2c_bus)
	67	{
	68	/*
	69	* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
	70	* here, in section 23.3.1, but in fact we seem to need a factor of
	71	* 16 to get the right frequency.
	72	*/
	73	clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
e32624ef TW	74	i2c_bus->speed * 2 * 8);
	75
	76	if (i2c_bus->is_scs) {
	77	/*
	78	* T114 I2C went to a single clock source for standard/fast and
	79	* HS clock speeds. The new clock rate setting calculation is:
	80	* SCL = CLK_SOURCE.I2C /
	81	* (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
	82	* I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
	83	*
	84	* NOTE: We do this here, after the initial clock/pll start,
	85	* because if we read the clk_div reg before the controller
	86	* is running, we hang, and we need it for the new calc.
	87	*/
	88	int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
	89	debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
	90	clk_div_stdfst_mode);
	91
	92	clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
	93	CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
	94	i2c_bus->speed * 2);
	95	}
96a78ac0 YL	96
	97	/* Reset I2C controller. */
	98	i2c_reset_controller(i2c_bus);
	99
	100	/* Configure I2C controller. */
	101	if (i2c_bus->is_dvc) { /* only for DVC I2C */
	102	struct dvc_ctlr dvc = (struct dvc_ctlr )i2c_bus->regs;
	103
	104	setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
	105	}
	106
	107	funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
	108	}
	109
	110	static void send_packet_headers(
	111	struct i2c_bus *i2c_bus,
	112	struct i2c_trans_info *trans,
68049a08 SW	113	u32 packet_id,
68049a08 SW	114	bool end_with_repeated_start)
96a78ac0 YL	115	{
	116	u32 data;
	117
	118	/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
	119	data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
	120	data \|= packet_id << PKT_HDR1_PKT_ID_SHIFT;
	121	data \|= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
	122	writel(data, &i2c_bus->control->tx_fifo);
	123	debug("pkt header 1 sent (0x%x)\n", data);
	124
	125	/* prepare header2 */
	126	data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
	127	writel(data, &i2c_bus->control->tx_fifo);
	128	debug("pkt header 2 sent (0x%x)\n", data);
	129
	130	/* prepare IO specific header: configure the slave address */
	131	data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
	132
	133	/* Enable Read if it is not a write transaction */
	134	if (!(trans->flags & I2C_IS_WRITE))
	135	data \|= PKT_HDR3_READ_MODE_MASK;
68049a08 SW	136	if (end_with_repeated_start)
68049a08 SW	137	data \|= PKT_HDR3_REPEAT_START_MASK;
96a78ac0 YL	138
	139	/* Write I2C specific header */
	140	writel(data, &i2c_bus->control->tx_fifo);
	141	debug("pkt header 3 sent (0x%x)\n", data);
	142	}
	143
	144	static int wait_for_tx_fifo_empty(struct i2c_control *control)
	145	{
	146	u32 count;
	147	int timeout_us = I2C_TIMEOUT_USEC;
	148
	149	while (timeout_us >= 0) {
	150	count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
	151	>> TX_FIFO_EMPTY_CNT_SHIFT;
	152	if (count == I2C_FIFO_DEPTH)
	153	return 1;
	154	udelay(10);
	155	timeout_us -= 10;
	156	}
	157
	158	return 0;
	159	}
	160
	161	static int wait_for_rx_fifo_notempty(struct i2c_control *control)
	162	{
	163	u32 count;
	164	int timeout_us = I2C_TIMEOUT_USEC;
	165
	166	while (timeout_us >= 0) {
	167	count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
	168	>> TX_FIFO_FULL_CNT_SHIFT;
	169	if (count)
	170	return 1;
	171	udelay(10);
	172	timeout_us -= 10;
	173	}
	174
	175	return 0;
	176	}
	177
	178	static int wait_for_transfer_complete(struct i2c_control *control)
	179	{
	180	int int_status;
	181	int timeout_us = I2C_TIMEOUT_USEC;
	182
	183	while (timeout_us >= 0) {
	184	int_status = readl(&control->int_status);
	185	if (int_status & I2C_INT_NO_ACK_MASK)
	186	return -int_status;
	187	if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
	188	return -int_status;
	189	if (int_status & I2C_INT_XFER_COMPLETE_MASK)
	190	return 0;
	191
	192	udelay(10);
	193	timeout_us -= 10;
	194	}
	195
	196	return -1;
	197	}
	198
	199	static int send_recv_packets(struct i2c_bus *i2c_bus,
	200	struct i2c_trans_info *trans)
	201	{
202	struct i2c_control *control = i2c_bus->control;
203	u32 int_status;
204	u32 words;
205	u8 *dptr;
206	u32 local;
207	uchar last_bytes;
208	int error = 0;
209	int is_write = trans->flags & I2C_IS_WRITE;
210
211	/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
212	int_status = readl(&control->int_status);
213	writel(int_status, &control->int_status);
214
68049a08 SW	215	send_packet_headers(i2c_bus, trans, 1,
68049a08 SW	216	trans->flags & I2C_USE_REPEATED_START);
96a78ac0 YL	217
	218	words = DIV_ROUND_UP(trans->num_bytes, 4);
	219	last_bytes = trans->num_bytes & 3;
	220	dptr = trans->buf;
	221
	222	while (words) {
	223	u32 wptr = (u32 )dptr;
	224
	225	if (is_write) {
	226	/* deal with word alignment */
981b14f0 SW	227	if ((words == 1) && last_bytes) {
	228	local = 0;
	229	memcpy(&local, dptr, last_bytes);
	230	} else if ((unsigned)dptr & 3) {
96a78ac0	231	memcpy(&local, dptr, sizeof(u32));
96a78ac0	232	} else {
981b14f0	233	local = *wptr;
96a78ac0	234	}
981b14f0 SW	235	writel(local, &control->tx_fifo);
981b14f0 SW	236	debug("pkt data sent (0x%x)\n", local);
96a78ac0 YL	237	if (!wait_for_tx_fifo_empty(control)) {
	238	error = -1;
	239	goto exit;
	240	}
	241	} else {
	242	if (!wait_for_rx_fifo_notempty(control)) {
	243	error = -1;
	244	goto exit;
	245	}
	246	/*
	247	* for the last word, we read into our local buffer,
	248	* in case that caller did not provide enough buffer.
	249	*/
	250	local = readl(&control->rx_fifo);
	251	if ((words == 1) && last_bytes)
	252	memcpy(dptr, (char *)&local, last_bytes);
	253	else if ((unsigned)dptr & 3)
	254	memcpy(dptr, &local, sizeof(u32));
	255	else
	256	*wptr = local;
	257	debug("pkt data received (0x%x)\n", local);
	258	}
	259	words--;
	260	dptr += sizeof(u32);
	261	}
	262
	263	if (wait_for_transfer_complete(control)) {
	264	error = -1;
	265	goto exit;
	266	}
	267	return 0;
	268	exit:
	269	/* error, reset the controller. */
	270	i2c_reset_controller(i2c_bus);
	271
	272	return error;
	273	}
	274
d84eb856	275	static int tegra_i2c_write_data(struct i2c_bus bus, u32 addr, u8 data,
68049a08	276	u32 len, bool end_with_repeated_start)
96a78ac0 YL	277	{
	278	int error;
	279	struct i2c_trans_info trans_info;
	280
	281	trans_info.address = addr;
	282	trans_info.buf = data;
	283	trans_info.flags = I2C_IS_WRITE;
68049a08 SW	284	if (end_with_repeated_start)
68049a08 SW	285	trans_info.flags \|= I2C_USE_REPEATED_START;
96a78ac0 YL	286	trans_info.num_bytes = len;
	287	trans_info.is_10bit_address = 0;
	288
d84eb856	289	error = send_recv_packets(bus, &trans_info);
96a78ac0	290	if (error)
29f3e3f2	291	debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
96a78ac0 YL	292
	293	return error;
	294	}
	295
d84eb856 SG	296	static int tegra_i2c_read_data(struct i2c_bus bus, u32 addr, u8 data,
d84eb856 SG	297	u32 len)
96a78ac0 YL	298	{
	299	int error;
	300	struct i2c_trans_info trans_info;
	301
	302	trans_info.address = addr \| 1;
	303	trans_info.buf = data;
	304	trans_info.flags = 0;
	305	trans_info.num_bytes = len;
	306	trans_info.is_10bit_address = 0;
	307
d84eb856	308	error = send_recv_packets(bus, &trans_info);
96a78ac0	309	if (error)
29f3e3f2	310	debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
96a78ac0 YL	311
	312	return error;
	313	}
	314
	315	#ifndef CONFIG_OF_CONTROL
	316	#error "Please enable device tree support to use this driver"
	317	#endif
	318
d84eb856 SG	319	/**
	320	* Check that a bus number is valid and return a pointer to it
	321	*
	322	* @param bus_num Bus number to check / return
	323	* @return pointer to bus, if valid, else NULL
	324	*/
1f2ba722	325	static struct i2c_bus tegra_i2c_get_bus(struct i2c_adapter adap)
96a78ac0	326	{
d84eb856 SG	327	struct i2c_bus *bus;
d84eb856 SG	328
1f2ba722	329	bus = &i2c_controllers[adap->hwadapnr];
d84eb856	330	if (!bus->inited) {
1f2ba722	331	debug("%s: Bus %u not available\n", __func__, adap->hwadapnr);
d84eb856 SG	332	return NULL;
	333	}
	334
	335	return bus;
96a78ac0 YL	336	}
96a78ac0 YL	337
1f2ba722 SG	338	static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap,
1f2ba722 SG	339	unsigned int speed)
96a78ac0	340	{
d84eb856	341	struct i2c_bus *bus;
96a78ac0	342
1f2ba722	343	bus = tegra_i2c_get_bus(adap);
d84eb856 SG	344	if (!bus)
	345	return 0;
	346	bus->speed = speed;
	347	i2c_init_controller(bus);
96a78ac0 YL	348
	349	return 0;
	350	}
	351
	352	static int i2c_get_config(const void blob, int node, struct i2c_bus i2c_bus)
	353	{
	354	i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
	355
	356	/*
	357	* We don't have a binding for pinmux yet. Leave it out for now. So
	358	* far no one needs anything other than the default.
	359	*/
	360	i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
	361	i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
	362	i2c_bus->periph_id = clock_decode_periph_id(blob, node);
	363
	364	/*
	365	* We can't specify the pinmux config in the fdt, so I2C2 will not
	366	* work on Seaboard. It normally has no devices on it anyway.
	367	* You could add in this little hack if you need to use it.
	368	* The correct solution is a pinmux binding in the fdt.
	369	*
	370	* if (i2c_bus->periph_id == PERIPH_ID_I2C2)
	371	* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
	372	*/
	373	if (i2c_bus->periph_id == -1)
	374	return -FDT_ERR_NOTFOUND;
	375
	376	return 0;
	377	}
	378
	379	/*
	380	* Process a list of nodes, adding them to our list of I2C ports.
	381	*
	382	* @param blob fdt blob
	383	* @param node_list list of nodes to process (any <=0 are ignored)
	384	* @param count number of nodes to process
	385	* @param is_dvc 1 if these are DVC ports, 0 if standard I2C
e32624ef	386	* @param is_scs 1 if this HW uses a single clock source (T114+)
96a78ac0 YL	387	* @return 0 if ok, -1 on error
	388	*/
	389	static int process_nodes(const void *blob, int node_list[], int count,
e32624ef	390	int is_dvc, int is_scs)
96a78ac0 YL	391	{
	392	struct i2c_bus *i2c_bus;
	393	int i;
	394
	395	/* build the i2c_controllers[] for each controller */
	396	for (i = 0; i < count; i++) {
	397	int node = node_list[i];
	398
	399	if (node <= 0)
	400	continue;
	401
	402	i2c_bus = &i2c_controllers[i];
	403	i2c_bus->id = i;
	404
	405	if (i2c_get_config(blob, node, i2c_bus)) {
	406	printf("i2c_init_board: failed to decode bus %d\n", i);
	407	return -1;
	408	}
	409
e32624ef TW	410	i2c_bus->is_scs = is_scs;
e32624ef TW	411
96a78ac0 YL	412	i2c_bus->is_dvc = is_dvc;
	413	if (is_dvc) {
	414	i2c_bus->control =
	415	&((struct dvc_ctlr *)i2c_bus->regs)->control;
	416	} else {
	417	i2c_bus->control = &i2c_bus->regs->control;
	418	}
	419	debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
	420	is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
	421	i2c_bus->periph_id, i2c_bus->speed);
	422	i2c_init_controller(i2c_bus);
	423	debug("ok\n");
	424	i2c_bus->inited = 1;
	425
	426	/* Mark position as used */
	427	node_list[i] = -1;
	428	}
	429
	430	return 0;
	431	}
	432
	433	/* Sadly there is no error return from this function */
	434	void i2c_init_board(void)
	435	{
	436	int node_list[TEGRA_I2C_NUM_CONTROLLERS];
	437	const void *blob = gd->fdt_blob;
	438	int count;
	439
e32624ef TW	440	/* First check for newer (T114+) I2C ports */
	441	count = fdtdec_find_aliases_for_id(blob, "i2c",
	442	COMPAT_NVIDIA_TEGRA114_I2C, node_list,
	443	TEGRA_I2C_NUM_CONTROLLERS);
	444	if (process_nodes(blob, node_list, count, 0, 1))
	445	return;
	446
	447	/* Now get the older (T20/T30) normal I2C ports */
96a78ac0 YL	448	count = fdtdec_find_aliases_for_id(blob, "i2c",
	449	COMPAT_NVIDIA_TEGRA20_I2C, node_list,
	450	TEGRA_I2C_NUM_CONTROLLERS);
e32624ef	451	if (process_nodes(blob, node_list, count, 0, 0))
96a78ac0 YL	452	return;
	453
	454	/* Now look for dvc ports */
	455	count = fdtdec_add_aliases_for_id(blob, "i2c",
	456	COMPAT_NVIDIA_TEGRA20_DVC, node_list,
	457	TEGRA_I2C_NUM_CONTROLLERS);
e32624ef	458	if (process_nodes(blob, node_list, count, 1, 0))
96a78ac0 YL	459	return;
	460	}
	461
1f2ba722	462	static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
96a78ac0	463	{
cdce8899 SG	464	/* No i2c support prior to relocation */
	465	if (!(gd->flags & GD_FLG_RELOC))
	466	return;
	467
96a78ac0 YL	468	/* This will override the speed selected in the fdt for that port */
	469	debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
	470	i2c_set_bus_speed(speed);
	471	}
	472
	473	/* i2c write version without the register address */
19d7bf3d JH	474	static int i2c_write_data(struct i2c_bus bus, uchar chip, uchar buffer,
19d7bf3d JH	475	int len, bool end_with_repeated_start)
96a78ac0 YL	476	{
	477	int rc;
	478
	479	debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
	480	debug("write_data: ");
	481	/* use rc for counter */
	482	for (rc = 0; rc < len; ++rc)
	483	debug(" 0x%02x", buffer[rc]);
	484	debug("\n");
	485
	486	/* Shift 7-bit address over for lower-level i2c functions */
68049a08 SW	487	rc = tegra_i2c_write_data(bus, chip << 1, buffer, len,
68049a08 SW	488	end_with_repeated_start);
96a78ac0 YL	489	if (rc)
	490	debug("i2c_write_data(): rc=%d\n", rc);
	491
	492	return rc;
	493	}
	494
	495	/* i2c read version without the register address */
19d7bf3d JH	496	static int i2c_read_data(struct i2c_bus bus, uchar chip, uchar buffer,
19d7bf3d JH	497	int len)
96a78ac0 YL	498	{
	499	int rc;
	500
	501	debug("inside i2c_read_data():\n");
	502	/* Shift 7-bit address over for lower-level i2c functions */
d84eb856	503	rc = tegra_i2c_read_data(bus, chip << 1, buffer, len);
96a78ac0 YL	504	if (rc) {
	505	debug("i2c_read_data(): rc=%d\n", rc);
	506	return rc;
	507	}
	508
	509	debug("i2c_read_data: ");
	510	/* reuse rc for counter*/
	511	for (rc = 0; rc < len; ++rc)
	512	debug(" 0x%02x", buffer[rc]);
	513	debug("\n");
	514
	515	return 0;
	516	}
	517
	518	/* Probe to see if a chip is present. */
1f2ba722	519	static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
96a78ac0	520	{
d84eb856	521	struct i2c_bus *bus;
96a78ac0 YL	522	int rc;
	523	uchar reg;
	524
	525	debug("i2c_probe: addr=0x%x\n", chip);
1f2ba722	526	bus = tegra_i2c_get_bus(adap);
d84eb856 SG	527	if (!bus)
d84eb856 SG	528	return 1;
96a78ac0	529	reg = 0;
68049a08	530	rc = i2c_write_data(bus, chip, &reg, 1, false);
96a78ac0 YL	531	if (rc) {
	532	debug("Error probing 0x%x.\n", chip);
	533	return 1;
	534	}
	535	return 0;
	536	}
	537
	538	static int i2c_addr_ok(const uint addr, const int alen)
	539	{
	540	/* We support 7 or 10 bit addresses, so one or two bytes each */
	541	return alen == 1 \|\| alen == 2;
	542	}
	543
	544	/* Read bytes */
1f2ba722 SG	545	static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
1f2ba722 SG	546	int alen, uchar *buffer, int len)
96a78ac0	547	{
d84eb856	548	struct i2c_bus *bus;
96a78ac0 YL	549	uint offset;
	550	int i;
	551
ad3091ad SW	552	debug("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
ad3091ad SW	553	chip, addr, alen, len);
1f2ba722	554	bus = tegra_i2c_get_bus(adap);
d84eb856 SG	555	if (!bus)
d84eb856 SG	556	return 1;
96a78ac0 YL	557	if (!i2c_addr_ok(addr, alen)) {
	558	debug("i2c_read: Bad address %x.%d.\n", addr, alen);
	559	return 1;
	560	}
	561	for (offset = 0; offset < len; offset++) {
	562	if (alen) {
	563	uchar data[alen];
	564	for (i = 0; i < alen; i++) {
	565	data[alen - i - 1] =
	566	(addr + offset) >> (8 * i);
	567	}
68049a08	568	if (i2c_write_data(bus, chip, data, alen, true)) {
96a78ac0 YL	569	debug("i2c_read: error sending (0x%x)\n",
	570	addr);
	571	return 1;
	572	}
	573	}
d84eb856	574	if (i2c_read_data(bus, chip, buffer + offset, 1)) {
96a78ac0 YL	575	debug("i2c_read: error reading (0x%x)\n", addr);
	576	return 1;
	577	}
	578	}
	579
	580	return 0;
	581	}
	582
	583	/* Write bytes */
1f2ba722 SG	584	static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
1f2ba722 SG	585	int alen, uchar *buffer, int len)
96a78ac0	586	{
d84eb856	587	struct i2c_bus *bus;
96a78ac0 YL	588	uint offset;
	589	int i;
	590
ad3091ad SW	591	debug("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
ad3091ad SW	592	chip, addr, alen, len);
1f2ba722	593	bus = tegra_i2c_get_bus(adap);
d84eb856 SG	594	if (!bus)
d84eb856 SG	595	return 1;
96a78ac0 YL	596	if (!i2c_addr_ok(addr, alen)) {
	597	debug("i2c_write: Bad address %x.%d.\n", addr, alen);
	598	return 1;
	599	}
	600	for (offset = 0; offset < len; offset++) {
	601	uchar data[alen + 1];
	602	for (i = 0; i < alen; i++)
	603	data[alen - i - 1] = (addr + offset) >> (8 * i);
	604	data[alen] = buffer[offset];
68049a08	605	if (i2c_write_data(bus, chip, data, alen + 1, false)) {
96a78ac0 YL	606	debug("i2c_write: error sending (0x%x)\n", addr);
	607	return 1;
	608	}
	609	}
	610
	611	return 0;
	612	}
	613
e31c1e50 SG	614	int tegra_i2c_get_dvc_bus_num(void)
	615	{
	616	int i;
	617
1f2ba722	618	for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) {
e31c1e50 SG	619	struct i2c_bus *bus = &i2c_controllers[i];
	620
	621	if (bus->inited && bus->is_dvc)
	622	return i;
	623	}
	624
	625	return -1;
	626	}
1f2ba722 SG	627
	628	/*
	629	* Register soft i2c adapters
	630	*/
	631	U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe,
	632	tegra_i2c_read, tegra_i2c_write,
	633	tegra_i2c_set_bus_speed, 100000, 0, 0)
	634	U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe,
	635	tegra_i2c_read, tegra_i2c_write,
	636	tegra_i2c_set_bus_speed, 100000, 0, 1)
	637	U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
	638	tegra_i2c_read, tegra_i2c_write,
	639	tegra_i2c_set_bus_speed, 100000, 0, 2)
	640	U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
	641	tegra_i2c_read, tegra_i2c_write,
	642	tegra_i2c_set_bus_speed, 100000, 0, 3)
ac2ff538 AB	643	#if TEGRA_I2C_NUM_CONTROLLERS > 4
	644	U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe,
	645	tegra_i2c_read, tegra_i2c_write,
	646	tegra_i2c_set_bus_speed, 100000, 0, 4)
	647	#endif