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8934f784 MS |
1 | /* |
2 | * Driver for the Zynq-7000 PS I2C controller | |
3 | * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) | |
4 | * | |
5 | * Author: Joe Hershberger <joe.hershberger@ni.com> | |
6 | * Copyright (c) 2012 Joe Hershberger. | |
7 | * | |
8 | * Copyright (c) 2012-2013 Xilinx, Michal Simek | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
8934f784 MS |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <asm/io.h> | |
15 | #include <i2c.h> | |
16 | #include <asm/errno.h> | |
17 | #include <asm/arch/hardware.h> | |
18 | ||
19 | /* i2c register set */ | |
20 | struct zynq_i2c_registers { | |
21 | u32 control; | |
22 | u32 status; | |
23 | u32 address; | |
24 | u32 data; | |
25 | u32 interrupt_status; | |
26 | u32 transfer_size; | |
27 | u32 slave_mon_pause; | |
28 | u32 time_out; | |
29 | u32 interrupt_mask; | |
30 | u32 interrupt_enable; | |
31 | u32 interrupt_disable; | |
32 | }; | |
33 | ||
34 | /* Control register fields */ | |
35 | #define ZYNQ_I2C_CONTROL_RW 0x00000001 | |
36 | #define ZYNQ_I2C_CONTROL_MS 0x00000002 | |
37 | #define ZYNQ_I2C_CONTROL_NEA 0x00000004 | |
38 | #define ZYNQ_I2C_CONTROL_ACKEN 0x00000008 | |
39 | #define ZYNQ_I2C_CONTROL_HOLD 0x00000010 | |
40 | #define ZYNQ_I2C_CONTROL_SLVMON 0x00000020 | |
41 | #define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040 | |
42 | #define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8 | |
43 | #define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00 | |
44 | #define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14 | |
45 | #define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000 | |
46 | ||
47 | /* Status register values */ | |
48 | #define ZYNQ_I2C_STATUS_RXDV 0x00000020 | |
49 | #define ZYNQ_I2C_STATUS_TXDV 0x00000040 | |
50 | #define ZYNQ_I2C_STATUS_RXOVF 0x00000080 | |
51 | #define ZYNQ_I2C_STATUS_BA 0x00000100 | |
52 | ||
53 | /* Interrupt register fields */ | |
54 | #define ZYNQ_I2C_INTERRUPT_COMP 0x00000001 | |
55 | #define ZYNQ_I2C_INTERRUPT_DATA 0x00000002 | |
56 | #define ZYNQ_I2C_INTERRUPT_NACK 0x00000004 | |
57 | #define ZYNQ_I2C_INTERRUPT_TO 0x00000008 | |
58 | #define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010 | |
59 | #define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020 | |
60 | #define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040 | |
61 | #define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080 | |
62 | #define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200 | |
63 | ||
64 | #define ZYNQ_I2C_FIFO_DEPTH 16 | |
65 | #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */ | |
66 | ||
67 | #if defined(CONFIG_ZYNQ_I2C0) | |
68 | # define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0 | |
69 | #else | |
70 | # define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1 | |
71 | #endif | |
72 | ||
73 | static struct zynq_i2c_registers *zynq_i2c = | |
74 | (struct zynq_i2c_registers *)ZYNQ_I2C_BASE; | |
75 | ||
76 | /* I2C init called by cmd_i2c when doing 'i2c reset'. */ | |
77 | void i2c_init(int requested_speed, int slaveadd) | |
78 | { | |
79 | /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ | |
80 | writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | | |
81 | (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control); | |
82 | ||
83 | /* Enable master mode, ack, and 7-bit addressing */ | |
84 | setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS | | |
85 | ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA); | |
86 | } | |
87 | ||
88 | #ifdef DEBUG | |
89 | static void zynq_i2c_debug_status(void) | |
90 | { | |
91 | int int_status; | |
92 | int status; | |
93 | int_status = readl(&zynq_i2c->interrupt_status); | |
94 | ||
95 | status = readl(&zynq_i2c->status); | |
96 | if (int_status || status) { | |
97 | debug("Status: "); | |
98 | if (int_status & ZYNQ_I2C_INTERRUPT_COMP) | |
99 | debug("COMP "); | |
100 | if (int_status & ZYNQ_I2C_INTERRUPT_DATA) | |
101 | debug("DATA "); | |
102 | if (int_status & ZYNQ_I2C_INTERRUPT_NACK) | |
103 | debug("NACK "); | |
104 | if (int_status & ZYNQ_I2C_INTERRUPT_TO) | |
105 | debug("TO "); | |
106 | if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY) | |
107 | debug("SLVRDY "); | |
108 | if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) | |
109 | debug("RXOVF "); | |
110 | if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) | |
111 | debug("TXOVF "); | |
112 | if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF) | |
113 | debug("RXUNF "); | |
114 | if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST) | |
115 | debug("ARBLOST "); | |
116 | if (status & ZYNQ_I2C_STATUS_RXDV) | |
117 | debug("RXDV "); | |
118 | if (status & ZYNQ_I2C_STATUS_TXDV) | |
119 | debug("TXDV "); | |
120 | if (status & ZYNQ_I2C_STATUS_RXOVF) | |
121 | debug("RXOVF "); | |
122 | if (status & ZYNQ_I2C_STATUS_BA) | |
123 | debug("BA "); | |
124 | debug("TS%d ", readl(&zynq_i2c->transfer_size)); | |
125 | debug("\n"); | |
126 | } | |
127 | } | |
128 | #endif | |
129 | ||
130 | /* Wait for an interrupt */ | |
131 | static u32 zynq_i2c_wait(u32 mask) | |
132 | { | |
133 | int timeout, int_status; | |
134 | ||
135 | for (timeout = 0; timeout < 100; timeout++) { | |
136 | udelay(100); | |
137 | int_status = readl(&zynq_i2c->interrupt_status); | |
138 | if (int_status & mask) | |
139 | break; | |
140 | } | |
141 | #ifdef DEBUG | |
142 | zynq_i2c_debug_status(); | |
143 | #endif | |
144 | /* Clear interrupt status flags */ | |
145 | writel(int_status & mask, &zynq_i2c->interrupt_status); | |
146 | ||
147 | return int_status & mask; | |
148 | } | |
149 | ||
150 | /* | |
151 | * I2C probe called by cmd_i2c when doing 'i2c probe'. | |
152 | * Begin read, nak data byte, end. | |
153 | */ | |
154 | int i2c_probe(u8 dev) | |
155 | { | |
156 | /* Attempt to read a byte */ | |
157 | setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | | |
158 | ZYNQ_I2C_CONTROL_RW); | |
159 | clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); | |
160 | writel(0xFF, &zynq_i2c->interrupt_status); | |
161 | writel(dev, &zynq_i2c->address); | |
162 | writel(1, &zynq_i2c->transfer_size); | |
163 | ||
164 | return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | | |
165 | ZYNQ_I2C_INTERRUPT_NACK) & | |
166 | ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; | |
167 | } | |
168 | ||
169 | /* | |
170 | * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c | |
171 | * Begin write, send address byte(s), begin read, receive data bytes, end. | |
172 | */ | |
173 | int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) | |
174 | { | |
175 | u32 status; | |
176 | u32 i = 0; | |
177 | u8 *cur_data = data; | |
178 | ||
179 | /* Check the hardware can handle the requested bytes */ | |
180 | if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX)) | |
181 | return -EINVAL; | |
182 | ||
183 | /* Write the register address */ | |
184 | setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | | |
185 | ZYNQ_I2C_CONTROL_HOLD); | |
186 | /* | |
187 | * Temporarily disable restart (by clearing hold) | |
188 | * It doesn't seem to work. | |
189 | */ | |
190 | clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW | | |
191 | ZYNQ_I2C_CONTROL_HOLD); | |
192 | writel(0xFF, &zynq_i2c->interrupt_status); | |
193 | while (alen--) | |
194 | writel(addr >> (8*alen), &zynq_i2c->data); | |
195 | writel(dev, &zynq_i2c->address); | |
196 | ||
197 | /* Wait for the address to be sent */ | |
198 | if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { | |
199 | /* Release the bus */ | |
200 | clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); | |
201 | return -ETIMEDOUT; | |
202 | } | |
203 | debug("Device acked address\n"); | |
204 | ||
205 | setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | | |
206 | ZYNQ_I2C_CONTROL_RW); | |
207 | /* Start reading data */ | |
208 | writel(dev, &zynq_i2c->address); | |
209 | writel(length, &zynq_i2c->transfer_size); | |
210 | ||
211 | /* Wait for data */ | |
212 | do { | |
213 | status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | | |
214 | ZYNQ_I2C_INTERRUPT_DATA); | |
215 | if (!status) { | |
216 | /* Release the bus */ | |
217 | clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); | |
218 | return -ETIMEDOUT; | |
219 | } | |
220 | debug("Read %d bytes\n", | |
221 | length - readl(&zynq_i2c->transfer_size)); | |
222 | for (; i < length - readl(&zynq_i2c->transfer_size); i++) | |
223 | *(cur_data++) = readl(&zynq_i2c->data); | |
224 | } while (readl(&zynq_i2c->transfer_size) != 0); | |
225 | /* All done... release the bus */ | |
226 | clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); | |
227 | ||
228 | #ifdef DEBUG | |
229 | zynq_i2c_debug_status(); | |
230 | #endif | |
231 | return 0; | |
232 | } | |
233 | ||
234 | /* | |
235 | * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c | |
236 | * Begin write, send address byte(s), send data bytes, end. | |
237 | */ | |
238 | int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) | |
239 | { | |
240 | u8 *cur_data = data; | |
241 | ||
242 | /* Write the register address */ | |
243 | setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | | |
244 | ZYNQ_I2C_CONTROL_HOLD); | |
245 | clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); | |
246 | writel(0xFF, &zynq_i2c->interrupt_status); | |
247 | while (alen--) | |
248 | writel(addr >> (8*alen), &zynq_i2c->data); | |
249 | /* Start the tranfer */ | |
250 | writel(dev, &zynq_i2c->address); | |
251 | if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { | |
252 | /* Release the bus */ | |
253 | clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); | |
254 | return -ETIMEDOUT; | |
255 | } | |
256 | ||
257 | debug("Device acked address\n"); | |
258 | while (length--) { | |
259 | writel(*(cur_data++), &zynq_i2c->data); | |
260 | if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) { | |
261 | if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { | |
262 | /* Release the bus */ | |
263 | clrbits_le32(&zynq_i2c->control, | |
264 | ZYNQ_I2C_CONTROL_HOLD); | |
265 | return -ETIMEDOUT; | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
270 | /* All done... release the bus */ | |
271 | clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); | |
272 | /* Wait for the address and data to be sent */ | |
273 | if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) | |
274 | return -ETIMEDOUT; | |
275 | return 0; | |
276 | } | |
277 | ||
278 | int i2c_set_bus_num(unsigned int bus) | |
279 | { | |
280 | /* Only support bus 0 */ | |
281 | if (bus > 0) | |
282 | return -1; | |
283 | return 0; | |
284 | } | |
285 | ||
286 | unsigned int i2c_get_bus_num(void) | |
287 | { | |
288 | /* Only support bus 0 */ | |
289 | return 0; | |
290 | } |