[people/ms/u-boot.git] / drivers / i2c / zynq_i2c.c

/*
 * Driver for the Zynq-7000 PS I2C controller
 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
 *
 * Author: Joe Hershberger <joe.hershberger@ni.com>
 * Copyright (c) 2012 Joe Hershberger.
 *
 * Copyright (c) 2012-2013 Xilinx, Michal Simek
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <i2c.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>

/* i2c register set */
struct zynq_i2c_registers {
	u32 control;
	u32 status;
	u32 address;
	u32 data;
	u32 interrupt_status;
	u32 transfer_size;
	u32 slave_mon_pause;
	u32 time_out;
	u32 interrupt_mask;
	u32 interrupt_enable;
	u32 interrupt_disable;
};

/* Control register fields */
#define ZYNQ_I2C_CONTROL_RW		0x00000001
#define ZYNQ_I2C_CONTROL_MS		0x00000002
#define ZYNQ_I2C_CONTROL_NEA		0x00000004
#define ZYNQ_I2C_CONTROL_ACKEN		0x00000008
#define ZYNQ_I2C_CONTROL_HOLD		0x00000010
#define ZYNQ_I2C_CONTROL_SLVMON		0x00000020
#define ZYNQ_I2C_CONTROL_CLR_FIFO	0x00000040
#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT	8
#define ZYNQ_I2C_CONTROL_DIV_B_MASK	0x00003F00
#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT	14
#define ZYNQ_I2C_CONTROL_DIV_A_MASK	0x0000C000

/* Status register values */
#define ZYNQ_I2C_STATUS_RXDV	0x00000020
#define ZYNQ_I2C_STATUS_TXDV	0x00000040
#define ZYNQ_I2C_STATUS_RXOVF	0x00000080
#define ZYNQ_I2C_STATUS_BA	0x00000100

/* Interrupt register fields */
#define ZYNQ_I2C_INTERRUPT_COMP		0x00000001
#define ZYNQ_I2C_INTERRUPT_DATA		0x00000002
#define ZYNQ_I2C_INTERRUPT_NACK		0x00000004
#define ZYNQ_I2C_INTERRUPT_TO		0x00000008
#define ZYNQ_I2C_INTERRUPT_SLVRDY	0x00000010
#define ZYNQ_I2C_INTERRUPT_RXOVF	0x00000020
#define ZYNQ_I2C_INTERRUPT_TXOVF	0x00000040
#define ZYNQ_I2C_INTERRUPT_RXUNF	0x00000080
#define ZYNQ_I2C_INTERRUPT_ARBLOST	0x00000200

#define ZYNQ_I2C_FIFO_DEPTH		16
#define ZYNQ_I2C_TRANSFERT_SIZE_MAX	255 /* Controller transfer limit */

static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
{
	return adap->hwadapnr ?
		/* Zynq PS I2C1 */
		(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
		/* Zynq PS I2C0 */
		(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
}

/* I2C init called by cmd_i2c when doing 'i2c reset'. */
static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
			  int slaveadd)
{
	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);

	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
	writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
		(2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);

	/* Enable master mode, ack, and 7-bit addressing */
	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
		ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
}

#ifdef DEBUG
static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
{
	int int_status;
	int status;
	int_status = readl(&zynq_i2c->interrupt_status);

	status = readl(&zynq_i2c->status);
	if (int_status || status) {
		debug("Status: ");
		if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
			debug("COMP ");
		if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
			debug("DATA ");
		if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
			debug("NACK ");
		if (int_status & ZYNQ_I2C_INTERRUPT_TO)
			debug("TO ");
		if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
			debug("SLVRDY ");
		if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
			debug("RXOVF ");
		if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
			debug("TXOVF ");
		if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
			debug("RXUNF ");
		if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
			debug("ARBLOST ");
		if (status & ZYNQ_I2C_STATUS_RXDV)
			debug("RXDV ");
		if (status & ZYNQ_I2C_STATUS_TXDV)
			debug("TXDV ");
		if (status & ZYNQ_I2C_STATUS_RXOVF)
			debug("RXOVF ");
		if (status & ZYNQ_I2C_STATUS_BA)
			debug("BA ");
		debug("TS%d ", readl(&zynq_i2c->transfer_size));
		debug("\n");
	}
}
#endif

/* Wait for an interrupt */
static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
{
	int timeout, int_status;

	for (timeout = 0; timeout < 100; timeout++) {
		udelay(100);
		int_status = readl(&zynq_i2c->interrupt_status);
		if (int_status & mask)
			break;
	}
#ifdef DEBUG
	zynq_i2c_debug_status(zynq_i2c);
#endif
	/* Clear interrupt status flags */
	writel(int_status & mask, &zynq_i2c->interrupt_status);

	return int_status & mask;
}

/*
 * I2C probe called by cmd_i2c when doing 'i2c probe'.
 * Begin read, nak data byte, end.
 */
static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);

	/* Attempt to read a byte */
	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
		ZYNQ_I2C_CONTROL_RW);
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	writel(0xFF, &zynq_i2c->interrupt_status);
	writel(dev, &zynq_i2c->address);
	writel(1, &zynq_i2c->transfer_size);

	return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
		ZYNQ_I2C_INTERRUPT_NACK) &
		ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
}

/*
 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 * Begin write, send address byte(s), begin read, receive data bytes, end.
 */
static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
			 int alen, u8 *data, int length)
{
	u32 status;
	u32 i = 0;
	u8 *cur_data = data;
	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);

	/* Check the hardware can handle the requested bytes */
	if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
		return -EINVAL;

	/* Write the register address */
	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
		ZYNQ_I2C_CONTROL_HOLD);
	/*
	 * Temporarily disable restart (by clearing hold)
	 * It doesn't seem to work.
	 */
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	writel(0xFF, &zynq_i2c->interrupt_status);
	if (alen) {
		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
		writel(dev, &zynq_i2c->address);
		while (alen--)
			writel(addr >> (8 * alen), &zynq_i2c->data);

		/* Wait for the address to be sent */
		if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
			/* Release the bus */
			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
			return -ETIMEDOUT;
		}
		debug("Device acked address\n");
	}

	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
		ZYNQ_I2C_CONTROL_RW);
	/* Start reading data */
	writel(dev, &zynq_i2c->address);
	writel(length, &zynq_i2c->transfer_size);

	/* Wait for data */
	do {
		status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
			ZYNQ_I2C_INTERRUPT_DATA);
		if (!status) {
			/* Release the bus */
			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
			return -ETIMEDOUT;
		}
		debug("Read %d bytes\n",
		      length - readl(&zynq_i2c->transfer_size));
		for (; i < length - readl(&zynq_i2c->transfer_size); i++)
			*(cur_data++) = readl(&zynq_i2c->data);
	} while (readl(&zynq_i2c->transfer_size) != 0);
	/* All done... release the bus */
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);

#ifdef DEBUG
	zynq_i2c_debug_status(zynq_i2c);
#endif
	return 0;
}

/*
 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 * Begin write, send address byte(s), send data bytes, end.
 */
static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			  int alen, u8 *data, int length)
{
	u8 *cur_data = data;
	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);

	/* Write the register address */
	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
		ZYNQ_I2C_CONTROL_HOLD);
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
	writel(0xFF, &zynq_i2c->interrupt_status);
	writel(dev, &zynq_i2c->address);
	if (alen) {
		while (alen--)
			writel(addr >> (8 * alen), &zynq_i2c->data);
		/* Start the tranfer */
		if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
			/* Release the bus */
			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
			return -ETIMEDOUT;
		}
		debug("Device acked address\n");
	}

	while (length--) {
		writel(*(cur_data++), &zynq_i2c->data);
		if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
			if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
				/* Release the bus */
				clrbits_le32(&zynq_i2c->control,
					     ZYNQ_I2C_CONTROL_HOLD);
				return -ETIMEDOUT;
			}
		}
	}

	/* All done... release the bus */
	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	/* Wait for the address and data to be sent */
	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
		return -ETIMEDOUT;
	return 0;
}

static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
			unsigned int speed)
{
	if (speed != 1000000)
		return -EINVAL;

	return 0;
}

#ifdef CONFIG_ZYNQ_I2C0
U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
			 zynq_i2c_write, zynq_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
			 0)
#endif
#ifdef CONFIG_ZYNQ_I2C1
U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
			 zynq_i2c_write, zynq_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
			 1)
#endif
Commit	Line	Data
8934f784 MS	1	/*
	2	* Driver for the Zynq-7000 PS I2C controller
	3	* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
	4	*
	5	* Author: Joe Hershberger <joe.hershberger@ni.com>
	6	* Copyright (c) 2012 Joe Hershberger.
	7	*
	8	* Copyright (c) 2012-2013 Xilinx, Michal Simek
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
8934f784 MS	11	*/
	12
	13	#include <common.h>
	14	#include <asm/io.h>
	15	#include <i2c.h>
	16	#include <asm/errno.h>
	17	#include <asm/arch/hardware.h>
	18
	19	/* i2c register set */
	20	struct zynq_i2c_registers {
	21	u32 control;
	22	u32 status;
	23	u32 address;
	24	u32 data;
	25	u32 interrupt_status;
	26	u32 transfer_size;
	27	u32 slave_mon_pause;
	28	u32 time_out;
	29	u32 interrupt_mask;
	30	u32 interrupt_enable;
	31	u32 interrupt_disable;
	32	};
	33
	34	/* Control register fields */
	35	#define ZYNQ_I2C_CONTROL_RW 0x00000001
	36	#define ZYNQ_I2C_CONTROL_MS 0x00000002
	37	#define ZYNQ_I2C_CONTROL_NEA 0x00000004
	38	#define ZYNQ_I2C_CONTROL_ACKEN 0x00000008
	39	#define ZYNQ_I2C_CONTROL_HOLD 0x00000010
	40	#define ZYNQ_I2C_CONTROL_SLVMON 0x00000020
	41	#define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040
	42	#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8
	43	#define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00
	44	#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14
	45	#define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000
	46
	47	/* Status register values */
	48	#define ZYNQ_I2C_STATUS_RXDV 0x00000020
	49	#define ZYNQ_I2C_STATUS_TXDV 0x00000040
	50	#define ZYNQ_I2C_STATUS_RXOVF 0x00000080
	51	#define ZYNQ_I2C_STATUS_BA 0x00000100
	52
	53	/* Interrupt register fields */
	54	#define ZYNQ_I2C_INTERRUPT_COMP 0x00000001
	55	#define ZYNQ_I2C_INTERRUPT_DATA 0x00000002
	56	#define ZYNQ_I2C_INTERRUPT_NACK 0x00000004
	57	#define ZYNQ_I2C_INTERRUPT_TO 0x00000008
	58	#define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010
	59	#define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020
	60	#define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040
	61	#define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080
	62	#define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200
	63
	64	#define ZYNQ_I2C_FIFO_DEPTH 16
	65	#define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */
	66
18948632 MB	67	static struct zynq_i2c_registers i2c_select(struct i2c_adapter adap)
	68	{
	69	return adap->hwadapnr ?
	70	/* Zynq PS I2C1 */
	71	(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
	72	/* Zynq PS I2C0 */
	73	(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
	74	}
8934f784 MS	75
8934f784 MS	76	/* I2C init called by cmd_i2c when doing 'i2c reset'. */
0bdffe71 HS	77	static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
0bdffe71 HS	78	int slaveadd)
8934f784	79	{
18948632 MB	80	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
18948632 MB	81
8934f784 MS	82	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
	83	writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) \|
	84	(2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
	85
	86	/* Enable master mode, ack, and 7-bit addressing */
	87	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS \|
	88	ZYNQ_I2C_CONTROL_ACKEN \| ZYNQ_I2C_CONTROL_NEA);
	89	}
	90
	91	#ifdef DEBUG
18948632	92	static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
8934f784 MS	93	{
	94	int int_status;
	95	int status;
	96	int_status = readl(&zynq_i2c->interrupt_status);
	97
	98	status = readl(&zynq_i2c->status);
	99	if (int_status \|\| status) {
	100	debug("Status: ");
	101	if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
	102	debug("COMP ");
	103	if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
	104	debug("DATA ");
	105	if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
	106	debug("NACK ");
	107	if (int_status & ZYNQ_I2C_INTERRUPT_TO)
	108	debug("TO ");
	109	if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
	110	debug("SLVRDY ");
	111	if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
	112	debug("RXOVF ");
	113	if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
	114	debug("TXOVF ");
	115	if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
	116	debug("RXUNF ");
	117	if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
	118	debug("ARBLOST ");
	119	if (status & ZYNQ_I2C_STATUS_RXDV)
	120	debug("RXDV ");
	121	if (status & ZYNQ_I2C_STATUS_TXDV)
	122	debug("TXDV ");
	123	if (status & ZYNQ_I2C_STATUS_RXOVF)
	124	debug("RXOVF ");
	125	if (status & ZYNQ_I2C_STATUS_BA)
	126	debug("BA ");
	127	debug("TS%d ", readl(&zynq_i2c->transfer_size));
	128	debug("\n");
	129	}
	130	}
	131	#endif
	132
	133	/* Wait for an interrupt */
18948632	134	static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
8934f784 MS	135	{
	136	int timeout, int_status;
	137
	138	for (timeout = 0; timeout < 100; timeout++) {
	139	udelay(100);
	140	int_status = readl(&zynq_i2c->interrupt_status);
	141	if (int_status & mask)
	142	break;
	143	}
	144	#ifdef DEBUG
5146fc2b	145	zynq_i2c_debug_status(zynq_i2c);
8934f784 MS	146	#endif
	147	/* Clear interrupt status flags */
	148	writel(int_status & mask, &zynq_i2c->interrupt_status);
	149
	150	return int_status & mask;
	151	}
	152
	153	/*
	154	* I2C probe called by cmd_i2c when doing 'i2c probe'.
	155	* Begin read, nak data byte, end.
	156	*/
0bdffe71	157	static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
8934f784	158	{
18948632 MB	159	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
18948632 MB	160
8934f784 MS	161	/* Attempt to read a byte */
	162	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO \|
	163	ZYNQ_I2C_CONTROL_RW);
	164	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	165	writel(0xFF, &zynq_i2c->interrupt_status);
	166	writel(dev, &zynq_i2c->address);
	167	writel(1, &zynq_i2c->transfer_size);
	168
18948632	169	return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP \|
8934f784 MS	170	ZYNQ_I2C_INTERRUPT_NACK) &
	171	ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
	172	}
	173
	174	/*
	175	* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
	176	* Begin write, send address byte(s), begin read, receive data bytes, end.
	177	*/
0bdffe71 HS	178	static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
0bdffe71 HS	179	int alen, u8 *data, int length)
8934f784 MS	180	{
	181	u32 status;
	182	u32 i = 0;
	183	u8 *cur_data = data;
18948632	184	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
8934f784 MS	185
	186	/* Check the hardware can handle the requested bytes */
	187	if ((length < 0) \|\| (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
	188	return -EINVAL;
	189
	190	/* Write the register address */
	191	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO \|
	192	ZYNQ_I2C_CONTROL_HOLD);
	193	/*
	194	* Temporarily disable restart (by clearing hold)
	195	* It doesn't seem to work.
	196	*/
9e901071	197	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
8934f784	198	writel(0xFF, &zynq_i2c->interrupt_status);
9e901071 MB	199	if (alen) {
	200	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
	201	writel(dev, &zynq_i2c->address);
	202	while (alen--)
	203	writel(addr >> (8 * alen), &zynq_i2c->data);
8934f784	204
9e901071	205	/* Wait for the address to be sent */
18948632	206	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
9e901071 MB	207	/* Release the bus */
	208	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	209	return -ETIMEDOUT;
	210	}
	211	debug("Device acked address\n");
8934f784	212	}
8934f784 MS	213
	214	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO \|
	215	ZYNQ_I2C_CONTROL_RW);
	216	/* Start reading data */
	217	writel(dev, &zynq_i2c->address);
	218	writel(length, &zynq_i2c->transfer_size);
	219
	220	/* Wait for data */
	221	do {
18948632	222	status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP \|
8934f784 MS	223	ZYNQ_I2C_INTERRUPT_DATA);
	224	if (!status) {
	225	/* Release the bus */
	226	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	227	return -ETIMEDOUT;
	228	}
	229	debug("Read %d bytes\n",
	230	length - readl(&zynq_i2c->transfer_size));
	231	for (; i < length - readl(&zynq_i2c->transfer_size); i++)
	232	*(cur_data++) = readl(&zynq_i2c->data);
	233	} while (readl(&zynq_i2c->transfer_size) != 0);
	234	/* All done... release the bus */
	235	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	236
	237	#ifdef DEBUG
5146fc2b	238	zynq_i2c_debug_status(zynq_i2c);
8934f784 MS	239	#endif
	240	return 0;
	241	}
	242
	243	/*
	244	* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
	245	* Begin write, send address byte(s), send data bytes, end.
	246	*/
0bdffe71 HS	247	static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
0bdffe71 HS	248	int alen, u8 *data, int length)
8934f784 MS	249	{
8934f784 MS	250	u8 *cur_data = data;
18948632	251	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
8934f784 MS	252
	253	/* Write the register address */
	254	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO \|
	255	ZYNQ_I2C_CONTROL_HOLD);
	256	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
	257	writel(0xFF, &zynq_i2c->interrupt_status);
8934f784	258	writel(dev, &zynq_i2c->address);
9e901071 MB	259	if (alen) {
	260	while (alen--)
	261	writel(addr >> (8 * alen), &zynq_i2c->data);
	262	/* Start the tranfer */
18948632	263	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
9e901071 MB	264	/* Release the bus */
	265	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	266	return -ETIMEDOUT;
	267	}
	268	debug("Device acked address\n");
8934f784 MS	269	}
8934f784 MS	270
8934f784 MS	271	while (length--) {
	272	writel(*(cur_data++), &zynq_i2c->data);
	273	if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
18948632	274	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
8934f784 MS	275	/* Release the bus */
	276	clrbits_le32(&zynq_i2c->control,
	277	ZYNQ_I2C_CONTROL_HOLD);
	278	return -ETIMEDOUT;
	279	}
	280	}
	281	}
	282
	283	/* All done... release the bus */
	284	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
	285	/* Wait for the address and data to be sent */
18948632	286	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
8934f784 MS	287	return -ETIMEDOUT;
	288	return 0;
	289	}
	290
0bdffe71 HS	291	static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
0bdffe71 HS	292	unsigned int speed)
8934f784	293	{
0bdffe71 HS	294	if (speed != 1000000)
0bdffe71 HS	295	return -EINVAL;
8934f784	296
8934f784 MS	297	return 0;
8934f784 MS	298	}
0bdffe71	299
009902a8	300	#ifdef CONFIG_ZYNQ_I2C0
0bdffe71 HS	301	U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
	302	zynq_i2c_write, zynq_i2c_set_bus_speed,
	303	CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
	304	0)
009902a8 MS	305	#endif
009902a8 MS	306	#ifdef CONFIG_ZYNQ_I2C1
18948632 MB	307	U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
	308	zynq_i2c_write, zynq_i2c_set_bus_speed,
	309	CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
	310	1)
009902a8	311	#endif