[people/ms/u-boot.git] / drivers / misc / Kconfig

#
# Multifunction miscellaneous devices
#

menu "Multifunction device drivers"

config MISC
	bool "Enable Driver Model for Misc drivers"
	depends on DM
	help
	  Enable driver model for miscellaneous devices. This class is
	  used only for those do not fit other more general classes. A
	  set of generic read, write and ioctl methods may be used to
	  access the device.

config ALTERA_SYSID
	bool "Altera Sysid support"
	depends on MISC
	help
	  Select this to enable a sysid for Altera devices. Please find
	  details on the "Embedded Peripherals IP User Guide" of Altera.

config ATSHA204A
	bool "Support for Atmel ATSHA204A module"
	depends on MISC
	help
	   Enable support for I2C connected Atmel's ATSHA204A
	   CryptoAuthentication module found for example on the Turris Omnia
	   board.

config ROCKCHIP_EFUSE
        bool "Rockchip e-fuse support"
	depends on MISC
	help
	  Enable (read-only) access for the e-fuse block found in Rockchip
	  SoCs: accesses can either be made using byte addressing and a length
	  or through child-nodes that are generated based on the e-fuse map
	  retrieved from the DTS.

	  This driver currently supports the RK3399 only, but can easily be
	  extended (by porting the read function from the Linux kernel sources)
	  to support other recent Rockchip devices.

config CMD_CROS_EC
	bool "Enable crosec command"
	depends on CROS_EC
	help
	  Enable command-line access to the Chrome OS EC (Embedded
	  Controller). This provides the 'crosec' command which has
	  a number of sub-commands for performing EC tasks such as
	  updating its flash, accessing a small saved context area
	  and talking to the I2C bus behind the EC (if there is one).

config CROS_EC
	bool "Enable Chrome OS EC"
	help
	  Enable access to the Chrome OS EC. This is a separate
	  microcontroller typically available on a SPI bus on Chromebooks. It
	  provides access to the keyboard, some internal storage and may
	  control access to the battery and main PMIC depending on the
	  device. You can use the 'crosec' command to access it.

config CROS_EC_I2C
	bool "Enable Chrome OS EC I2C driver"
	depends on CROS_EC
	help
	  Enable I2C access to the Chrome OS EC. This is used on older
	  ARM Chromebooks such as snow and spring before the standard bus
	  changed to SPI. The EC will accept commands across the I2C using
	  a special message protocol, and provide responses.

config CROS_EC_LPC
	bool "Enable Chrome OS EC LPC driver"
	depends on CROS_EC
	help
	  Enable I2C access to the Chrome OS EC. This is used on x86
	  Chromebooks such as link and falco. The keyboard is provided
	  through a legacy port interface, so on x86 machines the main
	  function of the EC is power and thermal management.

config CROS_EC_SANDBOX
	bool "Enable Chrome OS EC sandbox driver"
	depends on CROS_EC && SANDBOX
	help
	  Enable a sandbox emulation of the Chrome OS EC. This supports
	  keyboard (use the -l flag to enable the LCD), verified boot context,
	  EC flash read/write/erase support and a few other things. It is
	  enough to perform a Chrome OS verified boot on sandbox.

config CROS_EC_SPI
	bool "Enable Chrome OS EC SPI driver"
	depends on CROS_EC
	help
	  Enable SPI access to the Chrome OS EC. This is used on newer
	  ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
	  provides a faster and more robust interface than I2C but the bugs
	  are less interesting.

config DS4510
	bool "Enable support for DS4510 CPU supervisor"
	help
	  Enable support for the Maxim DS4510 CPU supervisor. It has an
	  integrated 64-byte EEPROM, four programmable non-volatile I/O pins
	  and a configurable timer for the supervisor function. The device is
	  connected over I2C.

config FSL_SEC_MON
	bool "Enable FSL SEC_MON Driver"
	help
	  Freescale Security Monitor block is responsible for monitoring
	  system states.
	  Security Monitor can be transitioned on any security failures,
	  like software violations or hardware security violations.

config MXC_OCOTP
	bool "Enable MXC OCOTP Driver"
	help
	  If you say Y here, you will get support for the One Time
	  Programmable memory pages that are stored on the some
	  Freescale i.MX processors.

config NUVOTON_NCT6102D
	bool "Enable Nuvoton NCT6102D Super I/O driver"
	help
	  If you say Y here, you will get support for the Nuvoton
	  NCT6102D Super I/O driver. This can be used to enable or
	  disable the legacy UART, the watchdog or other devices
	  in the Nuvoton Super IO chips on X86 platforms.

config PWRSEQ
	bool "Enable power-sequencing drivers"
	depends on DM
	help
	  Power-sequencing drivers provide support for controlling power for
	  devices. They are typically referenced by a phandle from another
	  device. When the device is started up, its power sequence can be
	  initiated.

config SPL_PWRSEQ
	bool "Enable power-sequencing drivers for SPL"
	depends on PWRSEQ
	help
	  Power-sequencing drivers provide support for controlling power for
	  devices. They are typically referenced by a phandle from another
	  device. When the device is started up, its power sequence can be
	  initiated.

config PCA9551_LED
	bool "Enable PCA9551 LED driver"
	help
	  Enable driver for PCA9551 LED controller. This controller
	  is connected via I2C. So I2C needs to be enabled.

config PCA9551_I2C_ADDR
	hex "I2C address of PCA9551 LED controller"
	depends on PCA9551_LED
	default 0x60
	help
	  The I2C address of the PCA9551 LED controller.

config STM32_RCC
	bool "Enable RCC driver for the STM32 SoC's family"
	depends on STM32 && MISC
	help
	  Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
	  block) is responsible of the management of the clock and reset
	  generation.
	  This driver is similar to an MFD driver in the Linux kernel.

config TEGRA_CAR
	bool "Enable support for the Tegra CAR driver"
	depends on TEGRA_NO_BPMP
	help
	  The Tegra CAR (Clock and Reset Controller) is a HW module that
	  controls almost all clocks and resets in a Tegra SoC.

config TEGRA186_BPMP
	bool "Enable support for the Tegra186 BPMP driver"
	depends on TEGRA186
	help
	  The Tegra BPMP (Boot and Power Management Processor) is a separate
	  auxiliary CPU embedded into Tegra to perform power management work,
	  and controls related features such as clocks, resets, power domains,
	  PMIC I2C bus, etc. This driver provides the core low-level
	  communication path by which feature-specific drivers (such as clock)
	  can make requests to the BPMP. This driver is similar to an MFD
	  driver in the Linux kernel.

config WINBOND_W83627
	bool "Enable Winbond Super I/O driver"
	help
	  If you say Y here, you will get support for the Winbond
	  W83627 Super I/O driver. This can be used to enable the
	  legacy UART or other devices in the Winbond Super IO chips
	  on X86 platforms.

config QFW
	bool
	help
	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.

config I2C_EEPROM
	bool "Enable driver for generic I2C-attached EEPROMs"
	depends on MISC
	help
	  Enable a generic driver for EEPROMs attached via I2C.


config SPL_I2C_EEPROM
	bool "Enable driver for generic I2C-attached EEPROMs for SPL"
	depends on MISC && SPL && SPL_DM
	help
	  This option is an SPL-variant of the I2C_EEPROM option.
	  See the help of I2C_EEPROM for details.

if I2C_EEPROM

config SYS_I2C_EEPROM_ADDR
	hex "Chip address of the EEPROM device"
	default 0

config SYS_I2C_EEPROM_BUS
	int "I2C bus of the EEPROM device."
	default 0

config SYS_EEPROM_SIZE
	int "Size in bytes of the EEPROM device"
	default 256

config SYS_EEPROM_PAGE_WRITE_BITS
	int "Number of bits used to address bytes in a single page"
	default 0
	help
	  The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
	  A 64 byte page, for example would require six bits.

config SYS_EEPROM_PAGE_WRITE_DELAY_MS
	int "Number of milliseconds to delay between page writes"
	default 0

config SYS_I2C_EEPROM_ADDR_LEN
	int "Length in bytes of the EEPROM memory array address"
	default 1
	help
	  Note: This is NOT the chip address length!

config SYS_I2C_EEPROM_ADDR_OVERFLOW
	hex "EEPROM Address Overflow"
	default 0
	help
	  EEPROM chips that implement "address overflow" are ones
	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	  address and the extra bits end up in the "chip address" bit
	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
	  byte chips.

endif


endmenu
Commit	Line	Data
0b11dbf7 MY	1	#
	2	# Multifunction miscellaneous devices
	3	#
	4
	5	menu "Multifunction device drivers"
	6
4395e06e TC	7	config MISC
	8	bool "Enable Driver Model for Misc drivers"
	9	depends on DM
	10	help
	11	Enable driver model for miscellaneous devices. This class is
	12	used only for those do not fit other more general classes. A
	13	set of generic read, write and ioctl methods may be used to
	14	access the device.
	15
ca844dd8 TC	16	config ALTERA_SYSID
	17	bool "Altera Sysid support"
	18	depends on MISC
	19	help
	20	Select this to enable a sysid for Altera devices. Please find
	21	details on the "Embedded Peripherals IP User Guide" of Altera.
	22
aa5eb9a3 MB	23	config ATSHA204A
	24	bool "Support for Atmel ATSHA204A module"
	25	depends on MISC
	26	help
	27	Enable support for I2C connected Atmel's ATSHA204A
	28	CryptoAuthentication module found for example on the Turris Omnia
	29	board.
	30
49cd8e85 PT	31	config ROCKCHIP_EFUSE
	32	bool "Rockchip e-fuse support"
	33	depends on MISC
	34	help
	35	Enable (read-only) access for the e-fuse block found in Rockchip
	36	SoCs: accesses can either be made using byte addressing and a length
	37	or through child-nodes that are generated based on the e-fuse map
	38	retrieved from the DTS.
	39
	40	This driver currently supports the RK3399 only, but can easily be
	41	extended (by porting the read function from the Linux kernel sources)
	42	to support other recent Rockchip devices.
	43
6fb9ac15 SG	44	config CMD_CROS_EC
	45	bool "Enable crosec command"
	46	depends on CROS_EC
	47	help
	48	Enable command-line access to the Chrome OS EC (Embedded
	49	Controller). This provides the 'crosec' command which has
	50	a number of sub-commands for performing EC tasks such as
	51	updating its flash, accessing a small saved context area
	52	and talking to the I2C bus behind the EC (if there is one).
	53
	54	config CROS_EC
	55	bool "Enable Chrome OS EC"
	56	help
	57	Enable access to the Chrome OS EC. This is a separate
	58	microcontroller typically available on a SPI bus on Chromebooks. It
	59	provides access to the keyboard, some internal storage and may
	60	control access to the battery and main PMIC depending on the
	61	device. You can use the 'crosec' command to access it.
	62
	63	config CROS_EC_I2C
	64	bool "Enable Chrome OS EC I2C driver"
	65	depends on CROS_EC
	66	help
	67	Enable I2C access to the Chrome OS EC. This is used on older
	68	ARM Chromebooks such as snow and spring before the standard bus
	69	changed to SPI. The EC will accept commands across the I2C using
	70	a special message protocol, and provide responses.
	71
	72	config CROS_EC_LPC
	73	bool "Enable Chrome OS EC LPC driver"
	74	depends on CROS_EC
	75	help
	76	Enable I2C access to the Chrome OS EC. This is used on x86
	77	Chromebooks such as link and falco. The keyboard is provided
	78	through a legacy port interface, so on x86 machines the main
	79	function of the EC is power and thermal management.
	80
47cb8c65 SG	81	config CROS_EC_SANDBOX
	82	bool "Enable Chrome OS EC sandbox driver"
	83	depends on CROS_EC && SANDBOX
	84	help
	85	Enable a sandbox emulation of the Chrome OS EC. This supports
	86	keyboard (use the -l flag to enable the LCD), verified boot context,
	87	EC flash read/write/erase support and a few other things. It is
	88	enough to perform a Chrome OS verified boot on sandbox.
	89
6fb9ac15 SG	90	config CROS_EC_SPI
	91	bool "Enable Chrome OS EC SPI driver"
	92	depends on CROS_EC
	93	help
	94	Enable SPI access to the Chrome OS EC. This is used on newer
	95	ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
	96	provides a faster and more robust interface than I2C but the bugs
	97	are less interesting.
	98
879704d8 SG	99	config DS4510
	100	bool "Enable support for DS4510 CPU supervisor"
	101	help
	102	Enable support for the Maxim DS4510 CPU supervisor. It has an
	103	integrated 64-byte EEPROM, four programmable non-volatile I/O pins
	104	and a configurable timer for the supervisor function. The device is
	105	connected over I2C.
	106
c12e0d93	107	config FSL_SEC_MON
fe78378d	108	bool "Enable FSL SEC_MON Driver"
	109	help
	110	Freescale Security Monitor block is responsible for monitoring
	111	system states.
	112	Security Monitor can be transitioned on any security failures,
	113	like software violations or hardware security violations.
1cdd9412	114
3e020f03 PF	115	config MXC_OCOTP
	116	bool "Enable MXC OCOTP Driver"
	117	help
	118	If you say Y here, you will get support for the One Time
	119	Programmable memory pages that are stored on the some
	120	Freescale i.MX processors.
	121
4cf9e464 SR	122	config NUVOTON_NCT6102D
	123	bool "Enable Nuvoton NCT6102D Super I/O driver"
	124	help
	125	If you say Y here, you will get support for the Nuvoton
	126	NCT6102D Super I/O driver. This can be used to enable or
	127	disable the legacy UART, the watchdog or other devices
	128	in the Nuvoton Super IO chips on X86 platforms.
	129
5fd6badb SG	130	config PWRSEQ
	131	bool "Enable power-sequencing drivers"
	132	depends on DM
	133	help
	134	Power-sequencing drivers provide support for controlling power for
	135	devices. They are typically referenced by a phandle from another
	136	device. When the device is started up, its power sequence can be
	137	initiated.
	138
	139	config SPL_PWRSEQ
	140	bool "Enable power-sequencing drivers for SPL"
	141	depends on PWRSEQ
	142	help
	143	Power-sequencing drivers provide support for controlling power for
	144	devices. They are typically referenced by a phandle from another
	145	device. When the device is started up, its power sequence can be
	146	initiated.
	147
1cdd9412 SR	148	config PCA9551_LED
	149	bool "Enable PCA9551 LED driver"
	150	help
	151	Enable driver for PCA9551 LED controller. This controller
	152	is connected via I2C. So I2C needs to be enabled.
	153
	154	config PCA9551_I2C_ADDR
	155	hex "I2C address of PCA9551 LED controller"
	156	depends on PCA9551_LED
	157	default 0x60
	158	help
	159	The I2C address of the PCA9551 LED controller.
f9917454	160
4e280b91 CK	161	config STM32_RCC
	162	bool "Enable RCC driver for the STM32 SoC's family"
	163	depends on STM32 && MISC
	164	help
	165	Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
	166	block) is responsible of the management of the clock and reset
	167	generation.
	168	This driver is similar to an MFD driver in the Linux kernel.
	169
bd3ee84a SW	170	config TEGRA_CAR
	171	bool "Enable support for the Tegra CAR driver"
	172	depends on TEGRA_NO_BPMP
	173	help
	174	The Tegra CAR (Clock and Reset Controller) is a HW module that
	175	controls almost all clocks and resets in a Tegra SoC.
	176
73dd5c4c SW	177	config TEGRA186_BPMP
	178	bool "Enable support for the Tegra186 BPMP driver"
	179	depends on TEGRA186
	180	help
	181	The Tegra BPMP (Boot and Power Management Processor) is a separate
	182	auxiliary CPU embedded into Tegra to perform power management work,
	183	and controls related features such as clocks, resets, power domains,
	184	PMIC I2C bus, etc. This driver provides the core low-level
	185	communication path by which feature-specific drivers (such as clock)
	186	can make requests to the BPMP. This driver is similar to an MFD
	187	driver in the Linux kernel.
	188
85056932 SR	189	config WINBOND_W83627
	190	bool "Enable Winbond Super I/O driver"
	191	help
	192	If you say Y here, you will get support for the Winbond
	193	W83627 Super I/O driver. This can be used to enable the
	194	legacy UART or other devices in the Winbond Super IO chips
	195	on X86 platforms.
	196
fcf5c041 MY	197	config QFW
	198	bool
	199	help
	200	Hidden option to enable QEMU fw_cfg interface. This will be selected by
18686590	201	either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
fcf5c041	202
d7e28918	203	config I2C_EEPROM
	204	bool "Enable driver for generic I2C-attached EEPROMs"
	205	depends on MISC
	206	help
	207	Enable a generic driver for EEPROMs attached via I2C.
e3f24d4f	208
d81a1de9 WY	209
	210	config SPL_I2C_EEPROM
	211	bool "Enable driver for generic I2C-attached EEPROMs for SPL"
	212	depends on MISC && SPL && SPL_DM
	213	help
	214	This option is an SPL-variant of the I2C_EEPROM option.
	215	See the help of I2C_EEPROM for details.
	216
e3f24d4f AF	217	if I2C_EEPROM
	218
	219	config SYS_I2C_EEPROM_ADDR
	220	hex "Chip address of the EEPROM device"
	221	default 0
	222
	223	config SYS_I2C_EEPROM_BUS
	224	int "I2C bus of the EEPROM device."
	225	default 0
	226
	227	config SYS_EEPROM_SIZE
	228	int "Size in bytes of the EEPROM device"
	229	default 256
	230
	231	config SYS_EEPROM_PAGE_WRITE_BITS
	232	int "Number of bits used to address bytes in a single page"
	233	default 0
	234	help
	235	The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
	236	A 64 byte page, for example would require six bits.
	237
	238	config SYS_EEPROM_PAGE_WRITE_DELAY_MS
	239	int "Number of milliseconds to delay between page writes"
	240	default 0
	241
	242	config SYS_I2C_EEPROM_ADDR_LEN
	243	int "Length in bytes of the EEPROM memory array address"
	244	default 1
	245	help
	246	Note: This is NOT the chip address length!
	247
	248	config SYS_I2C_EEPROM_ADDR_OVERFLOW
	249	hex "EEPROM Address Overflow"
	250	default 0
	251	help
	252	EEPROM chips that implement "address overflow" are ones
	253	like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	254	address and the extra bits end up in the "chip address" bit
	255	slots. This makes a 24WC08 (1Kbyte) chip look like four 256
	256	byte chips.
	257
	258	endif
	259
	260
0b11dbf7	261	endmenu