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Commit | Line | Data |
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0b11dbf7 MY |
1 | # |
2 | # Multifunction miscellaneous devices | |
3 | # | |
4 | ||
5 | menu "Multifunction device drivers" | |
6 | ||
4395e06e TC |
7 | config MISC |
8 | bool "Enable Driver Model for Misc drivers" | |
9 | depends on DM | |
10 | help | |
11 | Enable driver model for miscellaneous devices. This class is | |
12 | used only for those do not fit other more general classes. A | |
13 | set of generic read, write and ioctl methods may be used to | |
14 | access the device. | |
15 | ||
ca844dd8 TC |
16 | config ALTERA_SYSID |
17 | bool "Altera Sysid support" | |
18 | depends on MISC | |
19 | help | |
20 | Select this to enable a sysid for Altera devices. Please find | |
21 | details on the "Embedded Peripherals IP User Guide" of Altera. | |
22 | ||
6fb9ac15 SG |
23 | config CMD_CROS_EC |
24 | bool "Enable crosec command" | |
25 | depends on CROS_EC | |
26 | help | |
27 | Enable command-line access to the Chrome OS EC (Embedded | |
28 | Controller). This provides the 'crosec' command which has | |
29 | a number of sub-commands for performing EC tasks such as | |
30 | updating its flash, accessing a small saved context area | |
31 | and talking to the I2C bus behind the EC (if there is one). | |
32 | ||
33 | config CROS_EC | |
34 | bool "Enable Chrome OS EC" | |
35 | help | |
36 | Enable access to the Chrome OS EC. This is a separate | |
37 | microcontroller typically available on a SPI bus on Chromebooks. It | |
38 | provides access to the keyboard, some internal storage and may | |
39 | control access to the battery and main PMIC depending on the | |
40 | device. You can use the 'crosec' command to access it. | |
41 | ||
42 | config CROS_EC_I2C | |
43 | bool "Enable Chrome OS EC I2C driver" | |
44 | depends on CROS_EC | |
45 | help | |
46 | Enable I2C access to the Chrome OS EC. This is used on older | |
47 | ARM Chromebooks such as snow and spring before the standard bus | |
48 | changed to SPI. The EC will accept commands across the I2C using | |
49 | a special message protocol, and provide responses. | |
50 | ||
51 | config CROS_EC_LPC | |
52 | bool "Enable Chrome OS EC LPC driver" | |
53 | depends on CROS_EC | |
54 | help | |
55 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
56 | Chromebooks such as link and falco. The keyboard is provided | |
57 | through a legacy port interface, so on x86 machines the main | |
58 | function of the EC is power and thermal management. | |
59 | ||
47cb8c65 SG |
60 | config CROS_EC_SANDBOX |
61 | bool "Enable Chrome OS EC sandbox driver" | |
62 | depends on CROS_EC && SANDBOX | |
63 | help | |
64 | Enable a sandbox emulation of the Chrome OS EC. This supports | |
65 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
66 | EC flash read/write/erase support and a few other things. It is | |
67 | enough to perform a Chrome OS verified boot on sandbox. | |
68 | ||
6fb9ac15 SG |
69 | config CROS_EC_SPI |
70 | bool "Enable Chrome OS EC SPI driver" | |
71 | depends on CROS_EC | |
72 | help | |
73 | Enable SPI access to the Chrome OS EC. This is used on newer | |
74 | ARM Chromebooks such as pit, pi and nyan-big. The SPI interface | |
75 | provides a faster and more robust interface than I2C but the bugs | |
76 | are less interesting. | |
77 | ||
c12e0d93 | 78 | config FSL_SEC_MON |
fe78378d | 79 | bool "Enable FSL SEC_MON Driver" |
80 | help | |
81 | Freescale Security Monitor block is responsible for monitoring | |
82 | system states. | |
83 | Security Monitor can be transitioned on any security failures, | |
84 | like software violations or hardware security violations. | |
1cdd9412 | 85 | |
3e020f03 PF |
86 | config MXC_OCOTP |
87 | bool "Enable MXC OCOTP Driver" | |
88 | help | |
89 | If you say Y here, you will get support for the One Time | |
90 | Programmable memory pages that are stored on the some | |
91 | Freescale i.MX processors. | |
92 | ||
5fd6badb SG |
93 | config PWRSEQ |
94 | bool "Enable power-sequencing drivers" | |
95 | depends on DM | |
96 | help | |
97 | Power-sequencing drivers provide support for controlling power for | |
98 | devices. They are typically referenced by a phandle from another | |
99 | device. When the device is started up, its power sequence can be | |
100 | initiated. | |
101 | ||
102 | config SPL_PWRSEQ | |
103 | bool "Enable power-sequencing drivers for SPL" | |
104 | depends on PWRSEQ | |
105 | help | |
106 | Power-sequencing drivers provide support for controlling power for | |
107 | devices. They are typically referenced by a phandle from another | |
108 | device. When the device is started up, its power sequence can be | |
109 | initiated. | |
110 | ||
1cdd9412 SR |
111 | config PCA9551_LED |
112 | bool "Enable PCA9551 LED driver" | |
113 | help | |
114 | Enable driver for PCA9551 LED controller. This controller | |
115 | is connected via I2C. So I2C needs to be enabled. | |
116 | ||
117 | config PCA9551_I2C_ADDR | |
118 | hex "I2C address of PCA9551 LED controller" | |
119 | depends on PCA9551_LED | |
120 | default 0x60 | |
121 | help | |
122 | The I2C address of the PCA9551 LED controller. | |
f9917454 | 123 | |
85056932 SR |
124 | config WINBOND_W83627 |
125 | bool "Enable Winbond Super I/O driver" | |
126 | help | |
127 | If you say Y here, you will get support for the Winbond | |
128 | W83627 Super I/O driver. This can be used to enable the | |
129 | legacy UART or other devices in the Winbond Super IO chips | |
130 | on X86 platforms. | |
131 | ||
fcf5c041 MY |
132 | config QFW |
133 | bool | |
134 | help | |
135 | Hidden option to enable QEMU fw_cfg interface. This will be selected by | |
18686590 | 136 | either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. |
fcf5c041 | 137 | |
d7e28918 | 138 | config I2C_EEPROM |
139 | bool "Enable driver for generic I2C-attached EEPROMs" | |
140 | depends on MISC | |
141 | help | |
142 | Enable a generic driver for EEPROMs attached via I2C. | |
0b11dbf7 | 143 | endmenu |