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112fd2ec BT |
1 | /* |
2 | * (C) Copyright 2013 ADVANSEE | |
3 | * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | |
4 | * | |
5 | * Based on Dirk Behme's | |
6 | * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c, | |
7 | * which is based on Freescale's | |
8 | * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6, | |
9 | * which is: | |
10 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
11 | * | |
1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
112fd2ec BT |
13 | */ |
14 | ||
15 | #include <common.h> | |
16 | #include <fuse.h> | |
1221ce45 | 17 | #include <linux/errno.h> |
112fd2ec BT |
18 | #include <asm/io.h> |
19 | #include <asm/arch/clock.h> | |
20 | #include <asm/arch/imx-regs.h> | |
552a848e | 21 | #include <asm/mach-imx/sys_proto.h> |
112fd2ec BT |
22 | |
23 | #define BO_CTRL_WR_UNLOCK 16 | |
24 | #define BM_CTRL_WR_UNLOCK 0xffff0000 | |
25 | #define BV_CTRL_WR_UNLOCK_KEY 0x3e77 | |
26 | #define BM_CTRL_ERROR 0x00000200 | |
27 | #define BM_CTRL_BUSY 0x00000100 | |
28 | #define BO_CTRL_ADDR 0 | |
42c91c10 AA |
29 | #ifdef CONFIG_MX7 |
30 | #define BM_CTRL_ADDR 0x0000000f | |
31 | #define BM_CTRL_RELOAD 0x00000400 | |
3ca0f0d2 PF |
32 | #elif defined(CONFIG_MX7ULP) |
33 | #define BM_CTRL_ADDR 0x000000FF | |
34 | #define BM_CTRL_RELOAD 0x00000400 | |
35 | #define BM_OUT_STATUS_DED 0x00000400 | |
36 | #define BM_OUT_STATUS_LOCKED 0x00000800 | |
37 | #define BM_OUT_STATUS_PROGFAIL 0x00001000 | |
8a099b68 PF |
38 | #elif defined(CONFIG_MX8M) |
39 | #define BM_CTRL_ADDR 0x000000ff | |
42c91c10 | 40 | #else |
112fd2ec | 41 | #define BM_CTRL_ADDR 0x0000007f |
42c91c10 AA |
42 | #endif |
43 | ||
44 | #ifdef CONFIG_MX7 | |
45 | #define BO_TIMING_FSOURCE 12 | |
46 | #define BM_TIMING_FSOURCE 0x0007f000 | |
47 | #define BV_TIMING_FSOURCE_NS 1001 | |
48 | #define BO_TIMING_PROG 0 | |
49 | #define BM_TIMING_PROG 0x00000fff | |
50 | #define BV_TIMING_PROG_US 10 | |
51 | #else | |
112fd2ec BT |
52 | #define BO_TIMING_STROBE_READ 16 |
53 | #define BM_TIMING_STROBE_READ 0x003f0000 | |
54 | #define BV_TIMING_STROBE_READ_NS 37 | |
55 | #define BO_TIMING_RELAX 12 | |
56 | #define BM_TIMING_RELAX 0x0000f000 | |
57 | #define BV_TIMING_RELAX_NS 17 | |
58 | #define BO_TIMING_STROBE_PROG 0 | |
59 | #define BM_TIMING_STROBE_PROG 0x00000fff | |
60 | #define BV_TIMING_STROBE_PROG_US 10 | |
42c91c10 | 61 | #endif |
112fd2ec BT |
62 | |
63 | #define BM_READ_CTRL_READ_FUSE 0x00000001 | |
64 | ||
65 | #define BF(value, field) (((value) << BO_##field) & BM_##field) | |
66 | ||
67 | #define WRITE_POSTAMBLE_US 2 | |
68 | ||
7296a023 PF |
69 | #if defined(CONFIG_MX6) || defined(CONFIG_VF610) |
70 | #define FUSE_BANK_SIZE 0x80 | |
71 | #ifdef CONFIG_MX6SL | |
72 | #define FUSE_BANKS 8 | |
b2ebdd85 | 73 | #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) |
f8b95731 | 74 | #define FUSE_BANKS 9 |
7296a023 PF |
75 | #else |
76 | #define FUSE_BANKS 16 | |
77 | #endif | |
78 | #elif defined CONFIG_MX7 | |
79 | #define FUSE_BANK_SIZE 0x40 | |
80 | #define FUSE_BANKS 16 | |
3ca0f0d2 PF |
81 | #elif defined(CONFIG_MX7ULP) |
82 | #define FUSE_BANK_SIZE 0x80 | |
83 | #define FUSE_BANKS 31 | |
8a099b68 PF |
84 | #elif defined(CONFIG_MX8M) |
85 | #define FUSE_BANK_SIZE 0x40 | |
86 | #define FUSE_BANKS 64 | |
7296a023 PF |
87 | #else |
88 | #error "Unsupported architecture\n" | |
89 | #endif | |
90 | ||
91 | #if defined(CONFIG_MX6) | |
7296a023 PF |
92 | |
93 | /* | |
94 | * There is a hole in shadow registers address map of size 0x100 | |
f8b95731 | 95 | * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX, |
b2ebdd85 | 96 | * iMX6UL, i.MX6ULL and i.MX6SLL. |
7296a023 PF |
97 | * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, |
98 | * we should account for this hole in address space. | |
99 | * | |
100 | * Similar hole exists between bank 14 and bank 15 of size | |
101 | * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. | |
102 | * Note: iMX6SL has only 0-7 banks and there is no hole. | |
103 | * Note: iMX6UL doesn't have this one. | |
104 | * | |
105 | * This function is to covert user input to physical bank index. | |
106 | * Only needed when read fuse, because we use register offset, so | |
107 | * need to calculate real register offset. | |
108 | * When write, no need to consider hole, always use the bank/word | |
109 | * index from fuse map. | |
110 | */ | |
111 | u32 fuse_bank_physical(int index) | |
112 | { | |
113 | u32 phy_index; | |
114 | ||
3ca0f0d2 | 115 | if (is_mx6sl() || is_mx7ulp()) { |
7296a023 | 116 | phy_index = index; |
b2ebdd85 PF |
117 | } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { |
118 | if ((is_mx6ull() || is_mx6sll()) && index == 8) | |
f8b95731 PF |
119 | index = 7; |
120 | ||
7296a023 PF |
121 | if (index >= 6) |
122 | phy_index = fuse_bank_physical(5) + (index - 6) + 3; | |
123 | else | |
124 | phy_index = index; | |
125 | } else { | |
126 | if (index >= 15) | |
127 | phy_index = fuse_bank_physical(14) + (index - 15) + 2; | |
128 | else if (index >= 6) | |
129 | phy_index = fuse_bank_physical(5) + (index - 6) + 3; | |
130 | else | |
131 | phy_index = index; | |
132 | } | |
133 | return phy_index; | |
134 | } | |
f8b95731 PF |
135 | |
136 | u32 fuse_word_physical(u32 bank, u32 word_index) | |
137 | { | |
b2ebdd85 | 138 | if (is_mx6ull() || is_mx6sll()) { |
f8b95731 PF |
139 | if (bank == 8) |
140 | word_index = word_index + 4; | |
141 | } | |
142 | ||
143 | return word_index; | |
144 | } | |
7296a023 PF |
145 | #else |
146 | u32 fuse_bank_physical(int index) | |
147 | { | |
148 | return index; | |
149 | } | |
f8b95731 PF |
150 | |
151 | u32 fuse_word_physical(u32 bank, u32 word_index) | |
152 | { | |
153 | return word_index; | |
154 | } | |
155 | ||
7296a023 PF |
156 | #endif |
157 | ||
112fd2ec BT |
158 | static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) |
159 | { | |
160 | while (readl(®s->ctrl) & BM_CTRL_BUSY) | |
161 | udelay(delay_us); | |
162 | } | |
163 | ||
164 | static void clear_error(struct ocotp_regs *regs) | |
165 | { | |
166 | writel(BM_CTRL_ERROR, ®s->ctrl_clr); | |
167 | } | |
168 | ||
169 | static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, | |
170 | int assert, const char *caller) | |
171 | { | |
172 | *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
173 | ||
7296a023 PF |
174 | if (bank >= FUSE_BANKS || |
175 | word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || | |
176 | !assert) { | |
112fd2ec BT |
177 | printf("mxc_ocotp %s(): Invalid argument\n", caller); |
178 | return -EINVAL; | |
179 | } | |
180 | ||
b2ebdd85 | 181 | if (is_mx6ull() || is_mx6sll()) { |
f8b95731 PF |
182 | if ((bank == 7 || bank == 8) && |
183 | word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { | |
b2ebdd85 | 184 | printf("mxc_ocotp %s(): Invalid argument\n", caller); |
f8b95731 PF |
185 | return -EINVAL; |
186 | } | |
187 | } | |
188 | ||
112fd2ec BT |
189 | enable_ocotp_clk(1); |
190 | ||
191 | wait_busy(*regs, 1); | |
192 | clear_error(*regs); | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | static int finish_access(struct ocotp_regs *regs, const char *caller) | |
198 | { | |
199 | u32 err; | |
200 | ||
201 | err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); | |
202 | clear_error(regs); | |
203 | ||
3ca0f0d2 PF |
204 | #ifdef CONFIG_MX7ULP |
205 | /* Need to power down the OTP memory */ | |
206 | writel(1, ®s->pdn); | |
207 | #endif | |
112fd2ec BT |
208 | if (err) { |
209 | printf("mxc_ocotp %s(): Access protect error\n", caller); | |
210 | return -EIO; | |
211 | } | |
212 | ||
213 | return 0; | |
214 | } | |
215 | ||
216 | static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val, | |
217 | const char *caller) | |
218 | { | |
219 | return prepare_access(regs, bank, word, val != NULL, caller); | |
220 | } | |
221 | ||
222 | int fuse_read(u32 bank, u32 word, u32 *val) | |
223 | { | |
224 | struct ocotp_regs *regs; | |
225 | int ret; | |
7296a023 | 226 | u32 phy_bank; |
f8b95731 | 227 | u32 phy_word; |
112fd2ec BT |
228 | |
229 | ret = prepare_read(®s, bank, word, val, __func__); | |
230 | if (ret) | |
231 | return ret; | |
232 | ||
7296a023 | 233 | phy_bank = fuse_bank_physical(bank); |
f8b95731 | 234 | phy_word = fuse_word_physical(bank, word); |
7296a023 | 235 | |
f8b95731 | 236 | *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]); |
112fd2ec | 237 | |
3ca0f0d2 PF |
238 | #ifdef CONFIG_MX7ULP |
239 | if (readl(®s->out_status) & BM_OUT_STATUS_DED) { | |
240 | writel(BM_OUT_STATUS_DED, ®s->out_status_clr); | |
241 | printf("mxc_ocotp %s(): fuse read wrong\n", __func__); | |
242 | return -EIO; | |
243 | } | |
244 | #endif | |
112fd2ec BT |
245 | return finish_access(regs, __func__); |
246 | } | |
247 | ||
42c91c10 AA |
248 | #ifdef CONFIG_MX7 |
249 | static void set_timing(struct ocotp_regs *regs) | |
250 | { | |
251 | u32 ipg_clk; | |
252 | u32 fsource, prog; | |
253 | u32 timing; | |
254 | ||
255 | ipg_clk = mxc_get_clock(MXC_IPG_CLK); | |
256 | ||
257 | fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS, | |
258 | + 1000000) + 1; | |
259 | prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1; | |
260 | ||
261 | timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG); | |
262 | ||
263 | clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG, | |
264 | timing); | |
265 | } | |
3ca0f0d2 PF |
266 | #elif defined(CONFIG_MX7ULP) |
267 | static void set_timing(struct ocotp_regs *regs) | |
268 | { | |
269 | /* No timing set for MX7ULP */ | |
270 | } | |
271 | ||
42c91c10 | 272 | #else |
112fd2ec BT |
273 | static void set_timing(struct ocotp_regs *regs) |
274 | { | |
275 | u32 ipg_clk; | |
276 | u32 relax, strobe_read, strobe_prog; | |
277 | u32 timing; | |
278 | ||
279 | ipg_clk = mxc_get_clock(MXC_IPG_CLK); | |
280 | ||
281 | relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; | |
282 | strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, | |
283 | 1000000000) + 2 * (relax + 1) - 1; | |
4515992f MY |
284 | strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US, |
285 | 1000000) + 2 * (relax + 1) - 1; | |
112fd2ec BT |
286 | |
287 | timing = BF(strobe_read, TIMING_STROBE_READ) | | |
288 | BF(relax, TIMING_RELAX) | | |
289 | BF(strobe_prog, TIMING_STROBE_PROG); | |
290 | ||
291 | clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX | | |
292 | BM_TIMING_STROBE_PROG, timing); | |
293 | } | |
42c91c10 | 294 | #endif |
112fd2ec BT |
295 | |
296 | static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, | |
297 | int write) | |
298 | { | |
299 | u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; | |
42c91c10 AA |
300 | #ifdef CONFIG_MX7 |
301 | u32 addr = bank; | |
8a099b68 PF |
302 | #elif defined CONFIG_MX8M |
303 | u32 addr = bank << 2 | word; | |
42c91c10 | 304 | #else |
f8b95731 PF |
305 | u32 addr; |
306 | /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */ | |
b2ebdd85 | 307 | if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) { |
f8b95731 PF |
308 | bank = bank - 1; |
309 | word += 4; | |
310 | } | |
311 | addr = bank << 3 | word; | |
42c91c10 | 312 | #endif |
112fd2ec BT |
313 | |
314 | set_timing(regs); | |
315 | clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR, | |
316 | BF(wr_unlock, CTRL_WR_UNLOCK) | | |
317 | BF(addr, CTRL_ADDR)); | |
318 | } | |
319 | ||
320 | int fuse_sense(u32 bank, u32 word, u32 *val) | |
321 | { | |
322 | struct ocotp_regs *regs; | |
323 | int ret; | |
324 | ||
325 | ret = prepare_read(®s, bank, word, val, __func__); | |
326 | if (ret) | |
327 | return ret; | |
328 | ||
329 | setup_direct_access(regs, bank, word, false); | |
330 | writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl); | |
331 | wait_busy(regs, 1); | |
42c91c10 AA |
332 | #ifdef CONFIG_MX7 |
333 | *val = readl((®s->read_fuse_data0) + (word << 2)); | |
334 | #else | |
112fd2ec | 335 | *val = readl(®s->read_fuse_data); |
42c91c10 | 336 | #endif |
112fd2ec | 337 | |
3ca0f0d2 PF |
338 | #ifdef CONFIG_MX7ULP |
339 | if (readl(®s->out_status) & BM_OUT_STATUS_DED) { | |
340 | writel(BM_OUT_STATUS_DED, ®s->out_status_clr); | |
341 | printf("mxc_ocotp %s(): fuse read wrong\n", __func__); | |
342 | return -EIO; | |
343 | } | |
344 | #endif | |
345 | ||
112fd2ec BT |
346 | return finish_access(regs, __func__); |
347 | } | |
348 | ||
349 | static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, | |
350 | const char *caller) | |
351 | { | |
8df42bee PF |
352 | #ifdef CONFIG_MX7ULP |
353 | u32 val; | |
354 | int ret; | |
355 | ||
356 | /* Only bank 0 and 1 are redundancy mode, others are ECC mode */ | |
357 | if (bank != 0 && bank != 1) { | |
358 | ret = fuse_sense(bank, word, &val); | |
359 | if (ret) | |
360 | return ret; | |
361 | ||
362 | if (val != 0) { | |
363 | printf("mxc_ocotp: The word has been programmed, no more write\n"); | |
364 | return -EPERM; | |
365 | } | |
366 | } | |
367 | #endif | |
368 | ||
112fd2ec BT |
369 | return prepare_access(regs, bank, word, true, caller); |
370 | } | |
371 | ||
372 | int fuse_prog(u32 bank, u32 word, u32 val) | |
373 | { | |
374 | struct ocotp_regs *regs; | |
375 | int ret; | |
376 | ||
377 | ret = prepare_write(®s, bank, word, __func__); | |
378 | if (ret) | |
379 | return ret; | |
380 | ||
381 | setup_direct_access(regs, bank, word, true); | |
42c91c10 AA |
382 | #ifdef CONFIG_MX7 |
383 | switch (word) { | |
384 | case 0: | |
385 | writel(0, ®s->data1); | |
386 | writel(0, ®s->data2); | |
387 | writel(0, ®s->data3); | |
388 | writel(val, ®s->data0); | |
389 | break; | |
390 | case 1: | |
391 | writel(val, ®s->data1); | |
392 | writel(0, ®s->data2); | |
393 | writel(0, ®s->data3); | |
394 | writel(0, ®s->data0); | |
395 | break; | |
396 | case 2: | |
397 | writel(0, ®s->data1); | |
398 | writel(val, ®s->data2); | |
399 | writel(0, ®s->data3); | |
400 | writel(0, ®s->data0); | |
401 | break; | |
402 | case 3: | |
403 | writel(0, ®s->data1); | |
404 | writel(0, ®s->data2); | |
405 | writel(val, ®s->data3); | |
406 | writel(0, ®s->data0); | |
407 | break; | |
408 | } | |
409 | wait_busy(regs, BV_TIMING_PROG_US); | |
410 | #else | |
112fd2ec BT |
411 | writel(val, ®s->data); |
412 | wait_busy(regs, BV_TIMING_STROBE_PROG_US); | |
42c91c10 | 413 | #endif |
112fd2ec BT |
414 | udelay(WRITE_POSTAMBLE_US); |
415 | ||
3ca0f0d2 PF |
416 | #ifdef CONFIG_MX7ULP |
417 | if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { | |
418 | writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); | |
419 | printf("mxc_ocotp %s(): fuse write is failed\n", __func__); | |
420 | return -EIO; | |
421 | } | |
422 | #endif | |
423 | ||
112fd2ec BT |
424 | return finish_access(regs, __func__); |
425 | } | |
426 | ||
427 | int fuse_override(u32 bank, u32 word, u32 val) | |
428 | { | |
429 | struct ocotp_regs *regs; | |
430 | int ret; | |
7296a023 | 431 | u32 phy_bank; |
f8b95731 | 432 | u32 phy_word; |
112fd2ec BT |
433 | |
434 | ret = prepare_write(®s, bank, word, __func__); | |
435 | if (ret) | |
436 | return ret; | |
437 | ||
7296a023 | 438 | phy_bank = fuse_bank_physical(bank); |
f8b95731 | 439 | phy_word = fuse_word_physical(bank, word); |
7296a023 | 440 | |
f8b95731 | 441 | writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]); |
112fd2ec | 442 | |
3ca0f0d2 PF |
443 | #ifdef CONFIG_MX7ULP |
444 | if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { | |
445 | writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); | |
446 | printf("mxc_ocotp %s(): fuse write is failed\n", __func__); | |
447 | return -EIO; | |
448 | } | |
449 | #endif | |
450 | ||
112fd2ec BT |
451 | return finish_access(regs, __func__); |
452 | } |