[people/ms/u-boot.git] / drivers / mmc / arm_pl180_mmci.h

/*
 * ARM PrimeCell MultiMedia Card Interface - PL180
 *
 * Copyright (C) ST-Ericsson SA 2010
 *
 * Author: Ulf Hansson <ulf.hansson@stericsson.com>
 * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
 * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ARM_PL180_MMCI_H__
#define __ARM_PL180_MMCI_H__

/* need definition of struct mmc_config */
#include <mmc.h>

#define COMMAND_REG_DELAY	300
#define DATA_REG_DELAY		1000
#define CLK_CHANGE_DELAY	2000

#define INIT_PWR		0xBF /* Power on, full power, not open drain */
#define ARM_MCLK		(100*1000*1000)

/* SDI Power Control register bits */
#define SDI_PWR_PWRCTRL_MASK	0x00000003
#define SDI_PWR_PWRCTRL_ON	0x00000003
#define SDI_PWR_PWRCTRL_OFF	0x00000000
#define SDI_PWR_DAT2DIREN	0x00000004
#define SDI_PWR_CMDDIREN	0x00000008
#define SDI_PWR_DAT0DIREN	0x00000010
#define SDI_PWR_DAT31DIREN	0x00000020
#define SDI_PWR_OPD		0x00000040
#define SDI_PWR_FBCLKEN		0x00000080
#define SDI_PWR_DAT74DIREN	0x00000100
#define SDI_PWR_RSTEN		0x00000200

#define VOLTAGE_WINDOW_MMC	0x00FF8080
#define VOLTAGE_WINDOW_SD	0x80010000

/* SDI clock control register bits */
#define SDI_CLKCR_CLKDIV_MASK	0x000000FF
#define SDI_CLKCR_CLKEN		0x00000100
#define SDI_CLKCR_PWRSAV	0x00000200
#define SDI_CLKCR_BYPASS	0x00000400
#define SDI_CLKCR_WIDBUS_MASK	0x00001800
#define SDI_CLKCR_WIDBUS_1	0x00000000
#define SDI_CLKCR_WIDBUS_4	0x00000800
/* V2 only */
#define SDI_CLKCR_WIDBUS_8	0x00001000
#define SDI_CLKCR_NEDGE		0x00002000
#define SDI_CLKCR_HWFC_EN	0x00004000

#define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
#define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD

/* SDI command register bits */
#define SDI_CMD_CMDINDEX_MASK	0x000000FF
#define SDI_CMD_WAITRESP	0x00000040
#define SDI_CMD_LONGRESP	0x00000080
#define SDI_CMD_WAITINT		0x00000100
#define SDI_CMD_WAITPEND	0x00000200
#define SDI_CMD_CPSMEN		0x00000400
#define SDI_CMD_SDIOSUSPEND	0x00000800
#define SDI_CMD_ENDCMDCOMPL	0x00001000
#define SDI_CMD_NIEN		0x00002000
#define SDI_CMD_CE_ATACMD	0x00004000
#define SDI_CMD_CBOOTMODEEN	0x00008000

#define SDI_DTIMER_DEFAULT	0xFFFF0000

/* SDI Status register bits */
#define SDI_STA_CCRCFAIL	0x00000001
#define SDI_STA_DCRCFAIL	0x00000002
#define SDI_STA_CTIMEOUT	0x00000004
#define SDI_STA_DTIMEOUT	0x00000008
#define SDI_STA_TXUNDERR	0x00000010
#define SDI_STA_RXOVERR		0x00000020
#define SDI_STA_CMDREND		0x00000040
#define SDI_STA_CMDSENT		0x00000080
#define SDI_STA_DATAEND		0x00000100
#define SDI_STA_STBITERR	0x00000200
#define SDI_STA_DBCKEND		0x00000400
#define SDI_STA_CMDACT		0x00000800
#define SDI_STA_TXACT		0x00001000
#define SDI_STA_RXACT		0x00002000
#define SDI_STA_TXFIFOBW	0x00004000
#define SDI_STA_RXFIFOBR	0x00008000
#define SDI_STA_TXFIFOF		0x00010000
#define SDI_STA_RXFIFOF		0x00020000
#define SDI_STA_TXFIFOE		0x00040000
#define SDI_STA_RXFIFOE		0x00080000
#define SDI_STA_TXDAVL		0x00100000
#define SDI_STA_RXDAVL		0x00200000
#define SDI_STA_SDIOIT		0x00400000
#define SDI_STA_CEATAEND	0x00800000
#define SDI_STA_CARDBUSY	0x01000000
#define SDI_STA_BOOTMODE	0x02000000
#define SDI_STA_BOOTACKERR	0x04000000
#define SDI_STA_BOOTACKTIMEOUT	0x08000000
#define SDI_STA_RSTNEND		0x10000000

/* SDI Interrupt Clear register bits */
#define SDI_ICR_MASK		0x1DC007FF
#define SDI_ICR_CCRCFAILC	0x00000001
#define SDI_ICR_DCRCFAILC	0x00000002
#define SDI_ICR_CTIMEOUTC	0x00000004
#define SDI_ICR_DTIMEOUTC	0x00000008
#define SDI_ICR_TXUNDERRC	0x00000010
#define SDI_ICR_RXOVERRC	0x00000020
#define SDI_ICR_CMDRENDC	0x00000040
#define SDI_ICR_CMDSENTC	0x00000080
#define SDI_ICR_DATAENDC	0x00000100
#define SDI_ICR_STBITERRC	0x00000200
#define SDI_ICR_DBCKENDC	0x00000400
#define SDI_ICR_SDIOITC		0x00400000
#define SDI_ICR_CEATAENDC	0x00800000
#define SDI_ICR_BUSYENDC	0x01000000
#define SDI_ICR_BOOTACKERRC	0x04000000
#define SDI_ICR_BOOTACKTIMEOUTC	0x08000000
#define SDI_ICR_RSTNENDC	0x10000000

#define SDI_MASK0_MASK		0x1FFFFFFF

/* SDI Data control register bits */
#define SDI_DCTRL_DTEN		0x00000001
#define SDI_DCTRL_DTDIR_IN	0x00000002
#define SDI_DCTRL_DTMODE_STREAM	0x00000004
#define SDI_DCTRL_DMAEN		0x00000008
#define SDI_DCTRL_DBLKSIZE_MASK	0x000000F0
#define SDI_DCTRL_RWSTART	0x00000100
#define SDI_DCTRL_RWSTOP	0x00000200
#define SDI_DCTRL_RWMOD		0x00000200
#define SDI_DCTRL_SDIOEN	0x00000800
#define SDI_DCTRL_DMAREQCTL	0x00001000
#define SDI_DCTRL_DBOOTMODEEN	0x00002000
#define SDI_DCTRL_BUSYMODE	0x00004000
#define SDI_DCTRL_DDR_MODE	0x00008000
#define SDI_DCTRL_DBLOCKSIZE_V2_MASK   0x7fff0000
#define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT  16

#define SDI_FIFO_BURST_SIZE	8

#define VERSION1	false
#define VERSION2	true

struct sdi_registers {
	u32 power;		/* 0x00*/
	u32 clock;		/* 0x04*/
	u32 argument;		/* 0x08*/
	u32 command;		/* 0x0c*/
	u32 respcommand;	/* 0x10*/
	u32 response0;		/* 0x14*/
	u32 response1;		/* 0x18*/
	u32 response2;		/* 0x1c*/
	u32 response3;		/* 0x20*/
	u32 datatimer;		/* 0x24*/
	u32 datalength;		/* 0x28*/
	u32 datactrl;		/* 0x2c*/
	u32 datacount;		/* 0x30*/
	u32 status;		/* 0x34*/
	u32 status_clear;	/* 0x38*/
	u32 mask0;		/* 0x3c*/
	u32 mask1;		/* 0x40*/
	u32 card_select;	/* 0x44*/
	u32 fifo_count;		/* 0x48*/
	u32 padding1[(0x80-0x4C)>>2];
	u32 fifo;		/* 0x80*/
	u32 padding2[(0xFE0-0x84)>>2];
	u32 periph_id0;		/* 0xFE0 mmc Peripheral Identifcation Register*/
	u32 periph_id1;		/* 0xFE4*/
	u32 periph_id2;		/* 0xFE8*/
	u32 periph_id3;		/* 0xFEC*/
	u32 pcell_id0;		/* 0xFF0*/
	u32 pcell_id1;		/* 0xFF4*/
	u32 pcell_id2;		/* 0xFF8*/
	u32 pcell_id3;		/* 0xFFC*/
};

struct pl180_mmc_host {
	struct sdi_registers *base;
	char name[32];
	unsigned int b_max;
	unsigned int voltages;
	unsigned int caps;
	unsigned int clock_in;
	unsigned int clock_min;
	unsigned int clock_max;
	unsigned int clkdiv_init;
	unsigned int pwr_init;
	int version2;
	struct mmc_config cfg;
#ifdef CONFIG_DM_MMC
	struct gpio_desc cd_gpio;
	bool cd_inverted;
#endif
};

int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc);

#endif
Commit	Line	Data
23b93e1d MW	1	/*
	2	* ARM PrimeCell MultiMedia Card Interface - PL180
	3	*
	4	* Copyright (C) ST-Ericsson SA 2010
	5	*
	6	* Author: Ulf Hansson <ulf.hansson@stericsson.com>
	7	* Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
	8	* Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
23b93e1d MW	11	*/
	12
	13	#ifndef __ARM_PL180_MMCI_H__
	14	#define __ARM_PL180_MMCI_H__
	15
93bfd616 PA	16	/* need definition of struct mmc_config */
	17	#include <mmc.h>
	18
23b93e1d MW	19	#define COMMAND_REG_DELAY 300
	20	#define DATA_REG_DELAY 1000
	21	#define CLK_CHANGE_DELAY 2000
	22
	23	#define INIT_PWR 0xBF /* Power on, full power, not open drain */
	24	#define ARM_MCLK (10010001000)
	25
	26	/* SDI Power Control register bits */
	27	#define SDI_PWR_PWRCTRL_MASK 0x00000003
	28	#define SDI_PWR_PWRCTRL_ON 0x00000003
	29	#define SDI_PWR_PWRCTRL_OFF 0x00000000
	30	#define SDI_PWR_DAT2DIREN 0x00000004
	31	#define SDI_PWR_CMDDIREN 0x00000008
	32	#define SDI_PWR_DAT0DIREN 0x00000010
	33	#define SDI_PWR_DAT31DIREN 0x00000020
	34	#define SDI_PWR_OPD 0x00000040
	35	#define SDI_PWR_FBCLKEN 0x00000080
	36	#define SDI_PWR_DAT74DIREN 0x00000100
	37	#define SDI_PWR_RSTEN 0x00000200
	38
	39	#define VOLTAGE_WINDOW_MMC 0x00FF8080
	40	#define VOLTAGE_WINDOW_SD 0x80010000
	41
	42	/* SDI clock control register bits */
	43	#define SDI_CLKCR_CLKDIV_MASK 0x000000FF
	44	#define SDI_CLKCR_CLKEN 0x00000100
	45	#define SDI_CLKCR_PWRSAV 0x00000200
	46	#define SDI_CLKCR_BYPASS 0x00000400
	47	#define SDI_CLKCR_WIDBUS_MASK 0x00001800
	48	#define SDI_CLKCR_WIDBUS_1 0x00000000
	49	#define SDI_CLKCR_WIDBUS_4 0x00000800
10ed93dc JR	50	/* V2 only */
	51	#define SDI_CLKCR_WIDBUS_8 0x00001000
	52	#define SDI_CLKCR_NEDGE 0x00002000
	53	#define SDI_CLKCR_HWFC_EN 0x00004000
23b93e1d	54
10ed93dc JR	55	#define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2(0xC6+1)) => 505KHz /
10ed93dc JR	56	#define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD
23b93e1d MW	57
	58	/* SDI command register bits */
	59	#define SDI_CMD_CMDINDEX_MASK 0x000000FF
	60	#define SDI_CMD_WAITRESP 0x00000040
	61	#define SDI_CMD_LONGRESP 0x00000080
	62	#define SDI_CMD_WAITINT 0x00000100
	63	#define SDI_CMD_WAITPEND 0x00000200
	64	#define SDI_CMD_CPSMEN 0x00000400
	65	#define SDI_CMD_SDIOSUSPEND 0x00000800
	66	#define SDI_CMD_ENDCMDCOMPL 0x00001000
	67	#define SDI_CMD_NIEN 0x00002000
	68	#define SDI_CMD_CE_ATACMD 0x00004000
	69	#define SDI_CMD_CBOOTMODEEN 0x00008000
	70
	71	#define SDI_DTIMER_DEFAULT 0xFFFF0000
	72
	73	/* SDI Status register bits */
	74	#define SDI_STA_CCRCFAIL 0x00000001
	75	#define SDI_STA_DCRCFAIL 0x00000002
	76	#define SDI_STA_CTIMEOUT 0x00000004
	77	#define SDI_STA_DTIMEOUT 0x00000008
	78	#define SDI_STA_TXUNDERR 0x00000010
	79	#define SDI_STA_RXOVERR 0x00000020
	80	#define SDI_STA_CMDREND 0x00000040
	81	#define SDI_STA_CMDSENT 0x00000080
	82	#define SDI_STA_DATAEND 0x00000100
	83	#define SDI_STA_STBITERR 0x00000200
	84	#define SDI_STA_DBCKEND 0x00000400
	85	#define SDI_STA_CMDACT 0x00000800
	86	#define SDI_STA_TXACT 0x00001000
	87	#define SDI_STA_RXACT 0x00002000
	88	#define SDI_STA_TXFIFOBW 0x00004000
	89	#define SDI_STA_RXFIFOBR 0x00008000
	90	#define SDI_STA_TXFIFOF 0x00010000
	91	#define SDI_STA_RXFIFOF 0x00020000
	92	#define SDI_STA_TXFIFOE 0x00040000
	93	#define SDI_STA_RXFIFOE 0x00080000
	94	#define SDI_STA_TXDAVL 0x00100000
	95	#define SDI_STA_RXDAVL 0x00200000
	96	#define SDI_STA_SDIOIT 0x00400000
	97	#define SDI_STA_CEATAEND 0x00800000
	98	#define SDI_STA_CARDBUSY 0x01000000
	99	#define SDI_STA_BOOTMODE 0x02000000
	100	#define SDI_STA_BOOTACKERR 0x04000000
	101	#define SDI_STA_BOOTACKTIMEOUT 0x08000000
	102	#define SDI_STA_RSTNEND 0x10000000
	103
	104	/* SDI Interrupt Clear register bits */
	105	#define SDI_ICR_MASK 0x1DC007FF
	106	#define SDI_ICR_CCRCFAILC 0x00000001
	107	#define SDI_ICR_DCRCFAILC 0x00000002
	108	#define SDI_ICR_CTIMEOUTC 0x00000004
	109	#define SDI_ICR_DTIMEOUTC 0x00000008
	110	#define SDI_ICR_TXUNDERRC 0x00000010
	111	#define SDI_ICR_RXOVERRC 0x00000020
	112	#define SDI_ICR_CMDRENDC 0x00000040
	113	#define SDI_ICR_CMDSENTC 0x00000080
	114	#define SDI_ICR_DATAENDC 0x00000100
	115	#define SDI_ICR_STBITERRC 0x00000200
	116	#define SDI_ICR_DBCKENDC 0x00000400
	117	#define SDI_ICR_SDIOITC 0x00400000
	118	#define SDI_ICR_CEATAENDC 0x00800000
	119	#define SDI_ICR_BUSYENDC 0x01000000
	120	#define SDI_ICR_BOOTACKERRC 0x04000000
121	#define SDI_ICR_BOOTACKTIMEOUTC 0x08000000
122	#define SDI_ICR_RSTNENDC 0x10000000
123
124	#define SDI_MASK0_MASK 0x1FFFFFFF
125
126	/* SDI Data control register bits */
127	#define SDI_DCTRL_DTEN 0x00000001
128	#define SDI_DCTRL_DTDIR_IN 0x00000002
129	#define SDI_DCTRL_DTMODE_STREAM 0x00000004
130	#define SDI_DCTRL_DMAEN 0x00000008
131	#define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0
132	#define SDI_DCTRL_RWSTART 0x00000100
133	#define SDI_DCTRL_RWSTOP 0x00000200
134	#define SDI_DCTRL_RWMOD 0x00000200
135	#define SDI_DCTRL_SDIOEN 0x00000800
136	#define SDI_DCTRL_DMAREQCTL 0x00001000
137	#define SDI_DCTRL_DBOOTMODEEN 0x00002000
138	#define SDI_DCTRL_BUSYMODE 0x00004000
139	#define SDI_DCTRL_DDR_MODE 0x00008000
10ed93dc JR	140	#define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000
10ed93dc JR	141	#define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16
23b93e1d MW	142
	143	#define SDI_FIFO_BURST_SIZE 8
	144
3c0dbed2 PC	145	#define VERSION1 false
	146	#define VERSION2 true
	147
23b93e1d MW	148	struct sdi_registers {
	149	u32 power; /* 0x00*/
	150	u32 clock; /* 0x04*/
	151	u32 argument; /* 0x08*/
	152	u32 command; /* 0x0c*/
	153	u32 respcommand; /* 0x10*/
	154	u32 response0; /* 0x14*/
	155	u32 response1; /* 0x18*/
	156	u32 response2; /* 0x1c*/
	157	u32 response3; /* 0x20*/
	158	u32 datatimer; /* 0x24*/
	159	u32 datalength; /* 0x28*/
	160	u32 datactrl; /* 0x2c*/
	161	u32 datacount; /* 0x30*/
	162	u32 status; /* 0x34*/
	163	u32 status_clear; /* 0x38*/
	164	u32 mask0; /* 0x3c*/
	165	u32 mask1; /* 0x40*/
	166	u32 card_select; /* 0x44*/
	167	u32 fifo_count; /* 0x48*/
	168	u32 padding1[(0x80-0x4C)>>2];
	169	u32 fifo; /* 0x80*/
	170	u32 padding2[(0xFE0-0x84)>>2];
	171	u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/
	172	u32 periph_id1; /* 0xFE4*/
	173	u32 periph_id2; /* 0xFE8*/
	174	u32 periph_id3; /* 0xFEC*/
	175	u32 pcell_id0; /* 0xFF0*/
	176	u32 pcell_id1; /* 0xFF4*/
	177	u32 pcell_id2; /* 0xFF8*/
	178	u32 pcell_id3; /* 0xFFC*/
	179	};
	180
10ed93dc JR	181	struct pl180_mmc_host {
	182	struct sdi_registers *base;
	183	char name[32];
	184	unsigned int b_max;
	185	unsigned int voltages;
	186	unsigned int caps;
	187	unsigned int clock_in;
	188	unsigned int clock_min;
	189	unsigned int clock_max;
	190	unsigned int clkdiv_init;
	191	unsigned int pwr_init;
	192	int version2;
93bfd616	193	struct mmc_config cfg;
5829fe2d PC	194	#ifdef CONFIG_DM_MMC
	195	struct gpio_desc cd_gpio;
	196	bool cd_inverted;
	197	#endif
10ed93dc JR	198	};
10ed93dc JR	199
cb0060e8	200	int arm_pl180_mmci_init(struct pl180_mmc_host host, struct mmc *mmc);
10ed93dc	201
23b93e1d	202	#endif