[people/ms/u-boot.git] / drivers / mmc / exynos_dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <jh80.chung@samsung.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,  MA 02111-1307 USA
 *
 */

#include <common.h>
#include <dwmmc.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/pinmux.h>

#define	DWMMC_MAX_CH_NUM		4
#define	DWMMC_MAX_FREQ			52000000
#define	DWMMC_MIN_FREQ			400000
#define	DWMMC_MMC0_CLKSEL_VAL		0x03030001
#define	DWMMC_MMC2_CLKSEL_VAL		0x03020001

/*
 * Function used as callback function to initialise the
 * CLKSEL register for every mmc channel.
 */
static void exynos_dwmci_clksel(struct dwmci_host *host)
{
	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
}

unsigned int exynos_dwmci_get_clk(int dev_index)
{
	return get_mmc_clk(dev_index);
}

/*
 * This function adds the mmc channel to be registered with mmc core.
 * index -	mmc channel number.
 * regbase -	register base address of mmc channel specified in 'index'.
 * bus_width -	operating bus width of mmc channel specified in 'index'.
 * clksel -	value to be written into CLKSEL register in case of FDT.
 *		NULL in case od non-FDT.
 */
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
{
	struct dwmci_host *host = NULL;
	unsigned int div;
	unsigned long freq, sclk;
	host = malloc(sizeof(struct dwmci_host));
	if (!host) {
		printf("dwmci_host malloc fail!\n");
		return 1;
	}
	/* request mmc clock vlaue of 52MHz.  */
	freq = 52000000;
	sclk = get_mmc_clk(index);
	div = DIV_ROUND_UP(sclk, freq);
	/* set the clock divisor for mmc */
	set_mmc_clk(index, div);

	host->name = "EXYNOS DWMMC";
	host->ioaddr = (void *)regbase;
	host->buswidth = bus_width;

	if (clksel) {
		host->clksel_val = clksel;
	} else {
		if (0 == index)
			host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
		if (2 == index)
			host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
	}

	host->clksel = exynos_dwmci_clksel;
	host->dev_index = index;
	host->mmc_clk = exynos_dwmci_get_clk;
	/* Add the mmc channel to be registered with mmc core */
	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
		debug("dwmmc%d registration failed\n", index);
		return -1;
	}
	return 0;
}

#ifdef CONFIG_OF_CONTROL
int exynos_dwmmc_init(const void *blob)
{
	int index, bus_width;
	int node_list[DWMMC_MAX_CH_NUM];
	int err = 0, dev_id, flag, count, i;
	u32 clksel_val, base, timing[3];

	count = fdtdec_find_aliases_for_id(blob, "mmc",
				COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
				DWMMC_MAX_CH_NUM);

	for (i = 0; i < count; i++) {
		int node = node_list[i];

		if (node <= 0)
			continue;

		/* Extract device id for each mmc channel */
		dev_id = pinmux_decode_periph_id(blob, node);

		/* Get the bus width from the device node */
		bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
		if (bus_width <= 0) {
			debug("DWMMC: Can't get bus-width\n");
			return -1;
		}
		if (8 == bus_width)
			flag = PINMUX_FLAG_8BIT_MODE;
		else
			flag = PINMUX_FLAG_NONE;

		/* config pinmux for each mmc channel */
		err = exynos_pinmux_config(dev_id, flag);
		if (err) {
			debug("DWMMC not configured\n");
			return err;
		}

		index = dev_id - PERIPH_ID_SDMMC0;

		/* Get the base address from the device node */
		base = fdtdec_get_addr(blob, node, "reg");
		if (!base) {
			debug("DWMMC: Can't get base address\n");
			return -1;
		}
		/* Extract the timing info from the node */
		err = fdtdec_get_int_array(blob, node, "samsung,timing",
					timing, 3);
		if (err) {
			debug("Can't get sdr-timings for divider\n");
			return -1;
		}

		clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
				DWMCI_SET_DRV_CLK(timing[1]) |
				DWMCI_SET_DIV_RATIO(timing[2]));
		/* Initialise each mmc channel */
		err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
		if (err)
			debug("dwmmc Channel-%d init failed\n", index);
	}
	return 0;
}
#endif
Commit	Line	Data
d0ebbb8d JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <jh80.chung@samsung.com>
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*
	19	*/
	20
	21	#include <common.h>
d0ebbb8d	22	#include <dwmmc.h>
a082a2dd A	23	#include <fdtdec.h>
	24	#include <libfdt.h>
	25	#include <malloc.h>
d0ebbb8d JC	26	#include <asm/arch/dwmmc.h>
d0ebbb8d JC	27	#include <asm/arch/clk.h>
a082a2dd	28	#include <asm/arch/pinmux.h>
d0ebbb8d	29
a082a2dd A	30	#define DWMMC_MAX_CH_NUM 4
	31	#define DWMMC_MAX_FREQ 52000000
	32	#define DWMMC_MIN_FREQ 400000
	33	#define DWMMC_MMC0_CLKSEL_VAL 0x03030001
	34	#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
d0ebbb8d	35
a082a2dd A	36	/*
	37	* Function used as callback function to initialise the
	38	* CLKSEL register for every mmc channel.
	39	*/
d0ebbb8d JC	40	static void exynos_dwmci_clksel(struct dwmci_host *host)
d0ebbb8d JC	41	{
a082a2dd A	42	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
a082a2dd A	43	}
d0ebbb8d	44
a082a2dd A	45	unsigned int exynos_dwmci_get_clk(int dev_index)
	46	{
	47	return get_mmc_clk(dev_index);
d0ebbb8d JC	48	}
d0ebbb8d JC	49
a082a2dd A	50	/*
	51	* This function adds the mmc channel to be registered with mmc core.
	52	* index - mmc channel number.
	53	* regbase - register base address of mmc channel specified in 'index'.
	54	* bus_width - operating bus width of mmc channel specified in 'index'.
	55	* clksel - value to be written into CLKSEL register in case of FDT.
	56	* NULL in case od non-FDT.
	57	*/
	58	int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
d0ebbb8d JC	59	{
d0ebbb8d JC	60	struct dwmci_host *host = NULL;
a082a2dd A	61	unsigned int div;
a082a2dd A	62	unsigned long freq, sclk;
d0ebbb8d JC	63	host = malloc(sizeof(struct dwmci_host));
	64	if (!host) {
	65	printf("dwmci_host malloc fail!\n");
	66	return 1;
	67	}
a082a2dd A	68	/* request mmc clock vlaue of 52MHz. */
	69	freq = 52000000;
	70	sclk = get_mmc_clk(index);
	71	div = DIV_ROUND_UP(sclk, freq);
	72	/* set the clock divisor for mmc */
	73	set_mmc_clk(index, div);
d0ebbb8d	74
a082a2dd	75	host->name = "EXYNOS DWMMC";
d0ebbb8d JC	76	host->ioaddr = (void *)regbase;
d0ebbb8d JC	77	host->buswidth = bus_width;
a082a2dd A	78
	79	if (clksel) {
	80	host->clksel_val = clksel;
	81	} else {
	82	if (0 == index)
	83	host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
	84	if (2 == index)
	85	host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
	86	}
	87
d0ebbb8d JC	88	host->clksel = exynos_dwmci_clksel;
d0ebbb8d JC	89	host->dev_index = index;
a082a2dd A	90	host->mmc_clk = exynos_dwmci_get_clk;
	91	/* Add the mmc channel to be registered with mmc core */
	92	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
	93	debug("dwmmc%d registration failed\n", index);
	94	return -1;
	95	}
	96	return 0;
	97	}
	98
	99	#ifdef CONFIG_OF_CONTROL
	100	int exynos_dwmmc_init(const void *blob)
	101	{
	102	int index, bus_width;
	103	int node_list[DWMMC_MAX_CH_NUM];
	104	int err = 0, dev_id, flag, count, i;
	105	u32 clksel_val, base, timing[3];
	106
	107	count = fdtdec_find_aliases_for_id(blob, "mmc",
	108	COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
	109	DWMMC_MAX_CH_NUM);
	110
	111	for (i = 0; i < count; i++) {
	112	int node = node_list[i];
	113
	114	if (node <= 0)
	115	continue;
d0ebbb8d	116
a082a2dd A	117	/* Extract device id for each mmc channel */
a082a2dd A	118	dev_id = pinmux_decode_periph_id(blob, node);
d0ebbb8d	119
a082a2dd A	120	/* Get the bus width from the device node */
	121	bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
	122	if (bus_width <= 0) {
	123	debug("DWMMC: Can't get bus-width\n");
	124	return -1;
	125	}
	126	if (8 == bus_width)
	127	flag = PINMUX_FLAG_8BIT_MODE;
	128	else
	129	flag = PINMUX_FLAG_NONE;
	130
	131	/* config pinmux for each mmc channel */
	132	err = exynos_pinmux_config(dev_id, flag);
	133	if (err) {
	134	debug("DWMMC not configured\n");
	135	return err;
	136	}
	137
	138	index = dev_id - PERIPH_ID_SDMMC0;
	139
	140	/* Get the base address from the device node */
	141	base = fdtdec_get_addr(blob, node, "reg");
	142	if (!base) {
	143	debug("DWMMC: Can't get base address\n");
	144	return -1;
	145	}
	146	/* Extract the timing info from the node */
	147	err = fdtdec_get_int_array(blob, node, "samsung,timing",
	148	timing, 3);
	149	if (err) {
	150	debug("Can't get sdr-timings for divider\n");
	151	return -1;
	152	}
	153
	154	clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) \|
	155	DWMCI_SET_DRV_CLK(timing[1]) \|
	156	DWMCI_SET_DIV_RATIO(timing[2]));
	157	/* Initialise each mmc channel */
	158	err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
	159	if (err)
	160	debug("dwmmc Channel-%d init failed\n", index);
	161	}
d0ebbb8d JC	162	return 0;
d0ebbb8d JC	163	}
a082a2dd	164	#endif