[people/ms/u-boot.git] / drivers / mmc / fsl_esdhc.c

/*
 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based vaguely on the pxa mmc code:
 * (C) Copyright 2003
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

struct fsl_esdhc {
	uint	dsaddr;
	uint	blkattr;
	uint	cmdarg;
	uint	xfertyp;
	uint	cmdrsp0;
	uint	cmdrsp1;
	uint	cmdrsp2;
	uint	cmdrsp3;
	uint	datport;
	uint	prsstat;
	uint	proctl;
	uint	sysctl;
	uint	irqstat;
	uint	irqstaten;
	uint	irqsigen;
	uint	autoc12err;
	uint	hostcapblt;
	uint	wml;
	uint    mixctrl;
	char    reserved1[4];
	uint	fevt;
	char	reserved2[168];
	uint	hostver;
	char	reserved3[780];
	uint	scr;
};

/* Return the XFERTYP flags for a given command and data packet */
static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint xfertyp = 0;

	if (data) {
		xfertyp |= XFERTYP_DPSEL;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
		xfertyp |= XFERTYP_DMAEN;
#endif
		if (data->blocks > 1) {
			xfertyp |= XFERTYP_MSBSEL;
			xfertyp |= XFERTYP_BCEN;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
			xfertyp |= XFERTYP_AC12EN;
#endif
		}

		if (data->flags & MMC_DATA_READ)
			xfertyp |= XFERTYP_DTDSEL;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		xfertyp |= XFERTYP_CCCEN;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		xfertyp |= XFERTYP_CICEN;
	if (cmd->resp_type & MMC_RSP_136)
		xfertyp |= XFERTYP_RSPTYP_136;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
	else if (cmd->resp_type & MMC_RSP_PRESENT)
		xfertyp |= XFERTYP_RSPTYP_48;

#ifdef CONFIG_MX53
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}

#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
/*
 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 */
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
	struct fsl_esdhc_cfg *cfg = mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	uint blocks;
	char *buffer;
	uint databuf;
	uint size;
	uint irqstat;
	uint timeout;

	if (data->flags & MMC_DATA_READ) {
		blocks = data->blocks;
		buffer = data->dest;
		while (blocks) {
			timeout = PIO_TIMEOUT;
			size = data->blocksize;
			irqstat = esdhc_read32(&regs->irqstat);
			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
				&& --timeout);
			if (timeout <= 0) {
				printf("\nData Read Failed in PIO Mode.");
				return;
			}
			while (size && (!(irqstat & IRQSTAT_TC))) {
				udelay(100); /* Wait before last byte transfer complete */
				irqstat = esdhc_read32(&regs->irqstat);
				databuf = in_le32(&regs->datport);
				*((uint *)buffer) = databuf;
				buffer += 4;
				size -= 4;
			}
			blocks--;
		}
	} else {
		blocks = data->blocks;
		buffer = (char *)data->src;
		while (blocks) {
			timeout = PIO_TIMEOUT;
			size = data->blocksize;
			irqstat = esdhc_read32(&regs->irqstat);
			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
				&& --timeout);
			if (timeout <= 0) {
				printf("\nData Write Failed in PIO Mode.");
				return;
			}
			while (size && (!(irqstat & IRQSTAT_TC))) {
				udelay(100); /* Wait before last byte transfer complete */
				databuf = *((uint *)buffer);
				buffer += 4;
				size -= 4;
				irqstat = esdhc_read32(&regs->irqstat);
				out_le32(&regs->datport, databuf);
			}
			blocks--;
		}
	}
}
#endif

static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
	int timeout;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
	uint wml_value;

	wml_value = data->blocksize/4;

	if (data->flags & MMC_DATA_READ) {
		if (wml_value > WML_RD_WML_MAX)
			wml_value = WML_RD_WML_MAX_VAL;

		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
		esdhc_write32(&regs->dsaddr, (u32)data->dest);
	} else {
		flush_dcache_range((ulong)data->src,
				   (ulong)data->src+data->blocks
					 *data->blocksize);

		if (wml_value > WML_WR_WML_MAX)
			wml_value = WML_WR_WML_MAX_VAL;
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
			return TIMEOUT;
		}

		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
					wml_value << 16);
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	}
#else	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */
	if (!(data->flags & MMC_DATA_READ)) {
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. "
				"Can not write to a locked card.\n\n");
			return TIMEOUT;
		}
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	} else
		esdhc_write32(&regs->dsaddr, (u32)data->dest);
#endif	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */

	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);

	/* Calculate the timeout period for data transactions */
	/*
	 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
	 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
	 *  So, Number of SD Clock cycles for 0.25sec should be minimum
	 *		(SD Clock/sec * 0.25 sec) SD Clock cycles
	 *		= (mmc->tran_speed * 1/4) SD Clock cycles
	 * As 1) >=  2)
	 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
	 * Taking log2 both the sides
	 * => timeout + 13 >= log2(mmc->tran_speed/4)
	 * Rounding up to next power of 2
	 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
	 * => timeout + 13 = fls(mmc->tran_speed/4)
	 */
	timeout = fls(mmc->tran_speed/4);
	timeout -= 13;

	if (timeout > 14)
		timeout = 14;

	if (timeout < 0)
		timeout = 0;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
	if ((timeout == 4) || (timeout == 8) || (timeout == 12))
		timeout++;
#endif

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);

	return 0;
}

static void check_and_invalidate_dcache_range
	(struct mmc_cmd *cmd,
	 struct mmc_data *data) {
	unsigned start = (unsigned)data->dest ;
	unsigned size = roundup(ARCH_DMA_MINALIGN,
				data->blocks*data->blocksize);
	unsigned end = start+size ;
	invalidate_dcache_range(start, end);
}
/*
 * Sends a command out on the bus.  Takes the mmc pointer,
 * a command pointer, and an optional data pointer.
 */
static int
esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint	xfertyp;
	uint	irqstat;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		return 0;
#endif

	esdhc_write32(&regs->irqstat, -1);

	sync();

	/* Wait for the bus to be idle */
	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
		;

	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
		;

	/* Wait at least 8 SD clock cycles before the next command */
	/*
	 * Note: This is way more than 8 cycles, but 1ms seems to
	 * resolve timing issues with some cards
	 */
	udelay(1000);

	/* Set up for a data transfer if we have one */
	if (data) {
		int err;

		err = esdhc_setup_data(mmc, data);
		if(err)
			return err;
	}

	/* Figure out the transfer arguments */
	xfertyp = esdhc_xfertyp(cmd, data);

	/* Send the command */
	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
#if defined(CONFIG_FSL_USDHC)
	esdhc_write32(&regs->mixctrl,
	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
#else
	esdhc_write32(&regs->xfertyp, xfertyp);
#endif

	/* Mask all irqs */
	esdhc_write32(&regs->irqsigen, 0);

	/* Wait for the command to complete */
	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
		;

	if (data && (data->flags & MMC_DATA_READ))
		check_and_invalidate_dcache_range(cmd, data);

	irqstat = esdhc_read32(&regs->irqstat);
	esdhc_write32(&regs->irqstat, irqstat);

	/* Reset CMD and DATA portions on error */
	if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
			      SYSCTL_RSTC);
		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
			;

		if (data) {
			esdhc_write32(&regs->sysctl,
				      esdhc_read32(&regs->sysctl) |
				      SYSCTL_RSTD);
			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
				;
		}
	}

	if (irqstat & CMD_ERR)
		return COMM_ERR;

	if (irqstat & IRQSTAT_CTOE)
		return TIMEOUT;

	/* Workaround for ESDHC errata ENGcm03648 */
	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
		int timeout = 2500;

		/* Poll on DATA0 line for cmd with busy signal for 250 ms */
		while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
					PRSSTAT_DAT0)) {
			udelay(100);
			timeout--;
		}

		if (timeout <= 0) {
			printf("Timeout waiting for DAT0 to go high!\n");
			return TIMEOUT;
		}
	}

	/* Copy the response to the response buffer */
	if (cmd->resp_type & MMC_RSP_136) {
		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;

		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
		cmd->response[3] = (cmdrsp0 << 8);
	} else
		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);

	/* Wait until all of the blocks are transferred */
	if (data) {
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
		esdhc_pio_read_write(mmc, data);
#else
		do {
			irqstat = esdhc_read32(&regs->irqstat);

			if (irqstat & IRQSTAT_DTOE)
				return TIMEOUT;

			if (irqstat & DATA_ERR)
				return COMM_ERR;
		} while (!(irqstat & IRQSTAT_TC) &&
				(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
#endif
	}

	esdhc_write32(&regs->irqstat, -1);

	return 0;
}

static void set_sysctl(struct mmc *mmc, uint clock)
{
	int div, pre_div;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int sdhc_clk = cfg->sdhc_clk;
	uint clk;

	if (clock < mmc->f_min)
		clock = mmc->f_min;

	if (sdhc_clk / 16 > clock) {
		for (pre_div = 2; pre_div < 256; pre_div *= 2)
			if ((sdhc_clk / pre_div) <= (clock * 16))
				break;
	} else
		pre_div = 2;

	for (div = 1; div <= 16; div++)
		if ((sdhc_clk / (div * pre_div)) <= clock)
			break;

	pre_div >>= 1;
	div -= 1;

	clk = (pre_div << 8) | (div << 4);

	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);

	udelay(10000);

	clk = SYSCTL_PEREN | SYSCTL_CKEN;

	esdhc_setbits32(&regs->sysctl, clk);
}

static void esdhc_set_ios(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* Set the clock speed */
	set_sysctl(mmc, mmc->clock);

	/* Set the bus width */
	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);

	if (mmc->bus_width == 4)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
	else if (mmc->bus_width == 8)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);

}

static int esdhc_init(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int timeout = 1000;

	/* Reset the entire host controller */
	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);

	/* Wait until the controller is available */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);

#ifndef ARCH_MXC
	/* Enable cache snooping */
	esdhc_write32(&regs->scr, 0x00000040);
#endif

	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);

	/* Set the initial clock speed */
	mmc_set_clock(mmc, 400000);

	/* Disable the BRR and BWR bits in IRQSTAT */
	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);

	/* Put the PROCTL reg back to the default */
	esdhc_write32(&regs->proctl, PROCTL_INIT);

	/* Set timout to the maximum value */
	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);

	return 0;
}

static int esdhc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int timeout = 1000;

	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
		udelay(1000);

	return timeout > 0;
}

static void esdhc_reset(struct fsl_esdhc *regs)
{
	unsigned long timeout = 100; /* wait max 100 ms */

	/* reset the controller */
	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);

	/* hardware clears the bit when it is done */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);
	if (!timeout)
		printf("MMC/SD: Reset never completed.\n");
}

int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
	struct fsl_esdhc *regs;
	struct mmc *mmc;
	u32 caps, voltage_caps;

	if (!cfg)
		return -1;

	mmc = malloc(sizeof(struct mmc));

	sprintf(mmc->name, "FSL_SDHC");
	regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* First reset the eSDHC controller */
	esdhc_reset(regs);

	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
				| SYSCTL_IPGEN | SYSCTL_CKEN);

	mmc->priv = cfg;
	mmc->send_cmd = esdhc_send_cmd;
	mmc->set_ios = esdhc_set_ios;
	mmc->init = esdhc_init;
	mmc->getcd = esdhc_getcd;
	mmc->getwp = NULL;

	voltage_caps = 0;
	caps = regs->hostcapblt;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
#endif
	if (caps & ESDHC_HOSTCAPBLT_VS18)
		voltage_caps |= MMC_VDD_165_195;
	if (caps & ESDHC_HOSTCAPBLT_VS30)
		voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & ESDHC_HOSTCAPBLT_VS33)
		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;

#ifdef CONFIG_SYS_SD_VOLTAGE
	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
#else
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
	if ((mmc->voltages & voltage_caps) == 0) {
		printf("voltage not supported by controller\n");
		return -1;
	}

	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;

	if (cfg->max_bus_width > 0) {
		if (cfg->max_bus_width < 8)
			mmc->host_caps &= ~MMC_MODE_8BIT;
		if (cfg->max_bus_width < 4)
			mmc->host_caps &= ~MMC_MODE_4BIT;
	}

	if (caps & ESDHC_HOSTCAPBLT_HSS)
		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;

	mmc->f_min = 400000;
	mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);

	mmc->b_max = 0;
	mmc_register(mmc);

	return 0;
}

int fsl_esdhc_mmc_init(bd_t *bis)
{
	struct fsl_esdhc_cfg *cfg;

	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
	cfg->sdhc_clk = gd->arch.sdhc_clk;
	return fsl_esdhc_initialize(bis, cfg);
}

#ifdef CONFIG_OF_LIBFDT
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
	const char *compat = "fsl,esdhc";

#ifdef CONFIG_FSL_ESDHC_PIN_MUX
	if (!hwconfig("esdhc")) {
		do_fixup_by_compat(blob, compat, "status", "disabled",
				8 + 1, 1);
		return;
	}
#endif

	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
			       gd->arch.sdhc_clk, 1);

	do_fixup_by_compat(blob, compat, "status", "okay",
			   4 + 1, 1);
}
#endif
Commit	Line	Data
50586ef2	1	/*
d621da00	2	* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
50586ef2 AF	3	* Andy Fleming
	4	*
	5	* Based vaguely on the pxa mmc code:
	6	* (C) Copyright 2003
	7	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <common.h>
	30	#include <command.h>
b33433a6	31	#include <hwconfig.h>
50586ef2 AF	32	#include <mmc.h>
	33	#include <part.h>
	34	#include <malloc.h>
	35	#include <mmc.h>
	36	#include <fsl_esdhc.h>
b33433a6	37	#include <fdt_support.h>
50586ef2 AF	38	#include <asm/io.h>
50586ef2 AF	39
50586ef2 AF	40	DECLARE_GLOBAL_DATA_PTR;
	41
	42	struct fsl_esdhc {
	43	uint dsaddr;
	44	uint blkattr;
	45	uint cmdarg;
	46	uint xfertyp;
	47	uint cmdrsp0;
	48	uint cmdrsp1;
	49	uint cmdrsp2;
	50	uint cmdrsp3;
	51	uint datport;
	52	uint prsstat;
	53	uint proctl;
	54	uint sysctl;
	55	uint irqstat;
	56	uint irqstaten;
	57	uint irqsigen;
	58	uint autoc12err;
	59	uint hostcapblt;
	60	uint wml;
4692708d JL	61	uint mixctrl;
4692708d JL	62	char reserved1[4];
50586ef2 AF	63	uint fevt;
	64	char reserved2[168];
	65	uint hostver;
	66	char reserved3[780];
	67	uint scr;
	68	};
	69
	70	/* Return the XFERTYP flags for a given command and data packet */
eafa90a1	71	static uint esdhc_xfertyp(struct mmc_cmd cmd, struct mmc_data data)
50586ef2 AF	72	{
	73	uint xfertyp = 0;
	74
	75	if (data) {
77c1458d DD	76	xfertyp \|= XFERTYP_DPSEL;
	77	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
	78	xfertyp \|= XFERTYP_DMAEN;
	79	#endif
50586ef2 AF	80	if (data->blocks > 1) {
	81	xfertyp \|= XFERTYP_MSBSEL;
	82	xfertyp \|= XFERTYP_BCEN;
d621da00 JH	83	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	84	xfertyp \|= XFERTYP_AC12EN;
	85	#endif
50586ef2 AF	86	}
	87
	88	if (data->flags & MMC_DATA_READ)
	89	xfertyp \|= XFERTYP_DTDSEL;
	90	}
	91
	92	if (cmd->resp_type & MMC_RSP_CRC)
	93	xfertyp \|= XFERTYP_CCCEN;
	94	if (cmd->resp_type & MMC_RSP_OPCODE)
	95	xfertyp \|= XFERTYP_CICEN;
	96	if (cmd->resp_type & MMC_RSP_136)
	97	xfertyp \|= XFERTYP_RSPTYP_136;
	98	else if (cmd->resp_type & MMC_RSP_BUSY)
	99	xfertyp \|= XFERTYP_RSPTYP_48_BUSY;
	100	else if (cmd->resp_type & MMC_RSP_PRESENT)
	101	xfertyp \|= XFERTYP_RSPTYP_48;
	102
4571de33 JL	103	#ifdef CONFIG_MX53
	104	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	105	xfertyp \|= XFERTYP_CMDTYP_ABORT;
	106	#endif
50586ef2 AF	107	return XFERTYP_CMD(cmd->cmdidx) \| xfertyp;
	108	}
	109
77c1458d DD	110	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
	111	/*
	112	* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
	113	*/
7b43db92	114	static void
77c1458d DD	115	esdhc_pio_read_write(struct mmc mmc, struct mmc_data data)
77c1458d DD	116	{
8eee2bd7 IS	117	struct fsl_esdhc_cfg *cfg = mmc->priv;
8eee2bd7 IS	118	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
77c1458d DD	119	uint blocks;
	120	char *buffer;
	121	uint databuf;
	122	uint size;
	123	uint irqstat;
	124	uint timeout;
	125
	126	if (data->flags & MMC_DATA_READ) {
	127	blocks = data->blocks;
	128	buffer = data->dest;
	129	while (blocks) {
	130	timeout = PIO_TIMEOUT;
	131	size = data->blocksize;
	132	irqstat = esdhc_read32(&regs->irqstat);
	133	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
	134	&& --timeout);
	135	if (timeout <= 0) {
	136	printf("\nData Read Failed in PIO Mode.");
7b43db92	137	return;
77c1458d DD	138	}
	139	while (size && (!(irqstat & IRQSTAT_TC))) {
	140	udelay(100); /* Wait before last byte transfer complete */
	141	irqstat = esdhc_read32(&regs->irqstat);
	142	databuf = in_le32(&regs->datport);
	143	((uint )buffer) = databuf;
	144	buffer += 4;
	145	size -= 4;
	146	}
	147	blocks--;
	148	}
	149	} else {
	150	blocks = data->blocks;
7b43db92	151	buffer = (char *)data->src;
77c1458d DD	152	while (blocks) {
	153	timeout = PIO_TIMEOUT;
	154	size = data->blocksize;
	155	irqstat = esdhc_read32(&regs->irqstat);
	156	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
	157	&& --timeout);
	158	if (timeout <= 0) {
	159	printf("\nData Write Failed in PIO Mode.");
7b43db92	160	return;
77c1458d DD	161	}
	162	while (size && (!(irqstat & IRQSTAT_TC))) {
	163	udelay(100); /* Wait before last byte transfer complete */
	164	databuf = ((uint )buffer);
	165	buffer += 4;
	166	size -= 4;
	167	irqstat = esdhc_read32(&regs->irqstat);
	168	out_le32(&regs->datport, databuf);
	169	}
	170	blocks--;
	171	}
	172	}
	173	}
	174	#endif
	175
50586ef2 AF	176	static int esdhc_setup_data(struct mmc mmc, struct mmc_data data)
50586ef2 AF	177	{
50586ef2	178	int timeout;
c67bee14 SB	179	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	180	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
7b43db92 WD	181	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
7b43db92 WD	182	uint wml_value;
50586ef2 AF	183
	184	wml_value = data->blocksize/4;
	185
	186	if (data->flags & MMC_DATA_READ) {
32c8cfb2 PJ	187	if (wml_value > WML_RD_WML_MAX)
32c8cfb2 PJ	188	wml_value = WML_RD_WML_MAX_VAL;
50586ef2	189
ab467c51	190	esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
c67bee14	191	esdhc_write32(&regs->dsaddr, (u32)data->dest);
50586ef2	192	} else {
e576bd90 EN	193	flush_dcache_range((ulong)data->src,
	194	(ulong)data->src+data->blocks
	195	*data->blocksize);
	196
32c8cfb2 PJ	197	if (wml_value > WML_WR_WML_MAX)
32c8cfb2 PJ	198	wml_value = WML_WR_WML_MAX_VAL;
c67bee14	199	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
50586ef2 AF	200	printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
	201	return TIMEOUT;
	202	}
ab467c51 RZ	203
	204	esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
	205	wml_value << 16);
c67bee14	206	esdhc_write32(&regs->dsaddr, (u32)data->src);
50586ef2	207	}
7b43db92 WD	208	#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
	209	if (!(data->flags & MMC_DATA_READ)) {
	210	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
	211	printf("\nThe SD card is locked. "
	212	"Can not write to a locked card.\n\n");
	213	return TIMEOUT;
	214	}
	215	esdhc_write32(&regs->dsaddr, (u32)data->src);
	216	} else
	217	esdhc_write32(&regs->dsaddr, (u32)data->dest);
	218	#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
50586ef2	219
c67bee14	220	esdhc_write32(&regs->blkattr, data->blocks << 16 \| data->blocksize);
50586ef2 AF	221
50586ef2 AF	222	/* Calculate the timeout period for data transactions */
b71ea336 PJ	223	/*
	224	* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
	225	* 2)Timeout period should be minimum 0.250sec as per SD Card spec
	226	* So, Number of SD Clock cycles for 0.25sec should be minimum
	227	* (SD Clock/sec * 0.25 sec) SD Clock cycles
	228	* = (mmc->tran_speed * 1/4) SD Clock cycles
	229	* As 1) >= 2)
	230	* => (2^(timeout+13)) >= mmc->tran_speed * 1/4
	231	* Taking log2 both the sides
	232	* => timeout + 13 >= log2(mmc->tran_speed/4)
	233	* Rounding up to next power of 2
	234	* => timeout + 13 = log2(mmc->tran_speed/4) + 1
	235	* => timeout + 13 = fls(mmc->tran_speed/4)
	236	*/
	237	timeout = fls(mmc->tran_speed/4);
50586ef2 AF	238	timeout -= 13;
	239
	240	if (timeout > 14)
	241	timeout = 14;
	242
	243	if (timeout < 0)
	244	timeout = 0;
	245
5103a03a KG	246	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
	247	if ((timeout == 4) \|\| (timeout == 8) \|\| (timeout == 12))
	248	timeout++;
	249	#endif
	250
c67bee14	251	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
50586ef2 AF	252
	253	return 0;
	254	}
	255
e576bd90 EN	256	static void check_and_invalidate_dcache_range
	257	(struct mmc_cmd *cmd,
	258	struct mmc_data *data) {
	259	unsigned start = (unsigned)data->dest ;
	260	unsigned size = roundup(ARCH_DMA_MINALIGN,
	261	data->blocks*data->blocksize);
	262	unsigned end = start+size ;
	263	invalidate_dcache_range(start, end);
	264	}
50586ef2 AF	265	/*
	266	* Sends a command out on the bus. Takes the mmc pointer,
	267	* a command pointer, and an optional data pointer.
	268	*/
	269	static int
	270	esdhc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
	271	{
	272	uint xfertyp;
	273	uint irqstat;
c67bee14 SB	274	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	275	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2	276
d621da00 JH	277	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	278	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	279	return 0;
	280	#endif
	281
c67bee14	282	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	283
	284	sync();
	285
	286	/* Wait for the bus to be idle */
c67bee14 SB	287	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) \|\|
	288	(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
	289	;
50586ef2	290
c67bee14 SB	291	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
c67bee14 SB	292	;
50586ef2 AF	293
	294	/* Wait at least 8 SD clock cycles before the next command */
	295	/*
	296	* Note: This is way more than 8 cycles, but 1ms seems to
	297	* resolve timing issues with some cards
	298	*/
	299	udelay(1000);
	300
	301	/* Set up for a data transfer if we have one */
	302	if (data) {
	303	int err;
	304
	305	err = esdhc_setup_data(mmc, data);
	306	if(err)
	307	return err;
	308	}
	309
	310	/* Figure out the transfer arguments */
	311	xfertyp = esdhc_xfertyp(cmd, data);
	312
	313	/* Send the command */
c67bee14	314	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
4692708d JL	315	#if defined(CONFIG_FSL_USDHC)
	316	esdhc_write32(&regs->mixctrl,
	317	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) \| (xfertyp & 0x7F));
	318	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
	319	#else
c67bee14	320	esdhc_write32(&regs->xfertyp, xfertyp);
4692708d	321	#endif
7a5b8029 DB	322
	323	/* Mask all irqs */
	324	esdhc_write32(&regs->irqsigen, 0);
	325
50586ef2	326	/* Wait for the command to complete */
7a5b8029	327	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC \| IRQSTAT_CTOE)))
c67bee14	328	;
50586ef2	329
e576bd90 EN	330	if (data && (data->flags & MMC_DATA_READ))
	331	check_and_invalidate_dcache_range(cmd, data);
	332
c67bee14 SB	333	irqstat = esdhc_read32(&regs->irqstat);
c67bee14 SB	334	esdhc_write32(&regs->irqstat, irqstat);
50586ef2	335
7a5b8029 DB	336	/* Reset CMD and DATA portions on error */
	337	if (irqstat & (CMD_ERR \| IRQSTAT_CTOE)) {
	338	esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) \|
	339	SYSCTL_RSTC);
	340	while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
	341	;
	342
	343	if (data) {
	344	esdhc_write32(&regs->sysctl,
	345	esdhc_read32(&regs->sysctl) \|
	346	SYSCTL_RSTD);
	347	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
	348	;
	349	}
	350	}
	351
50586ef2 AF	352	if (irqstat & CMD_ERR)
	353	return COMM_ERR;
	354
	355	if (irqstat & IRQSTAT_CTOE)
	356	return TIMEOUT;
	357
7a5b8029 DB	358	/* Workaround for ESDHC errata ENGcm03648 */
	359	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
	360	int timeout = 2500;
	361
	362	/* Poll on DATA0 line for cmd with busy signal for 250 ms */
	363	while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
	364	PRSSTAT_DAT0)) {
	365	udelay(100);
	366	timeout--;
	367	}
	368
	369	if (timeout <= 0) {
	370	printf("Timeout waiting for DAT0 to go high!\n");
	371	return TIMEOUT;
	372	}
	373	}
	374
50586ef2 AF	375	/* Copy the response to the response buffer */
	376	if (cmd->resp_type & MMC_RSP_136) {
	377	u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
	378
c67bee14 SB	379	cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
	380	cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
	381	cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
	382	cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
998be3dd RV	383	cmd->response[0] = (cmdrsp3 << 8) \| (cmdrsp2 >> 24);
	384	cmd->response[1] = (cmdrsp2 << 8) \| (cmdrsp1 >> 24);
	385	cmd->response[2] = (cmdrsp1 << 8) \| (cmdrsp0 >> 24);
	386	cmd->response[3] = (cmdrsp0 << 8);
50586ef2	387	} else
c67bee14	388	cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
50586ef2 AF	389
	390	/* Wait until all of the blocks are transferred */
	391	if (data) {
77c1458d DD	392	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
	393	esdhc_pio_read_write(mmc, data);
	394	#else
50586ef2	395	do {
c67bee14	396	irqstat = esdhc_read32(&regs->irqstat);
50586ef2	397
50586ef2 AF	398	if (irqstat & IRQSTAT_DTOE)
50586ef2 AF	399	return TIMEOUT;
63fb5a7e FM	400
	401	if (irqstat & DATA_ERR)
	402	return COMM_ERR;
50586ef2	403	} while (!(irqstat & IRQSTAT_TC) &&
c67bee14	404	(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
77c1458d	405	#endif
50586ef2 AF	406	}
50586ef2 AF	407
c67bee14	408	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	409
	410	return 0;
	411	}
	412
eafa90a1	413	static void set_sysctl(struct mmc *mmc, uint clock)
50586ef2	414	{
50586ef2	415	int div, pre_div;
c67bee14 SB	416	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	417	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
a2ac1b3a	418	int sdhc_clk = cfg->sdhc_clk;
50586ef2 AF	419	uint clk;
50586ef2 AF	420
c67bee14 SB	421	if (clock < mmc->f_min)
	422	clock = mmc->f_min;
	423
50586ef2 AF	424	if (sdhc_clk / 16 > clock) {
	425	for (pre_div = 2; pre_div < 256; pre_div *= 2)
	426	if ((sdhc_clk / pre_div) <= (clock * 16))
	427	break;
	428	} else
	429	pre_div = 2;
	430
	431	for (div = 1; div <= 16; div++)
	432	if ((sdhc_clk / (div * pre_div)) <= clock)
	433	break;
	434
	435	pre_div >>= 1;
	436	div -= 1;
	437
	438	clk = (pre_div << 8) \| (div << 4);
	439
cc4d1226	440	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
c67bee14 SB	441
c67bee14 SB	442	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
50586ef2 AF	443
	444	udelay(10000);
	445
cc4d1226	446	clk = SYSCTL_PEREN \| SYSCTL_CKEN;
c67bee14 SB	447
c67bee14 SB	448	esdhc_setbits32(&regs->sysctl, clk);
50586ef2 AF	449	}
	450
	451	static void esdhc_set_ios(struct mmc *mmc)
	452	{
c67bee14 SB	453	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	454	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	455
	456	/* Set the clock speed */
	457	set_sysctl(mmc, mmc->clock);
	458
	459	/* Set the bus width */
c67bee14	460	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 \| PROCTL_DTW_8);
50586ef2 AF	461
50586ef2 AF	462	if (mmc->bus_width == 4)
c67bee14	463	esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
50586ef2	464	else if (mmc->bus_width == 8)
c67bee14 SB	465	esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
c67bee14 SB	466
50586ef2 AF	467	}
	468
	469	static int esdhc_init(struct mmc *mmc)
	470	{
c67bee14 SB	471	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	472	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	473	int timeout = 1000;
50586ef2 AF	474
c67bee14 SB	475	/* Reset the entire host controller */
	476	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
	477
	478	/* Wait until the controller is available */
	479	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	480	udelay(1000);
50586ef2	481
16e43f35	482	#ifndef ARCH_MXC
2c1764ef	483	/* Enable cache snooping */
16e43f35 BT	484	esdhc_write32(&regs->scr, 0x00000040);
16e43f35 BT	485	#endif
2c1764ef	486
c67bee14	487	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN \| SYSCTL_IPGEN);
50586ef2 AF	488
50586ef2 AF	489	/* Set the initial clock speed */
4a6ee172	490	mmc_set_clock(mmc, 400000);
50586ef2 AF	491
50586ef2 AF	492	/* Disable the BRR and BWR bits in IRQSTAT */
c67bee14	493	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR \| IRQSTATEN_BWR);
50586ef2 AF	494
50586ef2 AF	495	/* Put the PROCTL reg back to the default */
c67bee14	496	esdhc_write32(&regs->proctl, PROCTL_INIT);
50586ef2	497
c67bee14 SB	498	/* Set timout to the maximum value */
c67bee14 SB	499	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
50586ef2	500
d48d2e21 TR	501	return 0;
d48d2e21 TR	502	}
50586ef2	503
d48d2e21 TR	504	static int esdhc_getcd(struct mmc *mmc)
	505	{
	506	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	507	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
	508	int timeout = 1000;
	509
	510	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
	511	udelay(1000);
c67bee14	512
d48d2e21	513	return timeout > 0;
50586ef2 AF	514	}
50586ef2 AF	515
48bb3bb5 JH	516	static void esdhc_reset(struct fsl_esdhc *regs)
	517	{
	518	unsigned long timeout = 100; /* wait max 100 ms */
	519
	520	/* reset the controller */
	521	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
	522
	523	/* hardware clears the bit when it is done */
	524	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	525	udelay(1000);
	526	if (!timeout)
	527	printf("MMC/SD: Reset never completed.\n");
	528	}
	529
c67bee14	530	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg)
50586ef2	531	{
c67bee14	532	struct fsl_esdhc *regs;
50586ef2	533	struct mmc *mmc;
030955c2	534	u32 caps, voltage_caps;
50586ef2	535
c67bee14 SB	536	if (!cfg)
	537	return -1;
	538
50586ef2 AF	539	mmc = malloc(sizeof(struct mmc));
50586ef2 AF	540
4692708d	541	sprintf(mmc->name, "FSL_SDHC");
c67bee14 SB	542	regs = (struct fsl_esdhc *)cfg->esdhc_base;
c67bee14 SB	543
48bb3bb5 JH	544	/* First reset the eSDHC controller */
	545	esdhc_reset(regs);
	546
975324a7 JH	547	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN \| SYSCTL_HCKEN
	548	\| SYSCTL_IPGEN \| SYSCTL_CKEN);
	549
c67bee14	550	mmc->priv = cfg;
50586ef2 AF	551	mmc->send_cmd = esdhc_send_cmd;
	552	mmc->set_ios = esdhc_set_ios;
	553	mmc->init = esdhc_init;
d48d2e21	554	mmc->getcd = esdhc_getcd;
d23d8d7e	555	mmc->getwp = NULL;
50586ef2	556
030955c2	557	voltage_caps = 0;
50586ef2	558	caps = regs->hostcapblt;
3b4456ec RZ	559
	560	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
	561	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS \|
	562	ESDHC_HOSTCAPBLT_VS18 \| ESDHC_HOSTCAPBLT_VS30);
	563	#endif
50586ef2	564	if (caps & ESDHC_HOSTCAPBLT_VS18)
030955c2	565	voltage_caps \|= MMC_VDD_165_195;
50586ef2	566	if (caps & ESDHC_HOSTCAPBLT_VS30)
030955c2	567	voltage_caps \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
50586ef2	568	if (caps & ESDHC_HOSTCAPBLT_VS33)
030955c2 LY	569	voltage_caps \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
	570
	571	#ifdef CONFIG_SYS_SD_VOLTAGE
	572	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
	573	#else
	574	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
	575	#endif
	576	if ((mmc->voltages & voltage_caps) == 0) {
	577	printf("voltage not supported by controller\n");
	578	return -1;
	579	}
50586ef2	580
fb8302bf	581	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT \| MMC_MODE_HC;
50586ef2	582
aad4659a AR	583	if (cfg->max_bus_width > 0) {
	584	if (cfg->max_bus_width < 8)
	585	mmc->host_caps &= ~MMC_MODE_8BIT;
	586	if (cfg->max_bus_width < 4)
	587	mmc->host_caps &= ~MMC_MODE_4BIT;
	588	}
	589
50586ef2 AF	590	if (caps & ESDHC_HOSTCAPBLT_HSS)
	591	mmc->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
	592
	593	mmc->f_min = 400000;
e9adeca3	594	mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
50586ef2	595
1ed60d7a	596	mmc->b_max = 0;
50586ef2 AF	597	mmc_register(mmc);
	598
	599	return 0;
	600	}
	601
	602	int fsl_esdhc_mmc_init(bd_t *bis)
	603	{
c67bee14 SB	604	struct fsl_esdhc_cfg *cfg;
	605
	606	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
	607	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
	608	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
e9adeca3	609	cfg->sdhc_clk = gd->arch.sdhc_clk;
c67bee14	610	return fsl_esdhc_initialize(bis, cfg);
50586ef2	611	}
b33433a6	612
c67bee14	613	#ifdef CONFIG_OF_LIBFDT
b33433a6 AV	614	void fdt_fixup_esdhc(void blob, bd_t bd)
	615	{
	616	const char *compat = "fsl,esdhc";
b33433a6	617
a6da8b81	618	#ifdef CONFIG_FSL_ESDHC_PIN_MUX
b33433a6	619	if (!hwconfig("esdhc")) {
a6da8b81 CZ	620	do_fixup_by_compat(blob, compat, "status", "disabled",
	621	8 + 1, 1);
	622	return;
b33433a6	623	}
a6da8b81	624	#endif
b33433a6 AV	625
b33433a6 AV	626	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
e9adeca3	627	gd->arch.sdhc_clk, 1);
a6da8b81 CZ	628
	629	do_fixup_by_compat(blob, compat, "status", "okay",
	630	4 + 1, 1);
b33433a6	631	}
c67bee14	632	#endif