[people/ms/u-boot.git] / drivers / mmc / fsl_esdhc.c

/*
 * Copyright 2007,2010 Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based vaguely on the pxa mmc code:
 * (C) Copyright 2003
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

struct fsl_esdhc {
	uint	dsaddr;
	uint	blkattr;
	uint	cmdarg;
	uint	xfertyp;
	uint	cmdrsp0;
	uint	cmdrsp1;
	uint	cmdrsp2;
	uint	cmdrsp3;
	uint	datport;
	uint	prsstat;
	uint	proctl;
	uint	sysctl;
	uint	irqstat;
	uint	irqstaten;
	uint	irqsigen;
	uint	autoc12err;
	uint	hostcapblt;
	uint	wml;
	char	reserved1[8];
	uint	fevt;
	char	reserved2[168];
	uint	hostver;
	char	reserved3[780];
	uint	scr;
};

/* Return the XFERTYP flags for a given command and data packet */
uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint xfertyp = 0;

	if (data) {
		xfertyp |= XFERTYP_DPSEL;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
		xfertyp |= XFERTYP_DMAEN;
#endif
		if (data->blocks > 1) {
			xfertyp |= XFERTYP_MSBSEL;
			xfertyp |= XFERTYP_BCEN;
		}

		if (data->flags & MMC_DATA_READ)
			xfertyp |= XFERTYP_DTDSEL;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		xfertyp |= XFERTYP_CCCEN;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		xfertyp |= XFERTYP_CICEN;
	if (cmd->resp_type & MMC_RSP_136)
		xfertyp |= XFERTYP_RSPTYP_136;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
	else if (cmd->resp_type & MMC_RSP_PRESENT)
		xfertyp |= XFERTYP_RSPTYP_48;

	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}

#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
/*
 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 */
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
	struct fsl_esdhc *regs = mmc->priv;
	uint blocks;
	char *buffer;
	uint databuf;
	uint size;
	uint irqstat;
	uint timeout;

	if (data->flags & MMC_DATA_READ) {
		blocks = data->blocks;
		buffer = data->dest;
		while (blocks) {
			timeout = PIO_TIMEOUT;
			size = data->blocksize;
			irqstat = esdhc_read32(&regs->irqstat);
			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
				&& --timeout);
			if (timeout <= 0) {
				printf("\nData Read Failed in PIO Mode.");
				return;
			}
			while (size && (!(irqstat & IRQSTAT_TC))) {
				udelay(100); /* Wait before last byte transfer complete */
				irqstat = esdhc_read32(&regs->irqstat);
				databuf = in_le32(&regs->datport);
				*((uint *)buffer) = databuf;
				buffer += 4;
				size -= 4;
			}
			blocks--;
		}
	} else {
		blocks = data->blocks;
		buffer = (char *)data->src;
		while (blocks) {
			timeout = PIO_TIMEOUT;
			size = data->blocksize;
			irqstat = esdhc_read32(&regs->irqstat);
			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
				&& --timeout);
			if (timeout <= 0) {
				printf("\nData Write Failed in PIO Mode.");
				return;
			}
			while (size && (!(irqstat & IRQSTAT_TC))) {
				udelay(100); /* Wait before last byte transfer complete */
				databuf = *((uint *)buffer);
				buffer += 4;
				size -= 4;
				irqstat = esdhc_read32(&regs->irqstat);
				out_le32(&regs->datport, databuf);
			}
			blocks--;
		}
	}
}
#endif

static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
	int timeout;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
	uint wml_value;

	wml_value = data->blocksize/4;

	if (data->flags & MMC_DATA_READ) {
		if (wml_value > 0x10)
			wml_value = 0x10;

		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
		esdhc_write32(&regs->dsaddr, (u32)data->dest);
	} else {
		if (wml_value > 0x80)
			wml_value = 0x80;
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
			return TIMEOUT;
		}

		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
					wml_value << 16);
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	}
#else	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */
	if (!(data->flags & MMC_DATA_READ)) {
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. "
				"Can not write to a locked card.\n\n");
			return TIMEOUT;
		}
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	} else
		esdhc_write32(&regs->dsaddr, (u32)data->dest);
#endif	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */

	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);

	/* Calculate the timeout period for data transactions */
	timeout = fls(mmc->tran_speed/10) - 1;
	timeout -= 13;

	if (timeout > 14)
		timeout = 14;

	if (timeout < 0)
		timeout = 0;

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);

	return 0;
}


/*
 * Sends a command out on the bus.  Takes the mmc pointer,
 * a command pointer, and an optional data pointer.
 */
static int
esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint	xfertyp;
	uint	irqstat;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

	esdhc_write32(&regs->irqstat, -1);

	sync();

	/* Wait for the bus to be idle */
	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
		;

	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
		;

	/* Wait at least 8 SD clock cycles before the next command */
	/*
	 * Note: This is way more than 8 cycles, but 1ms seems to
	 * resolve timing issues with some cards
	 */
	udelay(1000);

	/* Set up for a data transfer if we have one */
	if (data) {
		int err;

		err = esdhc_setup_data(mmc, data);
		if(err)
			return err;
	}

	/* Figure out the transfer arguments */
	xfertyp = esdhc_xfertyp(cmd, data);

	/* Send the command */
	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
	esdhc_write32(&regs->xfertyp, xfertyp);

	/* Wait for the command to complete */
	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
		;

	irqstat = esdhc_read32(&regs->irqstat);
	esdhc_write32(&regs->irqstat, irqstat);

	if (irqstat & CMD_ERR)
		return COMM_ERR;

	if (irqstat & IRQSTAT_CTOE)
		return TIMEOUT;

	/* Copy the response to the response buffer */
	if (cmd->resp_type & MMC_RSP_136) {
		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;

		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
		cmd->response[3] = (cmdrsp0 << 8);
	} else
		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);

	/* Wait until all of the blocks are transferred */
	if (data) {
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
		esdhc_pio_read_write(mmc, data);
#else
		do {
			irqstat = esdhc_read32(&regs->irqstat);

			if (irqstat & DATA_ERR)
				return COMM_ERR;

			if (irqstat & IRQSTAT_DTOE)
				return TIMEOUT;
		} while (!(irqstat & IRQSTAT_TC) &&
				(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
#endif
	}

	esdhc_write32(&regs->irqstat, -1);

	return 0;
}

void set_sysctl(struct mmc *mmc, uint clock)
{
	int sdhc_clk = gd->sdhc_clk;
	int div, pre_div;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	uint clk;

	if (clock < mmc->f_min)
		clock = mmc->f_min;

	if (sdhc_clk / 16 > clock) {
		for (pre_div = 2; pre_div < 256; pre_div *= 2)
			if ((sdhc_clk / pre_div) <= (clock * 16))
				break;
	} else
		pre_div = 2;

	for (div = 1; div <= 16; div++)
		if ((sdhc_clk / (div * pre_div)) <= clock)
			break;

	pre_div >>= 1;
	div -= 1;

	clk = (pre_div << 8) | (div << 4);

	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);

	udelay(10000);

	clk = SYSCTL_PEREN | SYSCTL_CKEN;

	esdhc_setbits32(&regs->sysctl, clk);
}

static void esdhc_set_ios(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* Set the clock speed */
	set_sysctl(mmc, mmc->clock);

	/* Set the bus width */
	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);

	if (mmc->bus_width == 4)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
	else if (mmc->bus_width == 8)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);

}

static int esdhc_init(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int timeout = 1000;
	int ret = 0;
	u8 card_absent;

	/* Reset the entire host controller */
	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);

	/* Wait until the controller is available */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);

	/* Enable cache snooping */
	if (cfg && !cfg->no_snoop)
		esdhc_write32(&regs->scr, 0x00000040);

	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);

	/* Set the initial clock speed */
	mmc_set_clock(mmc, 400000);

	/* Disable the BRR and BWR bits in IRQSTAT */
	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);

	/* Put the PROCTL reg back to the default */
	esdhc_write32(&regs->proctl, PROCTL_INIT);

	/* Set timout to the maximum value */
	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);

	/* Check if there is a callback for detecting the card */
	if (board_mmc_getcd(&card_absent, mmc)) {
		timeout = 1000;
		while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) &&
				--timeout)
			udelay(1000);

		if (timeout <= 0)
			ret = NO_CARD_ERR;
	} else {
		if (card_absent)
			ret = NO_CARD_ERR;
	}

	return ret;
}

static void esdhc_reset(struct fsl_esdhc *regs)
{
	unsigned long timeout = 100; /* wait max 100 ms */

	/* reset the controller */
	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);

	/* hardware clears the bit when it is done */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);
	if (!timeout)
		printf("MMC/SD: Reset never completed.\n");
}

int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
	struct fsl_esdhc *regs;
	struct mmc *mmc;
	u32 caps, voltage_caps;

	if (!cfg)
		return -1;

	mmc = malloc(sizeof(struct mmc));

	sprintf(mmc->name, "FSL_ESDHC");
	regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* First reset the eSDHC controller */
	esdhc_reset(regs);

	mmc->priv = cfg;
	mmc->send_cmd = esdhc_send_cmd;
	mmc->set_ios = esdhc_set_ios;
	mmc->init = esdhc_init;

	voltage_caps = 0;
	caps = regs->hostcapblt;
	if (caps & ESDHC_HOSTCAPBLT_VS18)
		voltage_caps |= MMC_VDD_165_195;
	if (caps & ESDHC_HOSTCAPBLT_VS30)
		voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & ESDHC_HOSTCAPBLT_VS33)
		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;

#ifdef CONFIG_SYS_SD_VOLTAGE
	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
#else
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
	if ((mmc->voltages & voltage_caps) == 0) {
		printf("voltage not supported by controller\n");
		return -1;
	}

	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;

	if (caps & ESDHC_HOSTCAPBLT_HSS)
		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;

	mmc->f_min = 400000;
	mmc->f_max = MIN(gd->sdhc_clk, 52000000);

	mmc_register(mmc);

	return 0;
}

int fsl_esdhc_mmc_init(bd_t *bis)
{
	struct fsl_esdhc_cfg *cfg;

	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
	return fsl_esdhc_initialize(bis, cfg);
}

#ifdef CONFIG_OF_LIBFDT
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
	const char *compat = "fsl,esdhc";

#ifdef CONFIG_FSL_ESDHC_PIN_MUX
	if (!hwconfig("esdhc")) {
		do_fixup_by_compat(blob, compat, "status", "disabled",
				8 + 1, 1);
		return;
	}
#endif

	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
			       gd->sdhc_clk, 1);

	do_fixup_by_compat(blob, compat, "status", "okay",
			   4 + 1, 1);
}
#endif
Commit	Line	Data
50586ef2	1	/*
cc4d1226	2	* Copyright 2007,2010 Freescale Semiconductor, Inc
50586ef2 AF	3	* Andy Fleming
	4	*
	5	* Based vaguely on the pxa mmc code:
	6	* (C) Copyright 2003
	7	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <common.h>
	30	#include <command.h>
b33433a6	31	#include <hwconfig.h>
50586ef2 AF	32	#include <mmc.h>
	33	#include <part.h>
	34	#include <malloc.h>
	35	#include <mmc.h>
	36	#include <fsl_esdhc.h>
b33433a6	37	#include <fdt_support.h>
50586ef2 AF	38	#include <asm/io.h>
50586ef2 AF	39
50586ef2 AF	40	DECLARE_GLOBAL_DATA_PTR;
	41
	42	struct fsl_esdhc {
	43	uint dsaddr;
	44	uint blkattr;
	45	uint cmdarg;
	46	uint xfertyp;
	47	uint cmdrsp0;
	48	uint cmdrsp1;
	49	uint cmdrsp2;
	50	uint cmdrsp3;
	51	uint datport;
	52	uint prsstat;
	53	uint proctl;
	54	uint sysctl;
	55	uint irqstat;
	56	uint irqstaten;
	57	uint irqsigen;
	58	uint autoc12err;
	59	uint hostcapblt;
	60	uint wml;
	61	char reserved1[8];
	62	uint fevt;
	63	char reserved2[168];
	64	uint hostver;
	65	char reserved3[780];
	66	uint scr;
	67	};
	68
	69	/* Return the XFERTYP flags for a given command and data packet */
	70	uint esdhc_xfertyp(struct mmc_cmd cmd, struct mmc_data data)
	71	{
	72	uint xfertyp = 0;
	73
	74	if (data) {
77c1458d DD	75	xfertyp \|= XFERTYP_DPSEL;
	76	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
	77	xfertyp \|= XFERTYP_DMAEN;
	78	#endif
50586ef2 AF	79	if (data->blocks > 1) {
	80	xfertyp \|= XFERTYP_MSBSEL;
	81	xfertyp \|= XFERTYP_BCEN;
	82	}
	83
	84	if (data->flags & MMC_DATA_READ)
	85	xfertyp \|= XFERTYP_DTDSEL;
	86	}
	87
	88	if (cmd->resp_type & MMC_RSP_CRC)
	89	xfertyp \|= XFERTYP_CCCEN;
	90	if (cmd->resp_type & MMC_RSP_OPCODE)
	91	xfertyp \|= XFERTYP_CICEN;
	92	if (cmd->resp_type & MMC_RSP_136)
	93	xfertyp \|= XFERTYP_RSPTYP_136;
	94	else if (cmd->resp_type & MMC_RSP_BUSY)
	95	xfertyp \|= XFERTYP_RSPTYP_48_BUSY;
	96	else if (cmd->resp_type & MMC_RSP_PRESENT)
	97	xfertyp \|= XFERTYP_RSPTYP_48;
	98
	99	return XFERTYP_CMD(cmd->cmdidx) \| xfertyp;
	100	}
	101
77c1458d DD	102	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
	103	/*
	104	* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
	105	*/
7b43db92	106	static void
77c1458d DD	107	esdhc_pio_read_write(struct mmc mmc, struct mmc_data data)
	108	{
	109	struct fsl_esdhc *regs = mmc->priv;
	110	uint blocks;
	111	char *buffer;
	112	uint databuf;
	113	uint size;
	114	uint irqstat;
	115	uint timeout;
	116
	117	if (data->flags & MMC_DATA_READ) {
	118	blocks = data->blocks;
	119	buffer = data->dest;
	120	while (blocks) {
	121	timeout = PIO_TIMEOUT;
	122	size = data->blocksize;
	123	irqstat = esdhc_read32(&regs->irqstat);
	124	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
	125	&& --timeout);
	126	if (timeout <= 0) {
	127	printf("\nData Read Failed in PIO Mode.");
7b43db92	128	return;
77c1458d DD	129	}
	130	while (size && (!(irqstat & IRQSTAT_TC))) {
	131	udelay(100); /* Wait before last byte transfer complete */
	132	irqstat = esdhc_read32(&regs->irqstat);
	133	databuf = in_le32(&regs->datport);
	134	((uint )buffer) = databuf;
	135	buffer += 4;
	136	size -= 4;
	137	}
	138	blocks--;
	139	}
	140	} else {
	141	blocks = data->blocks;
7b43db92	142	buffer = (char *)data->src;
77c1458d DD	143	while (blocks) {
	144	timeout = PIO_TIMEOUT;
	145	size = data->blocksize;
	146	irqstat = esdhc_read32(&regs->irqstat);
	147	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
	148	&& --timeout);
	149	if (timeout <= 0) {
	150	printf("\nData Write Failed in PIO Mode.");
7b43db92	151	return;
77c1458d DD	152	}
	153	while (size && (!(irqstat & IRQSTAT_TC))) {
	154	udelay(100); /* Wait before last byte transfer complete */
	155	databuf = ((uint )buffer);
	156	buffer += 4;
	157	size -= 4;
	158	irqstat = esdhc_read32(&regs->irqstat);
	159	out_le32(&regs->datport, databuf);
	160	}
	161	blocks--;
	162	}
	163	}
	164	}
	165	#endif
	166
50586ef2 AF	167	static int esdhc_setup_data(struct mmc mmc, struct mmc_data data)
50586ef2 AF	168	{
50586ef2	169	int timeout;
c67bee14 SB	170	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	171	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
7b43db92 WD	172	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
7b43db92 WD	173	uint wml_value;
50586ef2 AF	174
	175	wml_value = data->blocksize/4;
	176
	177	if (data->flags & MMC_DATA_READ) {
	178	if (wml_value > 0x10)
	179	wml_value = 0x10;
	180
ab467c51	181	esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
c67bee14	182	esdhc_write32(&regs->dsaddr, (u32)data->dest);
50586ef2 AF	183	} else {
	184	if (wml_value > 0x80)
	185	wml_value = 0x80;
c67bee14	186	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
50586ef2 AF	187	printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
	188	return TIMEOUT;
	189	}
ab467c51 RZ	190
	191	esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
	192	wml_value << 16);
c67bee14	193	esdhc_write32(&regs->dsaddr, (u32)data->src);
50586ef2	194	}
7b43db92 WD	195	#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
	196	if (!(data->flags & MMC_DATA_READ)) {
	197	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
	198	printf("\nThe SD card is locked. "
	199	"Can not write to a locked card.\n\n");
	200	return TIMEOUT;
	201	}
	202	esdhc_write32(&regs->dsaddr, (u32)data->src);
	203	} else
	204	esdhc_write32(&regs->dsaddr, (u32)data->dest);
	205	#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
50586ef2	206
c67bee14	207	esdhc_write32(&regs->blkattr, data->blocks << 16 \| data->blocksize);
50586ef2 AF	208
50586ef2 AF	209	/* Calculate the timeout period for data transactions */
c67bee14	210	timeout = fls(mmc->tran_speed/10) - 1;
50586ef2 AF	211	timeout -= 13;
	212
	213	if (timeout > 14)
	214	timeout = 14;
	215
	216	if (timeout < 0)
	217	timeout = 0;
	218
c67bee14	219	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
50586ef2 AF	220
	221	return 0;
	222	}
	223
	224
	225	/*
	226	* Sends a command out on the bus. Takes the mmc pointer,
	227	* a command pointer, and an optional data pointer.
	228	*/
	229	static int
	230	esdhc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
	231	{
	232	uint xfertyp;
	233	uint irqstat;
c67bee14 SB	234	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	235	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2	236
c67bee14	237	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	238
	239	sync();
	240
	241	/* Wait for the bus to be idle */
c67bee14 SB	242	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) \|\|
	243	(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
	244	;
50586ef2	245
c67bee14 SB	246	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
c67bee14 SB	247	;
50586ef2 AF	248
	249	/* Wait at least 8 SD clock cycles before the next command */
	250	/*
	251	* Note: This is way more than 8 cycles, but 1ms seems to
	252	* resolve timing issues with some cards
	253	*/
	254	udelay(1000);
	255
	256	/* Set up for a data transfer if we have one */
	257	if (data) {
	258	int err;
	259
	260	err = esdhc_setup_data(mmc, data);
	261	if(err)
	262	return err;
	263	}
	264
	265	/* Figure out the transfer arguments */
	266	xfertyp = esdhc_xfertyp(cmd, data);
	267
	268	/* Send the command */
c67bee14 SB	269	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
c67bee14 SB	270	esdhc_write32(&regs->xfertyp, xfertyp);
50586ef2 AF	271
50586ef2 AF	272	/* Wait for the command to complete */
c67bee14 SB	273	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
c67bee14 SB	274	;
50586ef2	275
c67bee14 SB	276	irqstat = esdhc_read32(&regs->irqstat);
c67bee14 SB	277	esdhc_write32(&regs->irqstat, irqstat);
50586ef2 AF	278
	279	if (irqstat & CMD_ERR)
	280	return COMM_ERR;
	281
	282	if (irqstat & IRQSTAT_CTOE)
	283	return TIMEOUT;
	284
	285	/* Copy the response to the response buffer */
	286	if (cmd->resp_type & MMC_RSP_136) {
	287	u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
	288
c67bee14 SB	289	cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
	290	cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
	291	cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
	292	cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
998be3dd RV	293	cmd->response[0] = (cmdrsp3 << 8) \| (cmdrsp2 >> 24);
	294	cmd->response[1] = (cmdrsp2 << 8) \| (cmdrsp1 >> 24);
	295	cmd->response[2] = (cmdrsp1 << 8) \| (cmdrsp0 >> 24);
	296	cmd->response[3] = (cmdrsp0 << 8);
50586ef2	297	} else
c67bee14	298	cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
50586ef2 AF	299
	300	/* Wait until all of the blocks are transferred */
	301	if (data) {
77c1458d DD	302	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
	303	esdhc_pio_read_write(mmc, data);
	304	#else
50586ef2	305	do {
c67bee14	306	irqstat = esdhc_read32(&regs->irqstat);
50586ef2 AF	307
	308	if (irqstat & DATA_ERR)
	309	return COMM_ERR;
	310
	311	if (irqstat & IRQSTAT_DTOE)
	312	return TIMEOUT;
	313	} while (!(irqstat & IRQSTAT_TC) &&
c67bee14	314	(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
77c1458d	315	#endif
50586ef2 AF	316	}
50586ef2 AF	317
c67bee14	318	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	319
	320	return 0;
	321	}
	322
	323	void set_sysctl(struct mmc *mmc, uint clock)
	324	{
	325	int sdhc_clk = gd->sdhc_clk;
	326	int div, pre_div;
c67bee14 SB	327	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	328	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	329	uint clk;
50586ef2 AF	330
c67bee14 SB	331	if (clock < mmc->f_min)
	332	clock = mmc->f_min;
	333
50586ef2 AF	334	if (sdhc_clk / 16 > clock) {
	335	for (pre_div = 2; pre_div < 256; pre_div *= 2)
	336	if ((sdhc_clk / pre_div) <= (clock * 16))
	337	break;
	338	} else
	339	pre_div = 2;
	340
	341	for (div = 1; div <= 16; div++)
	342	if ((sdhc_clk / (div * pre_div)) <= clock)
	343	break;
	344
	345	pre_div >>= 1;
	346	div -= 1;
	347
	348	clk = (pre_div << 8) \| (div << 4);
	349
cc4d1226	350	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
c67bee14 SB	351
c67bee14 SB	352	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
50586ef2 AF	353
	354	udelay(10000);
	355
cc4d1226	356	clk = SYSCTL_PEREN \| SYSCTL_CKEN;
c67bee14 SB	357
c67bee14 SB	358	esdhc_setbits32(&regs->sysctl, clk);
50586ef2 AF	359	}
	360
	361	static void esdhc_set_ios(struct mmc *mmc)
	362	{
c67bee14 SB	363	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	364	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	365
	366	/* Set the clock speed */
	367	set_sysctl(mmc, mmc->clock);
	368
	369	/* Set the bus width */
c67bee14	370	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 \| PROCTL_DTW_8);
50586ef2 AF	371
50586ef2 AF	372	if (mmc->bus_width == 4)
c67bee14	373	esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
50586ef2	374	else if (mmc->bus_width == 8)
c67bee14 SB	375	esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
c67bee14 SB	376
50586ef2 AF	377	}
	378
	379	static int esdhc_init(struct mmc *mmc)
	380	{
c67bee14 SB	381	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	382	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2	383	int timeout = 1000;
c67bee14 SB	384	int ret = 0;
c67bee14 SB	385	u8 card_absent;
50586ef2	386
c67bee14 SB	387	/* Reset the entire host controller */
	388	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
	389
	390	/* Wait until the controller is available */
	391	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	392	udelay(1000);
50586ef2	393
2c1764ef S	394	/* Enable cache snooping */
	395	if (cfg && !cfg->no_snoop)
	396	esdhc_write32(&regs->scr, 0x00000040);
	397
c67bee14	398	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN \| SYSCTL_IPGEN);
50586ef2 AF	399
50586ef2 AF	400	/* Set the initial clock speed */
4a6ee172	401	mmc_set_clock(mmc, 400000);
50586ef2 AF	402
50586ef2 AF	403	/* Disable the BRR and BWR bits in IRQSTAT */
c67bee14	404	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR \| IRQSTATEN_BWR);
50586ef2 AF	405
50586ef2 AF	406	/* Put the PROCTL reg back to the default */
c67bee14	407	esdhc_write32(&regs->proctl, PROCTL_INIT);
50586ef2	408
c67bee14 SB	409	/* Set timout to the maximum value */
c67bee14 SB	410	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
50586ef2	411
c67bee14 SB	412	/* Check if there is a callback for detecting the card */
	413	if (board_mmc_getcd(&card_absent, mmc)) {
	414	timeout = 1000;
	415	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) &&
	416	--timeout)
	417	udelay(1000);
50586ef2	418
c67bee14 SB	419	if (timeout <= 0)
	420	ret = NO_CARD_ERR;
	421	} else {
	422	if (card_absent)
	423	ret = NO_CARD_ERR;
	424	}
	425
	426	return ret;
50586ef2 AF	427	}
50586ef2 AF	428
48bb3bb5 JH	429	static void esdhc_reset(struct fsl_esdhc *regs)
	430	{
	431	unsigned long timeout = 100; /* wait max 100 ms */
	432
	433	/* reset the controller */
	434	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
	435
	436	/* hardware clears the bit when it is done */
	437	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	438	udelay(1000);
	439	if (!timeout)
	440	printf("MMC/SD: Reset never completed.\n");
	441	}
	442
c67bee14	443	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg)
50586ef2	444	{
c67bee14	445	struct fsl_esdhc *regs;
50586ef2	446	struct mmc *mmc;
030955c2	447	u32 caps, voltage_caps;
50586ef2	448
c67bee14 SB	449	if (!cfg)
	450	return -1;
	451
50586ef2 AF	452	mmc = malloc(sizeof(struct mmc));
	453
	454	sprintf(mmc->name, "FSL_ESDHC");
c67bee14 SB	455	regs = (struct fsl_esdhc *)cfg->esdhc_base;
c67bee14 SB	456
48bb3bb5 JH	457	/* First reset the eSDHC controller */
	458	esdhc_reset(regs);
	459
c67bee14	460	mmc->priv = cfg;
50586ef2 AF	461	mmc->send_cmd = esdhc_send_cmd;
	462	mmc->set_ios = esdhc_set_ios;
	463	mmc->init = esdhc_init;
	464
030955c2	465	voltage_caps = 0;
50586ef2	466	caps = regs->hostcapblt;
50586ef2	467	if (caps & ESDHC_HOSTCAPBLT_VS18)
030955c2	468	voltage_caps \|= MMC_VDD_165_195;
50586ef2	469	if (caps & ESDHC_HOSTCAPBLT_VS30)
030955c2	470	voltage_caps \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
50586ef2	471	if (caps & ESDHC_HOSTCAPBLT_VS33)
030955c2 LY	472	voltage_caps \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
	473
	474	#ifdef CONFIG_SYS_SD_VOLTAGE
	475	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
	476	#else
	477	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
	478	#endif
	479	if ((mmc->voltages & voltage_caps) == 0) {
	480	printf("voltage not supported by controller\n");
	481	return -1;
	482	}
50586ef2 AF	483
	484	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT;
	485
	486	if (caps & ESDHC_HOSTCAPBLT_HSS)
	487	mmc->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
	488
	489	mmc->f_min = 400000;
63786d29	490	mmc->f_max = MIN(gd->sdhc_clk, 52000000);
50586ef2 AF	491
	492	mmc_register(mmc);
	493
	494	return 0;
	495	}
	496
	497	int fsl_esdhc_mmc_init(bd_t *bis)
	498	{
c67bee14 SB	499	struct fsl_esdhc_cfg *cfg;
	500
	501	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
	502	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
	503	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
	504	return fsl_esdhc_initialize(bis, cfg);
50586ef2	505	}
b33433a6	506
c67bee14	507	#ifdef CONFIG_OF_LIBFDT
b33433a6 AV	508	void fdt_fixup_esdhc(void blob, bd_t bd)
	509	{
	510	const char *compat = "fsl,esdhc";
b33433a6	511
a6da8b81	512	#ifdef CONFIG_FSL_ESDHC_PIN_MUX
b33433a6	513	if (!hwconfig("esdhc")) {
a6da8b81 CZ	514	do_fixup_by_compat(blob, compat, "status", "disabled",
	515	8 + 1, 1);
	516	return;
b33433a6	517	}
a6da8b81	518	#endif
b33433a6 AV	519
	520	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
	521	gd->sdhc_clk, 1);
a6da8b81 CZ	522
	523	do_fixup_by_compat(blob, compat, "status", "okay",
	524	4 + 1, 1);
b33433a6	525	}
c67bee14	526	#endif