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mmc: Fixed a problem with old sd or mmc that do not support High speed
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
2051aefe 18#include <power/regulator.h>
272cc70b 19#include <malloc.h>
cf92e05c 20#include <memalign.h>
272cc70b 21#include <linux/list.h>
9b1f942c 22#include <div64.h>
da61fa5f 23#include "mmc_private.h"
272cc70b 24
3697e599
PF		 25static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31};
32
aff5d3c8 33static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
fb7c3beb 34static int mmc_power_cycle(struct mmc *mmc);
01298da3 35static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
aff5d3c8 36
b5b838f1
MV		 37#if CONFIG_IS_ENABLED(MMC_TINY)
38static struct mmc mmc_static;
39struct mmc *find_mmc_device(int dev_num)
40{
41 return &mmc_static;
42}
43
44void mmc_do_preinit(void)
45{
46 struct mmc *m = &mmc_static;
47#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
48 mmc_set_preinit(m, 1);
49#endif
50 if (m->preinit)
51 mmc_start_init(m);
52}
53
54struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
55{
56 return &mmc->block_dev;
57}
58#endif
59
e7881d85 60#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6
JJH		 61
62static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
63{
64 return -ENOSYS;
65}
66
750121c3 67__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 68{
69 return -1;
70}
71
72int mmc_getwp(struct mmc *mmc)
73{
74 int wp;
75
76 wp = board_mmc_getwp(mmc);
77
d4e1da4e 78 if (wp < 0) {
93bfd616
PA		 79 if (mmc->cfg->ops->getwp)
80 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 81 else
82 wp = 0;
83 }
d23d8d7e
NK		 84
85 return wp;
86}
87
cee9ab7c
JH		 88__weak int board_mmc_getcd(struct mmc *mmc)
89{
11fdade2
SB		 90 return -1;
91}
8ca51e51 92#endif
11fdade2 93
c0c76eba
SG		 94#ifdef CONFIG_MMC_TRACE
95void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 96{
c0c76eba
SG		 97 printf("CMD_SEND:%d\n", cmd->cmdidx);
98 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
99}
8635ff9e 100
c0c76eba
SG		 101void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
102{
5db2fe3a
RR		 103 int i;
104 u8 *ptr;
105
7863ce58
BM		 106 if (ret) {
107 printf("\t\tRET\t\t\t %d\n", ret);
108 } else {
109 switch (cmd->resp_type) {
110 case MMC_RSP_NONE:
111 printf("\t\tMMC_RSP_NONE\n");
112 break;
113 case MMC_RSP_R1:
114 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
115 cmd->response[0]);
116 break;
117 case MMC_RSP_R1b:
118 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
119 cmd->response[0]);
120 break;
121 case MMC_RSP_R2:
122 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
123 cmd->response[0]);
124 printf("\t\t \t\t 0x%08X \n",
125 cmd->response[1]);
126 printf("\t\t \t\t 0x%08X \n",
127 cmd->response[2]);
128 printf("\t\t \t\t 0x%08X \n",
129 cmd->response[3]);
5db2fe3a 130 printf("\n");
7863ce58
BM		 131 printf("\t\t\t\t\tDUMPING DATA\n");
132 for (i = 0; i < 4; i++) {
133 int j;
134 printf("\t\t\t\t\t%03d - ", i*4);
135 ptr = (u8 *)&cmd->response[i];
136 ptr += 3;
137 for (j = 0; j < 4; j++)
138 printf("%02X ", *ptr--);
139 printf("\n");
140 }
141 break;
142 case MMC_RSP_R3:
143 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
144 cmd->response[0]);
145 break;
146 default:
147 printf("\t\tERROR MMC rsp not supported\n");
148 break;
53e8e40b 149 }
5db2fe3a 150 }
c0c76eba
SG		 151}
152
153void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
154{
155 int status;
156
157 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
158 printf("CURR STATE:%d\n", status);
159}
5db2fe3a 160#endif
c0c76eba 161
35f9e196
JJH		 162#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
163const char *mmc_mode_name(enum bus_mode mode)
164{
165 static const char *const names[] = {
166 [MMC_LEGACY] = "MMC legacy",
167 [SD_LEGACY] = "SD Legacy",
168 [MMC_HS] = "MMC High Speed (26MHz)",
169 [SD_HS] = "SD High Speed (50MHz)",
170 [UHS_SDR12] = "UHS SDR12 (25MHz)",
171 [UHS_SDR25] = "UHS SDR25 (50MHz)",
172 [UHS_SDR50] = "UHS SDR50 (100MHz)",
173 [UHS_SDR104] = "UHS SDR104 (208MHz)",
174 [UHS_DDR50] = "UHS DDR50 (50MHz)",
175 [MMC_HS_52] = "MMC High Speed (52MHz)",
176 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
177 [MMC_HS_200] = "HS200 (200MHz)",
178 };
179
180 if (mode >= MMC_MODES_END)
181 return "Unknown mode";
182 else
183 return names[mode];
184}
185#endif
186
05038576
JJH		 187static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
188{
189 static const int freqs[] = {
190 [SD_LEGACY] = 25000000,
191 [MMC_HS] = 26000000,
192 [SD_HS] = 50000000,
193 [UHS_SDR12] = 25000000,
194 [UHS_SDR25] = 50000000,
195 [UHS_SDR50] = 100000000,
196 [UHS_SDR104] = 208000000,
197 [UHS_DDR50] = 50000000,
198 [MMC_HS_52] = 52000000,
199 [MMC_DDR_52] = 52000000,
200 [MMC_HS_200] = 200000000,
201 };
202
203 if (mode == MMC_LEGACY)
204 return mmc->legacy_speed;
205 else if (mode >= MMC_MODES_END)
206 return 0;
207 else
208 return freqs[mode];
209}
210
35f9e196
JJH		 211static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
212{
213 mmc->selected_mode = mode;
05038576 214 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 215 mmc->ddr_mode = mmc_is_mode_ddr(mode);
35f9e196
JJH		 216 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
217 mmc->tran_speed / 1000000);
218 return 0;
219}
220
e7881d85 221#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 222int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
223{
224 int ret;
225
226 mmmc_trace_before_send(mmc, cmd);
227 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
228 mmmc_trace_after_send(mmc, cmd, ret);
229
8635ff9e 230 return ret;
272cc70b 231}
8ca51e51 232#endif
272cc70b 233
da61fa5f 234int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 235{
236 struct mmc_cmd cmd;
d617c426 237 int err, retries = 5;
5d4fc8d9
RR		 238
239 cmd.cmdidx = MMC_CMD_SEND_STATUS;
240 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 241 if (!mmc_host_is_spi(mmc))
242 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 243
1677eef4 244 while (1) {
5d4fc8d9 245 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 246 if (!err) {
247 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
248 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
249 MMC_STATE_PRG)
250 break;
d0c221fe
JJH		 251
252 if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 253#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 254 printf("Status Error: 0x%08X\n",
255 cmd.response[0]);
56196826 256#endif
915ffa52 257 return -ECOMM;
d617c426
JK		 258 }
259 } else if (--retries < 0)
5d4fc8d9 260 return err;
5d4fc8d9 261
1677eef4
AG		 262 if (timeout-- <= 0)
263 break;
5d4fc8d9 264
1677eef4
AG		 265 udelay(1000);
266 }
5d4fc8d9 267
c0c76eba 268 mmc_trace_state(mmc, &cmd);
5b0c942f 269 if (timeout <= 0) {
56196826 270#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 271 printf("Timeout waiting card ready\n");
56196826 272#endif
915ffa52 273 return -ETIMEDOUT;
5d4fc8d9
RR		 274 }
275
276 return 0;
277}
278
da61fa5f 279int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 280{
281 struct mmc_cmd cmd;
83dc4227 282 int err;
272cc70b 283
786e8f81 284 if (mmc->ddr_mode)
d22e3d46
JC		 285 return 0;
286
272cc70b
AF		 287 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
288 cmd.resp_type = MMC_RSP_R1;
289 cmd.cmdarg = len;
272cc70b 290
83dc4227
KVA		 291 err = mmc_send_cmd(mmc, &cmd, NULL);
292
293#ifdef CONFIG_MMC_QUIRKS
294 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
295 int retries = 4;
296 /*
297 * It has been seen that SET_BLOCKLEN may fail on the first
298 * attempt, let's try a few more time
299 */
300 do {
301 err = mmc_send_cmd(mmc, &cmd, NULL);
302 if (!err)
303 break;
304 } while (retries--);
305 }
306#endif
307
308 return err;
272cc70b
AF		 309}
310
9815e3ba
JJH		 311static const u8 tuning_blk_pattern_4bit[] = {
312 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
313 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
314 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
315 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
316 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
317 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
318 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
319 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
320};
321
322static const u8 tuning_blk_pattern_8bit[] = {
323 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
324 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
325 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
326 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
327 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
328 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
329 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
330 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
331 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
332 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
333 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
334 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
335 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
336 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
337 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
338 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
339};
340
341int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
342{
343 struct mmc_cmd cmd;
344 struct mmc_data data;
345 const u8 *tuning_block_pattern;
346 int size, err;
347
348 if (mmc->bus_width == 8) {
349 tuning_block_pattern = tuning_blk_pattern_8bit;
350 size = sizeof(tuning_blk_pattern_8bit);
351 } else if (mmc->bus_width == 4) {
352 tuning_block_pattern = tuning_blk_pattern_4bit;
353 size = sizeof(tuning_blk_pattern_4bit);
354 } else {
355 return -EINVAL;
356 }
357
358 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
359
360 cmd.cmdidx = opcode;
361 cmd.cmdarg = 0;
362 cmd.resp_type = MMC_RSP_R1;
363
364 data.dest = (void *)data_buf;
365 data.blocks = 1;
366 data.blocksize = size;
367 data.flags = MMC_DATA_READ;
368
369 err = mmc_send_cmd(mmc, &cmd, &data);
370 if (err)
371 return err;
372
373 if (memcmp(data_buf, tuning_block_pattern, size))
374 return -EIO;
375
376 return 0;
377}
378
ff8fef56 379static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 380 lbaint_t blkcnt)
272cc70b
AF		 381{
382 struct mmc_cmd cmd;
383 struct mmc_data data;
384
4a1a06bc
AS		 385 if (blkcnt > 1)
386 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
387 else
388 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 389
390 if (mmc->high_capacity)
4a1a06bc 391 cmd.cmdarg = start;
272cc70b 392 else
4a1a06bc 393 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 394
395 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 396
397 data.dest = dst;
4a1a06bc 398 data.blocks = blkcnt;
272cc70b
AF		 399 data.blocksize = mmc->read_bl_len;
400 data.flags = MMC_DATA_READ;
401
4a1a06bc
AS		 402 if (mmc_send_cmd(mmc, &cmd, &data))
403 return 0;
272cc70b 404
4a1a06bc
AS		 405 if (blkcnt > 1) {
406 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
407 cmd.cmdarg = 0;
408 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 409 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 410#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 411 printf("mmc fail to send stop cmd\n");
56196826 412#endif
4a1a06bc
AS		 413 return 0;
414 }
272cc70b
AF		 415 }
416
4a1a06bc 417 return blkcnt;
272cc70b
AF		 418}
419
c4d660d4 420#if CONFIG_IS_ENABLED(BLK)
7dba0b93 421ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 422#else
7dba0b93
SG		 423ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
424 void *dst)
33fb211d 425#endif
272cc70b 426{
c4d660d4 427#if CONFIG_IS_ENABLED(BLK)
33fb211d
SG		 428 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
429#endif
bcce53d0 430 int dev_num = block_dev->devnum;
873cc1d7 431 int err;
4a1a06bc
AS		 432 lbaint_t cur, blocks_todo = blkcnt;
433
434 if (blkcnt == 0)
435 return 0;
272cc70b 436
4a1a06bc 437 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 438 if (!mmc)
439 return 0;
440
b5b838f1
MV		 441 if (CONFIG_IS_ENABLED(MMC_TINY))
442 err = mmc_switch_part(mmc, block_dev->hwpart);
443 else
444 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
445
873cc1d7
SW		 446 if (err < 0)
447 return 0;
448
c40fdca6 449 if ((start + blkcnt) > block_dev->lba) {
56196826 450#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 451 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
c40fdca6 452 start + blkcnt, block_dev->lba);
56196826 453#endif
d2bf29e3
LW		 454 return 0;
455 }
272cc70b 456
11692991
SG		 457 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
458 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 459 return 0;
11692991 460 }
272cc70b 461
4a1a06bc 462 do {
93bfd616
PA		 463 cur = (blocks_todo > mmc->cfg->b_max) ?
464 mmc->cfg->b_max : blocks_todo;
11692991
SG		 465 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
466 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 467 return 0;
11692991 468 }
4a1a06bc
AS		 469 blocks_todo -= cur;
470 start += cur;
471 dst += cur * mmc->read_bl_len;
472 } while (blocks_todo > 0);
272cc70b
AF		 473
474 return blkcnt;
475}
476
fdbb873e 477static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 478{
479 struct mmc_cmd cmd;
480 int err;
481
482 udelay(1000);
483
484 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
485 cmd.cmdarg = 0;
486 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 487
488 err = mmc_send_cmd(mmc, &cmd, NULL);
489
490 if (err)
491 return err;
492
493 udelay(2000);
494
495 return 0;
496}
497
c10b85d6
JJH		 498static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
499{
500 struct mmc_cmd cmd;
501 int err = 0;
502
503 /*
504 * Send CMD11 only if the request is to switch the card to
505 * 1.8V signalling.
506 */
507 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
508 return mmc_set_signal_voltage(mmc, signal_voltage);
509
510 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
511 cmd.cmdarg = 0;
512 cmd.resp_type = MMC_RSP_R1;
513
514 err = mmc_send_cmd(mmc, &cmd, NULL);
515 if (err)
516 return err;
517
518 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
519 return -EIO;
520
521 /*
522 * The card should drive cmd and dat[0:3] low immediately
523 * after the response of cmd11, but wait 100 us to be sure
524 */
525 err = mmc_wait_dat0(mmc, 0, 100);
526 if (err == -ENOSYS)
527 udelay(100);
528 else if (err)
529 return -ETIMEDOUT;
530
531 /*
532 * During a signal voltage level switch, the clock must be gated
533 * for 5 ms according to the SD spec
534 */
535 mmc_set_clock(mmc, mmc->clock, true);
536
537 err = mmc_set_signal_voltage(mmc, signal_voltage);
538 if (err)
539 return err;
540
541 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
542 mdelay(10);
543 mmc_set_clock(mmc, mmc->clock, false);
544
545 /*
546 * Failure to switch is indicated by the card holding
547 * dat[0:3] low. Wait for at least 1 ms according to spec
548 */
549 err = mmc_wait_dat0(mmc, 1, 1000);
550 if (err == -ENOSYS)
551 udelay(1000);
552 else if (err)
553 return -ETIMEDOUT;
554
555 return 0;
556}
557
558static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 559{
560 int timeout = 1000;
561 int err;
562 struct mmc_cmd cmd;
563
1677eef4 564 while (1) {
272cc70b
AF		 565 cmd.cmdidx = MMC_CMD_APP_CMD;
566 cmd.resp_type = MMC_RSP_R1;
567 cmd.cmdarg = 0;
272cc70b
AF		 568
569 err = mmc_send_cmd(mmc, &cmd, NULL);
570
571 if (err)
572 return err;
573
574 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
575 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 576
577 /*
578 * Most cards do not answer if some reserved bits
579 * in the ocr are set. However, Some controller
580 * can set bit 7 (reserved for low voltages), but
581 * how to manage low voltages SD card is not yet
582 * specified.
583 */
d52ebf10 584 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 585 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 586
587 if (mmc->version == SD_VERSION_2)
588 cmd.cmdarg |= OCR_HCS;
589
c10b85d6
JJH		 590 if (uhs_en)
591 cmd.cmdarg |= OCR_S18R;
592
272cc70b
AF		 593 err = mmc_send_cmd(mmc, &cmd, NULL);
594
595 if (err)
596 return err;
597
1677eef4
AG		 598 if (cmd.response[0] & OCR_BUSY)
599 break;
600
601 if (timeout-- <= 0)
915ffa52 602 return -EOPNOTSUPP;
272cc70b 603
1677eef4
AG		 604 udelay(1000);
605 }
272cc70b
AF		 606
607 if (mmc->version != SD_VERSION_2)
608 mmc->version = SD_VERSION_1_0;
609
d52ebf10
TC		 610 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
611 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
612 cmd.resp_type = MMC_RSP_R3;
613 cmd.cmdarg = 0;
d52ebf10
TC		 614
615 err = mmc_send_cmd(mmc, &cmd, NULL);
616
617 if (err)
618 return err;
619 }
620
998be3dd 621 mmc->ocr = cmd.response[0];
272cc70b 622
c10b85d6
JJH		 623 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
624 == 0x41000000) {
625 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
626 if (err)
627 return err;
628 }
629
272cc70b
AF		 630 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
631 mmc->rca = 0;
632
633 return 0;
634}
635
5289b535 636static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 637{
5289b535 638 struct mmc_cmd cmd;
272cc70b
AF		 639 int err;
640
5289b535
AG		 641 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
642 cmd.resp_type = MMC_RSP_R3;
643 cmd.cmdarg = 0;
5a20397b
RH		 644 if (use_arg && !mmc_host_is_spi(mmc))
645 cmd.cmdarg = OCR_HCS |
93bfd616 646 (mmc->cfg->voltages &
a626c8d4
AG		 647 (mmc->ocr & OCR_VOLTAGE_MASK)) |
648 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 649
5289b535 650 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 651 if (err)
652 return err;
5289b535 653 mmc->ocr = cmd.response[0];
e9550449
CLC		 654 return 0;
655}
656
750121c3 657static int mmc_send_op_cond(struct mmc *mmc)
e9550449 658{
e9550449
CLC		 659 int err, i;
660
272cc70b
AF		 661 /* Some cards seem to need this */
662 mmc_go_idle(mmc);
663
31cacbab 664 /* Asking to the card its capabilities */
e9550449 665 for (i = 0; i < 2; i++) {
5289b535 666 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 667 if (err)
668 return err;
cd6881b5 669
e9550449 670 /* exit if not busy (flag seems to be inverted) */
a626c8d4 671 if (mmc->ocr & OCR_BUSY)
bd47c135 672 break;
e9550449 673 }
bd47c135
AG		 674 mmc->op_cond_pending = 1;
675 return 0;
e9550449 676}
cd6881b5 677
750121c3 678static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 679{
680 struct mmc_cmd cmd;
681 int timeout = 1000;
682 uint start;
683 int err;
cd6881b5 684
e9550449 685 mmc->op_cond_pending = 0;
cc17c01f 686 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 687 /* Some cards seem to need this */
688 mmc_go_idle(mmc);
689
cc17c01f 690 start = get_timer(0);
1677eef4 691 while (1) {
cc17c01f
AG		 692 err = mmc_send_op_cond_iter(mmc, 1);
693 if (err)
694 return err;
1677eef4
AG		 695 if (mmc->ocr & OCR_BUSY)
696 break;
cc17c01f 697 if (get_timer(start) > timeout)
915ffa52 698 return -EOPNOTSUPP;
cc17c01f 699 udelay(100);
1677eef4 700 }
cc17c01f 701 }
272cc70b 702
d52ebf10
TC		 703 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
704 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
705 cmd.resp_type = MMC_RSP_R3;
706 cmd.cmdarg = 0;
d52ebf10
TC		 707
708 err = mmc_send_cmd(mmc, &cmd, NULL);
709
710 if (err)
711 return err;
a626c8d4
AG		 712
713 mmc->ocr = cmd.response[0];
d52ebf10
TC		 714 }
715
272cc70b 716 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 717
718 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 719 mmc->rca = 1;
272cc70b
AF		 720
721 return 0;
722}
723
724
fdbb873e 725static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 726{
727 struct mmc_cmd cmd;
728 struct mmc_data data;
729 int err;
730
731 /* Get the Card Status Register */
732 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
733 cmd.resp_type = MMC_RSP_R1;
734 cmd.cmdarg = 0;
272cc70b 735
cdfd1ac6 736 data.dest = (char *)ext_csd;
272cc70b 737 data.blocks = 1;
8bfa195e 738 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 739 data.flags = MMC_DATA_READ;
740
741 err = mmc_send_cmd(mmc, &cmd, &data);
742
743 return err;
744}
745
c40704f4 746int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 747{
748 struct mmc_cmd cmd;
5d4fc8d9 749 int timeout = 1000;
a9003dc6 750 int retries = 3;
5d4fc8d9 751 int ret;
272cc70b
AF		 752
753 cmd.cmdidx = MMC_CMD_SWITCH;
754 cmd.resp_type = MMC_RSP_R1b;
755 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 756 (index << 16) |
757 (value << 8);
272cc70b 758
a9003dc6
MR		 759 while (retries > 0) {
760 ret = mmc_send_cmd(mmc, &cmd, NULL);
5d4fc8d9 761
a9003dc6
MR		 762 /* Waiting for the ready status */
763 if (!ret) {
764 ret = mmc_send_status(mmc, timeout);
765 return ret;
766 }
767
768 retries--;
769 }
5d4fc8d9
RR		 770
771 return ret;
772
272cc70b
AF		 773}
774
3862b854 775static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
272cc70b 776{
272cc70b 777 int err;
3862b854
JJH		 778 int speed_bits;
779
780 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
781
782 switch (mode) {
783 case MMC_HS:
784 case MMC_HS_52:
785 case MMC_DDR_52:
786 speed_bits = EXT_CSD_TIMING_HS;
634d4849
KVA		 787 break;
788 case MMC_HS_200:
789 speed_bits = EXT_CSD_TIMING_HS200;
790 break;
3862b854
JJH		 791 case MMC_LEGACY:
792 speed_bits = EXT_CSD_TIMING_LEGACY;
793 break;
794 default:
795 return -EINVAL;
796 }
797 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
798 speed_bits);
799 if (err)
800 return err;
801
802 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
803 /* Now check to see that it worked */
804 err = mmc_send_ext_csd(mmc, test_csd);
805 if (err)
806 return err;
807
808 /* No high-speed support */
809 if (!test_csd[EXT_CSD_HS_TIMING])
810 return -ENOTSUPP;
811 }
812
813 return 0;
814}
815
816static int mmc_get_capabilities(struct mmc *mmc)
817{
818 u8 *ext_csd = mmc->ext_csd;
819 char cardtype;
272cc70b 820
00e446fa 821 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 822
d52ebf10
TC		 823 if (mmc_host_is_spi(mmc))
824 return 0;
825
272cc70b
AF		 826 /* Only version 4 supports high-speed */
827 if (mmc->version < MMC_VERSION_4)
828 return 0;
829
3862b854
JJH		 830 if (!ext_csd) {
831 printf("No ext_csd found!\n"); /* this should enver happen */
832 return -ENOTSUPP;
833 }
272cc70b 834
3862b854 835 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 836
634d4849 837 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
bc1e3272 838 mmc->cardtype = cardtype;
272cc70b 839
634d4849
KVA		 840 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
841 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
842 mmc->card_caps |= MMC_MODE_HS200;
843 }
d22e3d46 844 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 845 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 846 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 847 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 848 }
3862b854
JJH		 849 if (cardtype & EXT_CSD_CARD_TYPE_26)
850 mmc->card_caps |= MMC_MODE_HS;
272cc70b
AF		 851
852 return 0;
853}
854
f866a46d
SW		 855static int mmc_set_capacity(struct mmc *mmc, int part_num)
856{
857 switch (part_num) {
858 case 0:
859 mmc->capacity = mmc->capacity_user;
860 break;
861 case 1:
862 case 2:
863 mmc->capacity = mmc->capacity_boot;
864 break;
865 case 3:
866 mmc->capacity = mmc->capacity_rpmb;
867 break;
868 case 4:
869 case 5:
870 case 6:
871 case 7:
872 mmc->capacity = mmc->capacity_gp[part_num - 4];
873 break;
874 default:
875 return -1;
876 }
877
c40fdca6 878 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 879
880 return 0;
881}
882
01298da3
JJH		 883static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
884{
885 int forbidden = 0;
886 bool change = false;
887
888 if (part_num & PART_ACCESS_MASK)
889 forbidden = MMC_CAP(MMC_HS_200);
890
891 if (MMC_CAP(mmc->selected_mode) & forbidden) {
892 debug("selected mode (%s) is forbidden for part %d\n",
893 mmc_mode_name(mmc->selected_mode), part_num);
894 change = true;
895 } else if (mmc->selected_mode != mmc->best_mode) {
896 debug("selected mode is not optimal\n");
897 change = true;
898 }
899
900 if (change)
901 return mmc_select_mode_and_width(mmc,
902 mmc->card_caps & ~forbidden);
903
904 return 0;
905}
906
7dba0b93 907int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 908{
f866a46d 909 int ret;
bc897b1d 910
01298da3
JJH		 911 ret = mmc_boot_part_access_chk(mmc, part_num);
912 if (ret)
913 return ret;
914
f866a46d
SW		 915 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
916 (mmc->part_config & ~PART_ACCESS_MASK)
917 | (part_num & PART_ACCESS_MASK));
f866a46d 918
6dc93e70
PB		 919 /*
920 * Set the capacity if the switch succeeded or was intended
921 * to return to representing the raw device.
922 */
873cc1d7 923 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 924 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 925 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 926 }
6dc93e70
PB		 927
928 return ret;
bc897b1d
LW		 929}
930
ac9da0e0
DSC		 931int mmc_hwpart_config(struct mmc *mmc,
932 const struct mmc_hwpart_conf *conf,
933 enum mmc_hwpart_conf_mode mode)
934{
935 u8 part_attrs = 0;
936 u32 enh_size_mult;
937 u32 enh_start_addr;
938 u32 gp_size_mult[4];
939 u32 max_enh_size_mult;
940 u32 tot_enh_size_mult = 0;
8dda5b0e 941 u8 wr_rel_set;
ac9da0e0
DSC		 942 int i, pidx, err;
943 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
944
945 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
946 return -EINVAL;
947
948 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
949 printf("eMMC >= 4.4 required for enhanced user data area\n");
950 return -EMEDIUMTYPE;
951 }
952
953 if (!(mmc->part_support & PART_SUPPORT)) {
954 printf("Card does not support partitioning\n");
955 return -EMEDIUMTYPE;
956 }
957
958 if (!mmc->hc_wp_grp_size) {
959 printf("Card does not define HC WP group size\n");
960 return -EMEDIUMTYPE;
961 }
962
963 /* check partition alignment and total enhanced size */
964 if (conf->user.enh_size) {
965 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
966 conf->user.enh_start % mmc->hc_wp_grp_size) {
967 printf("User data enhanced area not HC WP group "
968 "size aligned\n");
969 return -EINVAL;
970 }
971 part_attrs |= EXT_CSD_ENH_USR;
972 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
973 if (mmc->high_capacity) {
974 enh_start_addr = conf->user.enh_start;
975 } else {
976 enh_start_addr = (conf->user.enh_start << 9);
977 }
978 } else {
979 enh_size_mult = 0;
980 enh_start_addr = 0;
981 }
982 tot_enh_size_mult += enh_size_mult;
983
984 for (pidx = 0; pidx < 4; pidx++) {
985 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
986 printf("GP%i partition not HC WP group size "
987 "aligned\n", pidx+1);
988 return -EINVAL;
989 }
990 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
991 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
992 part_attrs |= EXT_CSD_ENH_GP(pidx);
993 tot_enh_size_mult += gp_size_mult[pidx];
994 }
995 }
996
997 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
998 printf("Card does not support enhanced attribute\n");
999 return -EMEDIUMTYPE;
1000 }
1001
1002 err = mmc_send_ext_csd(mmc, ext_csd);
1003 if (err)
1004 return err;
1005
1006 max_enh_size_mult =
1007 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1008 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1009 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1010 if (tot_enh_size_mult > max_enh_size_mult) {
1011 printf("Total enhanced size exceeds maximum (%u > %u)\n",
1012 tot_enh_size_mult, max_enh_size_mult);
1013 return -EMEDIUMTYPE;
1014 }
1015
8dda5b0e
DSC		 1016 /* The default value of EXT_CSD_WR_REL_SET is device
1017 * dependent, the values can only be changed if the
1018 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1019 * changed only once and before partitioning is completed. */
1020 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1021 if (conf->user.wr_rel_change) {
1022 if (conf->user.wr_rel_set)
1023 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1024 else
1025 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1026 }
1027 for (pidx = 0; pidx < 4; pidx++) {
1028 if (conf->gp_part[pidx].wr_rel_change) {
1029 if (conf->gp_part[pidx].wr_rel_set)
1030 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1031 else
1032 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1033 }
1034 }
1035
1036 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1037 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1038 puts("Card does not support host controlled partition write "
1039 "reliability settings\n");
1040 return -EMEDIUMTYPE;
1041 }
1042
ac9da0e0
DSC		 1043 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1044 EXT_CSD_PARTITION_SETTING_COMPLETED) {
1045 printf("Card already partitioned\n");
1046 return -EPERM;
1047 }
1048
1049 if (mode == MMC_HWPART_CONF_CHECK)
1050 return 0;
1051
1052 /* Partitioning requires high-capacity size definitions */
1053 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1054 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1055 EXT_CSD_ERASE_GROUP_DEF, 1);
1056
1057 if (err)
1058 return err;
1059
1060 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1061
1062 /* update erase group size to be high-capacity */
1063 mmc->erase_grp_size =
1064 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1065
1066 }
1067
1068 /* all OK, write the configuration */
1069 for (i = 0; i < 4; i++) {
1070 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1071 EXT_CSD_ENH_START_ADDR+i,
1072 (enh_start_addr >> (i*8)) & 0xFF);
1073 if (err)
1074 return err;
1075 }
1076 for (i = 0; i < 3; i++) {
1077 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1078 EXT_CSD_ENH_SIZE_MULT+i,
1079 (enh_size_mult >> (i*8)) & 0xFF);
1080 if (err)
1081 return err;
1082 }
1083 for (pidx = 0; pidx < 4; pidx++) {
1084 for (i = 0; i < 3; i++) {
1085 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1086 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1087 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1088 if (err)
1089 return err;
1090 }
1091 }
1092 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1093 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1094 if (err)
1095 return err;
1096
1097 if (mode == MMC_HWPART_CONF_SET)
1098 return 0;
1099
8dda5b0e
DSC		 1100 /* The WR_REL_SET is a write-once register but shall be
1101 * written before setting PART_SETTING_COMPLETED. As it is
1102 * write-once we can only write it when completing the
1103 * partitioning. */
1104 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1105 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1106 EXT_CSD_WR_REL_SET, wr_rel_set);
1107 if (err)
1108 return err;
1109 }
1110
ac9da0e0
DSC		 1111 /* Setting PART_SETTING_COMPLETED confirms the partition
1112 * configuration but it only becomes effective after power
1113 * cycle, so we do not adjust the partition related settings
1114 * in the mmc struct. */
1115
1116 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1117 EXT_CSD_PARTITION_SETTING,
1118 EXT_CSD_PARTITION_SETTING_COMPLETED);
1119 if (err)
1120 return err;
1121
1122 return 0;
1123}
1124
e7881d85 1125#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1126int mmc_getcd(struct mmc *mmc)
1127{
1128 int cd;
1129
1130 cd = board_mmc_getcd(mmc);
1131
d4e1da4e 1132 if (cd < 0) {
93bfd616
PA		 1133 if (mmc->cfg->ops->getcd)
1134 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1135 else
1136 cd = 1;
1137 }
48972d90
TR		 1138
1139 return cd;
1140}
8ca51e51 1141#endif
48972d90 1142
fdbb873e 1143static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1144{
1145 struct mmc_cmd cmd;
1146 struct mmc_data data;
1147
1148 /* Switch the frequency */
1149 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1150 cmd.resp_type = MMC_RSP_R1;
1151 cmd.cmdarg = (mode << 31) | 0xffffff;
1152 cmd.cmdarg &= ~(0xf << (group * 4));
1153 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1154
1155 data.dest = (char *)resp;
1156 data.blocksize = 64;
1157 data.blocks = 1;
1158 data.flags = MMC_DATA_READ;
1159
1160 return mmc_send_cmd(mmc, &cmd, &data);
1161}
1162
1163
d0c221fe 1164static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1165{
1166 int err;
1167 struct mmc_cmd cmd;
18e7c8f6
SM		 1168 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1169 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1170 struct mmc_data data;
1171 int timeout;
c10b85d6 1172 u32 sd3_bus_mode;
272cc70b 1173
00e446fa 1174 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
272cc70b 1175
d52ebf10
TC		 1176 if (mmc_host_is_spi(mmc))
1177 return 0;
1178
272cc70b
AF		 1179 /* Read the SCR to find out if this card supports higher speeds */
1180 cmd.cmdidx = MMC_CMD_APP_CMD;
1181 cmd.resp_type = MMC_RSP_R1;
1182 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1183
1184 err = mmc_send_cmd(mmc, &cmd, NULL);
1185
1186 if (err)
1187 return err;
1188
1189 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1190 cmd.resp_type = MMC_RSP_R1;
1191 cmd.cmdarg = 0;
272cc70b
AF		 1192
1193 timeout = 3;
1194
1195retry_scr:
f781dd38 1196 data.dest = (char *)scr;
272cc70b
AF		 1197 data.blocksize = 8;
1198 data.blocks = 1;
1199 data.flags = MMC_DATA_READ;
1200
1201 err = mmc_send_cmd(mmc, &cmd, &data);
1202
1203 if (err) {
1204 if (timeout--)
1205 goto retry_scr;
1206
1207 return err;
1208 }
1209
4e3d89ba
YK		 1210 mmc->scr[0] = __be32_to_cpu(scr[0]);
1211 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1212
1213 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1214 case 0:
1215 mmc->version = SD_VERSION_1_0;
1216 break;
1217 case 1:
1218 mmc->version = SD_VERSION_1_10;
1219 break;
1220 case 2:
1221 mmc->version = SD_VERSION_2;
1222 if ((mmc->scr[0] >> 15) & 0x1)
1223 mmc->version = SD_VERSION_3;
1224 break;
1225 default:
1226 mmc->version = SD_VERSION_1_0;
1227 break;
272cc70b
AF		 1228 }
1229
b44c7083
AS		 1230 if (mmc->scr[0] & SD_DATA_4BIT)
1231 mmc->card_caps |= MMC_MODE_4BIT;
1232
272cc70b
AF		 1233 /* Version 1.0 doesn't support switching */
1234 if (mmc->version == SD_VERSION_1_0)
1235 return 0;
1236
1237 timeout = 4;
1238 while (timeout--) {
1239 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1240 (u8 *)switch_status);
272cc70b
AF		 1241
1242 if (err)
1243 return err;
1244
1245 /* The high-speed function is busy. Try again */
4e3d89ba 1246 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1247 break;
1248 }
1249
272cc70b 1250 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1251 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1252 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1253
c10b85d6
JJH		 1254 /* Version before 3.0 don't support UHS modes */
1255 if (mmc->version < SD_VERSION_3)
1256 return 0;
1257
1258 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1259 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1260 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1261 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1262 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1263 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1264 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1265 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1266 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1267 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1268 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1269
d0c221fe
JJH		 1270 return 0;
1271}
1272
1273static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1274{
1275 int err;
1276
1277 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1278 int speed;
2c3fbf4c 1279
c10b85d6
JJH		 1280 switch (mode) {
1281 case SD_LEGACY:
1282 case UHS_SDR12:
1283 speed = UHS_SDR12_BUS_SPEED;
1284 break;
1285 case SD_HS:
1286 case UHS_SDR25:
1287 speed = UHS_SDR25_BUS_SPEED;
1288 break;
1289 case UHS_SDR50:
1290 speed = UHS_SDR50_BUS_SPEED;
1291 break;
1292 case UHS_DDR50:
1293 speed = UHS_DDR50_BUS_SPEED;
1294 break;
1295 case UHS_SDR104:
1296 speed = UHS_SDR104_BUS_SPEED;
1297 break;
1298 default:
1299 return -EINVAL;
1300 }
1301
1302 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1303 if (err)
1304 return err;
1305
c10b85d6 1306 if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
d0c221fe 1307 return -ENOTSUPP;
272cc70b 1308
d0c221fe
JJH		 1309 return 0;
1310}
1311
1312int sd_select_bus_width(struct mmc *mmc, int w)
1313{
1314 int err;
1315 struct mmc_cmd cmd;
1316
1317 if ((w != 4) && (w != 1))
1318 return -EINVAL;
1319
1320 cmd.cmdidx = MMC_CMD_APP_CMD;
1321 cmd.resp_type = MMC_RSP_R1;
1322 cmd.cmdarg = mmc->rca << 16;
1323
1324 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1325 if (err)
1326 return err;
1327
d0c221fe
JJH		 1328 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1329 cmd.resp_type = MMC_RSP_R1;
1330 if (w == 4)
1331 cmd.cmdarg = 2;
1332 else if (w == 1)
1333 cmd.cmdarg = 0;
1334 err = mmc_send_cmd(mmc, &cmd, NULL);
1335 if (err)
1336 return err;
272cc70b
AF		 1337
1338 return 0;
1339}
1340
3697e599
PF		 1341static int sd_read_ssr(struct mmc *mmc)
1342{
1343 int err, i;
1344 struct mmc_cmd cmd;
1345 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1346 struct mmc_data data;
1347 int timeout = 3;
1348 unsigned int au, eo, et, es;
1349
1350 cmd.cmdidx = MMC_CMD_APP_CMD;
1351 cmd.resp_type = MMC_RSP_R1;
1352 cmd.cmdarg = mmc->rca << 16;
1353
1354 err = mmc_send_cmd(mmc, &cmd, NULL);
1355 if (err)
1356 return err;
1357
1358 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1359 cmd.resp_type = MMC_RSP_R1;
1360 cmd.cmdarg = 0;
1361
1362retry_ssr:
1363 data.dest = (char *)ssr;
1364 data.blocksize = 64;
1365 data.blocks = 1;
1366 data.flags = MMC_DATA_READ;
1367
1368 err = mmc_send_cmd(mmc, &cmd, &data);
1369 if (err) {
1370 if (timeout--)
1371 goto retry_ssr;
1372
1373 return err;
1374 }
1375
1376 for (i = 0; i < 16; i++)
1377 ssr[i] = be32_to_cpu(ssr[i]);
1378
1379 au = (ssr[2] >> 12) & 0xF;
1380 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1381 mmc->ssr.au = sd_au_size[au];
1382 es = (ssr[3] >> 24) & 0xFF;
1383 es |= (ssr[2] & 0xFF) << 8;
1384 et = (ssr[3] >> 18) & 0x3F;
1385 if (es && et) {
1386 eo = (ssr[3] >> 16) & 0x3;
1387 mmc->ssr.erase_timeout = (et * 1000) / es;
1388 mmc->ssr.erase_offset = eo * 1000;
1389 }
1390 } else {
1391 debug("Invalid Allocation Unit Size.\n");
1392 }
1393
1394 return 0;
1395}
1396
272cc70b
AF		 1397/* frequency bases */
1398/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1399static const int fbase[] = {
272cc70b
AF		 1400 10000,
1401 100000,
1402 1000000,
1403 10000000,
1404};
1405
1406/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1407 * to platforms without floating point.
1408 */
61fe076f 1409static const u8 multipliers[] = {
272cc70b
AF		 1410 0, /* reserved */
1411 10,
1412 12,
1413 13,
1414 15,
1415 20,
1416 25,
1417 30,
1418 35,
1419 40,
1420 45,
1421 50,
1422 55,
1423 60,
1424 70,
1425 80,
1426};
1427
d0c221fe
JJH		 1428static inline int bus_width(uint cap)
1429{
1430 if (cap == MMC_MODE_8BIT)
1431 return 8;
1432 if (cap == MMC_MODE_4BIT)
1433 return 4;
1434 if (cap == MMC_MODE_1BIT)
1435 return 1;
1436 printf("invalid bus witdh capability 0x%x\n", cap);
1437 return 0;
1438}
1439
e7881d85 1440#if !CONFIG_IS_ENABLED(DM_MMC)
ec841209
KVA		 1441static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1442{
1443 return -ENOTSUPP;
1444}
1445
318a7a57
JJH		 1446static void mmc_send_init_stream(struct mmc *mmc)
1447{
1448}
1449
2a4d212f 1450static int mmc_set_ios(struct mmc *mmc)
272cc70b 1451{
2a4d212f
KVA		 1452 int ret = 0;
1453
93bfd616 1454 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1455 ret = mmc->cfg->ops->set_ios(mmc);
1456
1457 return ret;
272cc70b 1458}
8ca51e51 1459#endif
272cc70b 1460
35f67820 1461int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1462{
93bfd616
PA		 1463 if (clock > mmc->cfg->f_max)
1464 clock = mmc->cfg->f_max;
272cc70b 1465
93bfd616
PA		 1466 if (clock < mmc->cfg->f_min)
1467 clock = mmc->cfg->f_min;
272cc70b
AF		 1468
1469 mmc->clock = clock;
35f67820 1470 mmc->clk_disable = disable;
272cc70b 1471
2a4d212f 1472 return mmc_set_ios(mmc);
272cc70b
AF		 1473}
1474
2a4d212f 1475static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1476{
1477 mmc->bus_width = width;
1478
2a4d212f 1479 return mmc_set_ios(mmc);
272cc70b
AF		 1480}
1481
4c9d2aaa
JJH		 1482#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1483/*
1484 * helper function to display the capabilities in a human
1485 * friendly manner. The capabilities include bus width and
1486 * supported modes.
1487 */
1488void mmc_dump_capabilities(const char *text, uint caps)
1489{
1490 enum bus_mode mode;
1491
1492 printf("%s: widths [", text);
1493 if (caps & MMC_MODE_8BIT)
1494 printf("8, ");
1495 if (caps & MMC_MODE_4BIT)
1496 printf("4, ");
d0c221fe
JJH		 1497 if (caps & MMC_MODE_1BIT)
1498 printf("1, ");
1499 printf("\b\b] modes [");
4c9d2aaa
JJH		 1500 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1501 if (MMC_CAP(mode) & caps)
1502 printf("%s, ", mmc_mode_name(mode));
1503 printf("\b\b]\n");
1504}
1505#endif
1506
d0c221fe
JJH		 1507struct mode_width_tuning {
1508 enum bus_mode mode;
1509 uint widths;
634d4849 1510 uint tuning;
d0c221fe
JJH		 1511};
1512
bc1e3272
JJH		 1513int mmc_voltage_to_mv(enum mmc_voltage voltage)
1514{
1515 switch (voltage) {
1516 case MMC_SIGNAL_VOLTAGE_000: return 0;
1517 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1518 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1519 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1520 }
1521 return -EINVAL;
1522}
1523
aff5d3c8
KVA		 1524static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1525{
bc1e3272
JJH		 1526 int err;
1527
1528 if (mmc->signal_voltage == signal_voltage)
1529 return 0;
1530
aff5d3c8 1531 mmc->signal_voltage = signal_voltage;
bc1e3272
JJH		 1532 err = mmc_set_ios(mmc);
1533 if (err)
1534 debug("unable to set voltage (err %d)\n", err);
1535
1536 return err;
aff5d3c8
KVA		 1537}
1538
d0c221fe 1539static const struct mode_width_tuning sd_modes_by_pref[] = {
c10b85d6
JJH		 1540 {
1541 .mode = UHS_SDR104,
1542 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1543 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1544 },
1545 {
1546 .mode = UHS_SDR50,
1547 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1548 },
1549 {
1550 .mode = UHS_DDR50,
1551 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1552 },
1553 {
1554 .mode = UHS_SDR25,
1555 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1556 },
d0c221fe
JJH		 1557 {
1558 .mode = SD_HS,
1559 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1560 },
c10b85d6
JJH		 1561 {
1562 .mode = UHS_SDR12,
1563 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1564 },
d0c221fe
JJH		 1565 {
1566 .mode = SD_LEGACY,
1567 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1568 }
1569};
1570
1571#define for_each_sd_mode_by_pref(caps, mwt) \
1572 for (mwt = sd_modes_by_pref;\
1573 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1574 mwt++) \
1575 if (caps & MMC_CAP(mwt->mode))
1576
01298da3 1577static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1578{
1579 int err;
d0c221fe
JJH		 1580 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1581 const struct mode_width_tuning *mwt;
c10b85d6
JJH		 1582 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1583 uint caps;
1584
52d241df
JJH		 1585#ifdef DEBUG
1586 mmc_dump_capabilities("sd card", card_caps);
1587 mmc_dump_capabilities("host", mmc->host_caps | MMC_MODE_1BIT);
1588#endif
8ac8a263 1589
8ac8a263 1590 /* Restrict card's capabilities by what the host can do */
01298da3 1591 caps = card_caps & (mmc->host_caps | MMC_MODE_1BIT);
d0c221fe 1592
c10b85d6
JJH		 1593 if (!uhs_en)
1594 caps &= ~UHS_CAPS;
1595
1596 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1597 uint *w;
1598
1599 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1600 if (*w & caps & mwt->widths) {
d0c221fe
JJH		 1601 debug("trying mode %s width %d (at %d MHz)\n",
1602 mmc_mode_name(mwt->mode),
1603 bus_width(*w),
1604 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1605
1606 /* configure the bus width (card + host) */
1607 err = sd_select_bus_width(mmc, bus_width(*w));
1608 if (err)
1609 goto error;
1610 mmc_set_bus_width(mmc, bus_width(*w));
1611
1612 /* configure the bus mode (card) */
1613 err = sd_set_card_speed(mmc, mwt->mode);
1614 if (err)
1615 goto error;
1616
1617 /* configure the bus mode (host) */
1618 mmc_select_mode(mmc, mwt->mode);
35f67820 1619 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe 1620
c10b85d6
JJH		 1621 /* execute tuning if needed */
1622 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1623 err = mmc_execute_tuning(mmc,
1624 mwt->tuning);
1625 if (err) {
1626 debug("tuning failed\n");
1627 goto error;
1628 }
1629 }
1630
d0c221fe
JJH		 1631 err = sd_read_ssr(mmc);
1632 if (!err)
1633 return 0;
1634
1635 printf("bad ssr\n");
1636
1637error:
1638 /* revert to a safer bus speed */
1639 mmc_select_mode(mmc, SD_LEGACY);
35f67820 1640 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe
JJH		 1641 }
1642 }
8ac8a263
JJH		 1643 }
1644
d0c221fe
JJH		 1645 printf("unable to select a mode\n");
1646 return -ENOTSUPP;
8ac8a263
JJH		 1647}
1648
7382e691
JJH		 1649/*
1650 * read the compare the part of ext csd that is constant.
1651 * This can be used to check that the transfer is working
1652 * as expected.
1653 */
1654static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1655{
7382e691 1656 int err;
dfda9d88 1657 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1658 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1659
1660 err = mmc_send_ext_csd(mmc, test_csd);
1661 if (err)
1662 return err;
1663
1664 /* Only compare read only fields */
1665 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1666 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1667 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1668 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1669 ext_csd[EXT_CSD_REV]
1670 == test_csd[EXT_CSD_REV] &&
1671 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1672 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1673 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1674 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1675 return 0;
1676
1677 return -EBADMSG;
1678}
1679
bc1e3272
JJH		 1680static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1681 uint32_t allowed_mask)
1682{
1683 u32 card_mask = 0;
1684
1685 switch (mode) {
1686 case MMC_HS_200:
1687 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
1688 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1689 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
1690 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1691 break;
1692 case MMC_DDR_52:
1693 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1694 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1695 MMC_SIGNAL_VOLTAGE_180;
1696 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1697 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1698 break;
1699 default:
1700 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1701 break;
1702 }
1703
1704 while (card_mask & allowed_mask) {
1705 enum mmc_voltage best_match;
1706
1707 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1708 if (!mmc_set_signal_voltage(mmc, best_match))
1709 return 0;
1710
1711 allowed_mask &= ~best_match;
1712 }
1713
1714 return -ENOTSUPP;
1715}
1716
3862b854
JJH		 1717static const struct mode_width_tuning mmc_modes_by_pref[] = {
1718 {
1719 .mode = MMC_HS_200,
1720 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1721 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854
JJH		 1722 },
1723 {
1724 .mode = MMC_DDR_52,
1725 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1726 },
1727 {
1728 .mode = MMC_HS_52,
1729 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1730 },
1731 {
1732 .mode = MMC_HS,
1733 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1734 },
1735 {
1736 .mode = MMC_LEGACY,
1737 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1738 }
1739};
1740
1741#define for_each_mmc_mode_by_pref(caps, mwt) \
1742 for (mwt = mmc_modes_by_pref;\
1743 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1744 mwt++) \
1745 if (caps & MMC_CAP(mwt->mode))
1746
1747static const struct ext_csd_bus_width {
1748 uint cap;
1749 bool is_ddr;
1750 uint ext_csd_bits;
1751} ext_csd_bus_width[] = {
1752 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1753 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1754 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1755 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1756 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1757};
1758
1759#define for_each_supported_width(caps, ddr, ecbv) \
1760 for (ecbv = ext_csd_bus_width;\
1761 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1762 ecbv++) \
1763 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1764
01298da3 1765static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 1766{
8ac8a263 1767 int err;
3862b854
JJH		 1768 const struct mode_width_tuning *mwt;
1769 const struct ext_csd_bus_width *ecbw;
8ac8a263 1770
52d241df
JJH		 1771#ifdef DEBUG
1772 mmc_dump_capabilities("mmc", card_caps);
1773 mmc_dump_capabilities("host", mmc->host_caps | MMC_MODE_1BIT);
1774#endif
1775
8ac8a263 1776 /* Restrict card's capabilities by what the host can do */
01298da3 1777 card_caps &= (mmc->host_caps | MMC_MODE_1BIT);
8ac8a263
JJH		 1778
1779 /* Only version 4 of MMC supports wider bus widths */
1780 if (mmc->version < MMC_VERSION_4)
1781 return 0;
1782
dfda9d88
JJH		 1783 if (!mmc->ext_csd) {
1784 debug("No ext_csd found!\n"); /* this should enver happen */
1785 return -ENOTSUPP;
1786 }
1787
01298da3
JJH		 1788 mmc_set_clock(mmc, mmc->legacy_speed, false);
1789
1790 for_each_mmc_mode_by_pref(card_caps, mwt) {
1791 for_each_supported_width(card_caps & mwt->widths,
3862b854 1792 mmc_is_mode_ddr(mwt->mode), ecbw) {
bc1e3272 1793 enum mmc_voltage old_voltage;
3862b854
JJH		 1794 debug("trying mode %s width %d (at %d MHz)\n",
1795 mmc_mode_name(mwt->mode),
1796 bus_width(ecbw->cap),
1797 mmc_mode2freq(mmc, mwt->mode) / 1000000);
bc1e3272
JJH		 1798 old_voltage = mmc->signal_voltage;
1799 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1800 MMC_ALL_SIGNAL_VOLTAGE);
1801 if (err)
1802 continue;
1803
3862b854
JJH		 1804 /* configure the bus width (card + host) */
1805 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1806 EXT_CSD_BUS_WIDTH,
1807 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1808 if (err)
1809 goto error;
1810 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 1811
3862b854
JJH		 1812 /* configure the bus speed (card) */
1813 err = mmc_set_card_speed(mmc, mwt->mode);
1814 if (err)
1815 goto error;
1816
1817 /*
1818 * configure the bus width AND the ddr mode (card)
1819 * The host side will be taken care of in the next step
1820 */
1821 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1822 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1823 EXT_CSD_BUS_WIDTH,
1824 ecbw->ext_csd_bits);
1825 if (err)
1826 goto error;
1827 }
8ac8a263 1828
3862b854
JJH		 1829 /* configure the bus mode (host) */
1830 mmc_select_mode(mmc, mwt->mode);
35f67820 1831 mmc_set_clock(mmc, mmc->tran_speed, false);
8ac8a263 1832
634d4849
KVA		 1833 /* execute tuning if needed */
1834 if (mwt->tuning) {
1835 err = mmc_execute_tuning(mmc, mwt->tuning);
1836 if (err) {
1837 debug("tuning failed\n");
1838 goto error;
1839 }
1840 }
1841
3862b854
JJH		 1842 /* do a transfer to check the configuration */
1843 err = mmc_read_and_compare_ext_csd(mmc);
1844 if (!err)
1845 return 0;
1846error:
bc1e3272 1847 mmc_set_signal_voltage(mmc, old_voltage);
3862b854
JJH		 1848 /* if an error occured, revert to a safer bus mode */
1849 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1850 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1851 mmc_select_mode(mmc, MMC_LEGACY);
1852 mmc_set_bus_width(mmc, 1);
1853 }
8ac8a263
JJH		 1854 }
1855
3862b854 1856 printf("unable to select a mode\n");
8ac8a263 1857
3862b854 1858 return -ENOTSUPP;
8ac8a263
JJH		 1859}
1860
dfda9d88 1861static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 1862{
1863 int err, i;
1864 u64 capacity;
1865 bool has_parts = false;
1866 bool part_completed;
dfda9d88 1867 u8 *ext_csd;
c744b6f6
JJH		 1868
1869 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1870 return 0;
1871
dfda9d88
JJH		 1872 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1873 if (!ext_csd)
1874 return -ENOMEM;
1875
1876 mmc->ext_csd = ext_csd;
1877
c744b6f6
JJH		 1878 /* check ext_csd version and capacity */
1879 err = mmc_send_ext_csd(mmc, ext_csd);
1880 if (err)
1881 return err;
1882 if (ext_csd[EXT_CSD_REV] >= 2) {
1883 /*
1884 * According to the JEDEC Standard, the value of
1885 * ext_csd's capacity is valid if the value is more
1886 * than 2GB
1887 */
1888 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1889 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1890 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1891 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1892 capacity *= MMC_MAX_BLOCK_LEN;
1893 if ((capacity >> 20) > 2 * 1024)
1894 mmc->capacity_user = capacity;
1895 }
1896
1897 switch (ext_csd[EXT_CSD_REV]) {
1898 case 1:
1899 mmc->version = MMC_VERSION_4_1;
1900 break;
1901 case 2:
1902 mmc->version = MMC_VERSION_4_2;
1903 break;
1904 case 3:
1905 mmc->version = MMC_VERSION_4_3;
1906 break;
1907 case 5:
1908 mmc->version = MMC_VERSION_4_41;
1909 break;
1910 case 6:
1911 mmc->version = MMC_VERSION_4_5;
1912 break;
1913 case 7:
1914 mmc->version = MMC_VERSION_5_0;
1915 break;
1916 case 8:
1917 mmc->version = MMC_VERSION_5_1;
1918 break;
1919 }
1920
1921 /* The partition data may be non-zero but it is only
1922 * effective if PARTITION_SETTING_COMPLETED is set in
1923 * EXT_CSD, so ignore any data if this bit is not set,
1924 * except for enabling the high-capacity group size
1925 * definition (see below).
1926 */
1927 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1928 EXT_CSD_PARTITION_SETTING_COMPLETED);
1929
1930 /* store the partition info of emmc */
1931 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1932 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1933 ext_csd[EXT_CSD_BOOT_MULT])
1934 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1935 if (part_completed &&
1936 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1937 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1938
1939 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1940
1941 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1942
1943 for (i = 0; i < 4; i++) {
1944 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1945 uint mult = (ext_csd[idx + 2] << 16) +
1946 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1947 if (mult)
1948 has_parts = true;
1949 if (!part_completed)
1950 continue;
1951 mmc->capacity_gp[i] = mult;
1952 mmc->capacity_gp[i] *=
1953 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1954 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1955 mmc->capacity_gp[i] <<= 19;
1956 }
1957
1958 if (part_completed) {
1959 mmc->enh_user_size =
1960 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1961 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1962 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1963 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1964 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1965 mmc->enh_user_size <<= 19;
1966 mmc->enh_user_start =
1967 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1968 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1969 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1970 ext_csd[EXT_CSD_ENH_START_ADDR];
1971 if (mmc->high_capacity)
1972 mmc->enh_user_start <<= 9;
1973 }
1974
1975 /*
1976 * Host needs to enable ERASE_GRP_DEF bit if device is
1977 * partitioned. This bit will be lost every time after a reset
1978 * or power off. This will affect erase size.
1979 */
1980 if (part_completed)
1981 has_parts = true;
1982 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1983 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1984 has_parts = true;
1985 if (has_parts) {
1986 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1987 EXT_CSD_ERASE_GROUP_DEF, 1);
1988
1989 if (err)
1990 return err;
1991
1992 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1993 }
1994
1995 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1996 /* Read out group size from ext_csd */
1997 mmc->erase_grp_size =
1998 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1999 /*
2000 * if high capacity and partition setting completed
2001 * SEC_COUNT is valid even if it is smaller than 2 GiB
2002 * JEDEC Standard JESD84-B45, 6.2.4
2003 */
2004 if (mmc->high_capacity && part_completed) {
2005 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2006 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2007 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2008 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2009 capacity *= MMC_MAX_BLOCK_LEN;
2010 mmc->capacity_user = capacity;
2011 }
2012 } else {
2013 /* Calculate the group size from the csd value. */
2014 int erase_gsz, erase_gmul;
2015
2016 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2017 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2018 mmc->erase_grp_size = (erase_gsz + 1)
2019 * (erase_gmul + 1);
2020 }
2021
2022 mmc->hc_wp_grp_size = 1024
2023 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2024 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2025
2026 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2027
2028 return 0;
2029}
2030
fdbb873e 2031static int mmc_startup(struct mmc *mmc)
272cc70b 2032{
f866a46d 2033 int err, i;
272cc70b 2034 uint mult, freq;
c744b6f6 2035 u64 cmult, csize;
272cc70b 2036 struct mmc_cmd cmd;
c40fdca6 2037 struct blk_desc *bdesc;
272cc70b 2038
d52ebf10
TC		 2039#ifdef CONFIG_MMC_SPI_CRC_ON
2040 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2041 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2042 cmd.resp_type = MMC_RSP_R1;
2043 cmd.cmdarg = 1;
d52ebf10 2044 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 2045 if (err)
2046 return err;
2047 }
2048#endif
2049
272cc70b 2050 /* Put the Card in Identify Mode */
d52ebf10
TC		 2051 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2052 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 2053 cmd.resp_type = MMC_RSP_R2;
2054 cmd.cmdarg = 0;
272cc70b
AF		 2055
2056 err = mmc_send_cmd(mmc, &cmd, NULL);
2057
83dc4227
KVA		 2058#ifdef CONFIG_MMC_QUIRKS
2059 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2060 int retries = 4;
2061 /*
2062 * It has been seen that SEND_CID may fail on the first
2063 * attempt, let's try a few more time
2064 */
2065 do {
2066 err = mmc_send_cmd(mmc, &cmd, NULL);
2067 if (!err)
2068 break;
2069 } while (retries--);
2070 }
2071#endif
2072
272cc70b
AF		 2073 if (err)
2074 return err;
2075
2076 memcpy(mmc->cid, cmd.response, 16);
2077
2078 /*
2079 * For MMC cards, set the Relative Address.
2080 * For SD cards, get the Relatvie Address.
2081 * This also puts the cards into Standby State
2082 */
d52ebf10
TC		 2083 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2084 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2085 cmd.cmdarg = mmc->rca << 16;
2086 cmd.resp_type = MMC_RSP_R6;
272cc70b 2087
d52ebf10 2088 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2089
d52ebf10
TC		 2090 if (err)
2091 return err;
272cc70b 2092
d52ebf10
TC		 2093 if (IS_SD(mmc))
2094 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2095 }
272cc70b
AF		 2096
2097 /* Get the Card-Specific Data */
2098 cmd.cmdidx = MMC_CMD_SEND_CSD;
2099 cmd.resp_type = MMC_RSP_R2;
2100 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 2101
2102 err = mmc_send_cmd(mmc, &cmd, NULL);
2103
2104 if (err)
2105 return err;
2106
998be3dd
RV		 2107 mmc->csd[0] = cmd.response[0];
2108 mmc->csd[1] = cmd.response[1];
2109 mmc->csd[2] = cmd.response[2];
2110 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 2111
2112 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 2113 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 2114
2115 switch (version) {
53e8e40b
BM		 2116 case 0:
2117 mmc->version = MMC_VERSION_1_2;
2118 break;
2119 case 1:
2120 mmc->version = MMC_VERSION_1_4;
2121 break;
2122 case 2:
2123 mmc->version = MMC_VERSION_2_2;
2124 break;
2125 case 3:
2126 mmc->version = MMC_VERSION_3;
2127 break;
2128 case 4:
2129 mmc->version = MMC_VERSION_4;
2130 break;
2131 default:
2132 mmc->version = MMC_VERSION_1_2;
2133 break;
272cc70b
AF		 2134 }
2135 }
2136
2137 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 2138 freq = fbase[(cmd.response[0] & 0x7)];
2139 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 2140
35f9e196 2141 mmc->legacy_speed = freq * mult;
35f9e196 2142 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2143
ab71188c 2144 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2145 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 2146
2147 if (IS_SD(mmc))
2148 mmc->write_bl_len = mmc->read_bl_len;
2149 else
998be3dd 2150 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 2151
2152 if (mmc->high_capacity) {
2153 csize = (mmc->csd[1] & 0x3f) << 16
2154 | (mmc->csd[2] & 0xffff0000) >> 16;
2155 cmult = 8;
2156 } else {
2157 csize = (mmc->csd[1] & 0x3ff) << 2
2158 | (mmc->csd[2] & 0xc0000000) >> 30;
2159 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2160 }
2161
f866a46d
SW		 2162 mmc->capacity_user = (csize + 1) << (cmult + 2);
2163 mmc->capacity_user *= mmc->read_bl_len;
2164 mmc->capacity_boot = 0;
2165 mmc->capacity_rpmb = 0;
2166 for (i = 0; i < 4; i++)
2167 mmc->capacity_gp[i] = 0;
272cc70b 2168
8bfa195e
SG		 2169 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2170 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2171
8bfa195e
SG		 2172 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2173 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2174
ab71188c
MN		 2175 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2176 cmd.cmdidx = MMC_CMD_SET_DSR;
2177 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2178 cmd.resp_type = MMC_RSP_NONE;
2179 if (mmc_send_cmd(mmc, &cmd, NULL))
2180 printf("MMC: SET_DSR failed\n");
2181 }
2182
272cc70b 2183 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2184 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2185 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2186 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2187 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2188 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2189
d52ebf10
TC		 2190 if (err)
2191 return err;
2192 }
272cc70b 2193
e6f99a56
LW		 2194 /*
2195 * For SD, its erase group is always one sector
2196 */
2197 mmc->erase_grp_size = 1;
bc897b1d 2198 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2199
dfda9d88 2200 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2201 if (err)
2202 return err;
d23e2c09 2203
c40fdca6 2204 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2205 if (err)
2206 return err;
2207
01298da3
JJH		 2208 if (IS_SD(mmc)) {
2209 err = sd_get_capabilities(mmc);
2210 if (err)
2211 return err;
2212 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2213 } else {
2214 err = mmc_get_capabilities(mmc);
2215 if (err)
2216 return err;
2217 mmc_select_mode_and_width(mmc, mmc->card_caps);
2218 }
272cc70b
AF		 2219
2220 if (err)
2221 return err;
2222
01298da3 2223 mmc->best_mode = mmc->selected_mode;
ad5fd922 2224
5af8f45c
AG		 2225 /* Fix the block length for DDR mode */
2226 if (mmc->ddr_mode) {
2227 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2228 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2229 }
2230
272cc70b 2231 /* fill in device description */
c40fdca6
SG		 2232 bdesc = mmc_get_blk_desc(mmc);
2233 bdesc->lun = 0;
2234 bdesc->hwpart = 0;
2235 bdesc->type = 0;
2236 bdesc->blksz = mmc->read_bl_len;
2237 bdesc->log2blksz = LOG2(bdesc->blksz);
2238 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2239#if !defined(CONFIG_SPL_BUILD) || \
2240 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2241 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 2242 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2243 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2244 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2245 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2246 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2247 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2248 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2249 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2250 (mmc->cid[2] >> 16) & 0xf);
56196826 2251#else
c40fdca6
SG		 2252 bdesc->vendor[0] = 0;
2253 bdesc->product[0] = 0;
2254 bdesc->revision[0] = 0;
56196826 2255#endif
122efd43 2256#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
c40fdca6 2257 part_init(bdesc);
122efd43 2258#endif
272cc70b
AF		 2259
2260 return 0;
2261}
2262
fdbb873e 2263static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2264{
2265 struct mmc_cmd cmd;
2266 int err;
2267
2268 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2269 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2270 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2271 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2272
2273 err = mmc_send_cmd(mmc, &cmd, NULL);
2274
2275 if (err)
2276 return err;
2277
998be3dd 2278 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2279 return -EOPNOTSUPP;
272cc70b
AF		 2280 else
2281 mmc->version = SD_VERSION_2;
2282
2283 return 0;
2284}
2285
c4d660d4 2286#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2287/* board-specific MMC power initializations. */
2288__weak void board_mmc_power_init(void)
2289{
2290}
05cbeb7c 2291#endif
95de9ab2 2292
2051aefe
PF		 2293static int mmc_power_init(struct mmc *mmc)
2294{
c4d660d4 2295#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2296#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2297 int ret;
2298
2299 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2300 &mmc->vmmc_supply);
2301 if (ret)
288db7c7 2302 debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2303
06ec045f
JJH		 2304 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2305 &mmc->vqmmc_supply);
2306 if (ret)
2307 debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2308#endif
2309#else /* !CONFIG_DM_MMC */
2310 /*
2311 * Driver model should use a regulator, as above, rather than calling
2312 * out to board code.
2313 */
2314 board_mmc_power_init();
2315#endif
2316 return 0;
2317}
2318
2319/*
2320 * put the host in the initial state:
2321 * - turn on Vdd (card power supply)
2322 * - configure the bus width and clock to minimal values
2323 */
2324static void mmc_set_initial_state(struct mmc *mmc)
2325{
2326 int err;
2327
2328 /* First try to set 3.3V. If it fails set to 1.8V */
2329 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2330 if (err != 0)
2331 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2332 if (err != 0)
2333 printf("mmc: failed to set signal voltage\n");
2334
2335 mmc_select_mode(mmc, MMC_LEGACY);
2336 mmc_set_bus_width(mmc, 1);
35f67820 2337 mmc_set_clock(mmc, 0, false);
fb7c3beb 2338}
06ec045f 2339
fb7c3beb
KVA		 2340static int mmc_power_on(struct mmc *mmc)
2341{
2342#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2343 if (mmc->vmmc_supply) {
fb7c3beb
KVA		 2344 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2345
06ec045f
JJH		 2346 if (ret) {
2347 puts("Error enabling VMMC supply\n");
2348 return ret;
2349 }
2051aefe 2350 }
05cbeb7c 2351#endif
fb7c3beb
KVA		 2352 return 0;
2353}
2354
2355static int mmc_power_off(struct mmc *mmc)
2356{
2e7410d7 2357 mmc_set_clock(mmc, 1, true);
fb7c3beb
KVA		 2358#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2359 if (mmc->vmmc_supply) {
2360 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2361
2362 if (ret) {
c10b85d6 2363 debug("Error disabling VMMC supply\n");
fb7c3beb
KVA		 2364 return ret;
2365 }
2366 }
2051aefe
PF		 2367#endif
2368 return 0;
2369}
2370
fb7c3beb
KVA		 2371static int mmc_power_cycle(struct mmc *mmc)
2372{
2373 int ret;
2374
2375 ret = mmc_power_off(mmc);
2376 if (ret)
2377 return ret;
2378 /*
2379 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2380 * to be on the safer side.
2381 */
2382 udelay(2000);
2383 return mmc_power_on(mmc);
2384}
2385
e9550449 2386int mmc_start_init(struct mmc *mmc)
272cc70b 2387{
8ca51e51 2388 bool no_card;
c10b85d6 2389 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2390 int err;
272cc70b 2391
04a2ea24
JJH		 2392 mmc->host_caps = mmc->cfg->host_caps;
2393
ab769f22 2394 /* we pretend there's no card when init is NULL */
8ca51e51 2395 no_card = mmc_getcd(mmc) == 0;
e7881d85 2396#if !CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2397 no_card = no_card || (mmc->cfg->ops->init == NULL);
2398#endif
2399 if (no_card) {
48972d90 2400 mmc->has_init = 0;
56196826 2401#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 2402 printf("MMC: no card present\n");
56196826 2403#endif
915ffa52 2404 return -ENOMEDIUM;
48972d90
TR		 2405 }
2406
bc897b1d
LW		 2407 if (mmc->has_init)
2408 return 0;
2409
5a8dbdc6
YL		 2410#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2411 mmc_adapter_card_type_ident();
2412#endif
2051aefe
PF		 2413 err = mmc_power_init(mmc);
2414 if (err)
2415 return err;
95de9ab2 2416
83dc4227
KVA		 2417#ifdef CONFIG_MMC_QUIRKS
2418 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2419 MMC_QUIRK_RETRY_SEND_CID;
2420#endif
2421
04a2ea24
JJH		 2422 err = mmc_power_cycle(mmc);
2423 if (err) {
2424 /*
2425 * if power cycling is not supported, we should not try
2426 * to use the UHS modes, because we wouldn't be able to
2427 * recover from an error during the UHS initialization.
2428 */
2429 debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2430 uhs_en = false;
2431 mmc->host_caps &= ~UHS_CAPS;
2432 err = mmc_power_on(mmc);
2433 }
fb7c3beb
KVA		 2434 if (err)
2435 return err;
2436
e7881d85 2437#if CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2438 /* The device has already been probed ready for use */
2439#else
ab769f22 2440 /* made sure it's not NULL earlier */
93bfd616 2441 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 2442 if (err)
2443 return err;
8ca51e51 2444#endif
786e8f81 2445 mmc->ddr_mode = 0;
aff5d3c8 2446
c10b85d6 2447retry:
fb7c3beb 2448 mmc_set_initial_state(mmc);
318a7a57
JJH		 2449 mmc_send_init_stream(mmc);
2450
272cc70b
AF		 2451 /* Reset the Card */
2452 err = mmc_go_idle(mmc);
2453
2454 if (err)
2455 return err;
2456
bc897b1d 2457 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 2458 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2459
272cc70b 2460 /* Test for SD version 2 */
afd5932b 2461 err = mmc_send_if_cond(mmc);
272cc70b 2462
272cc70b 2463 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2464 err = sd_send_op_cond(mmc, uhs_en);
2465 if (err && uhs_en) {
2466 uhs_en = false;
2467 mmc_power_cycle(mmc);
2468 goto retry;
2469 }
272cc70b
AF		 2470
2471 /* If the command timed out, we check for an MMC card */
915ffa52 2472 if (err == -ETIMEDOUT) {
272cc70b
AF		 2473 err = mmc_send_op_cond(mmc);
2474
bd47c135 2475 if (err) {
56196826 2476#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 2477 printf("Card did not respond to voltage select!\n");
56196826 2478#endif
915ffa52 2479 return -EOPNOTSUPP;
272cc70b
AF		 2480 }
2481 }
2482
bd47c135 2483 if (!err)
e9550449
CLC		 2484 mmc->init_in_progress = 1;
2485
2486 return err;
2487}
2488
2489static int mmc_complete_init(struct mmc *mmc)
2490{
2491 int err = 0;
2492
bd47c135 2493 mmc->init_in_progress = 0;
e9550449
CLC		 2494 if (mmc->op_cond_pending)
2495 err = mmc_complete_op_cond(mmc);
2496
2497 if (!err)
2498 err = mmc_startup(mmc);
bc897b1d
LW		 2499 if (err)
2500 mmc->has_init = 0;
2501 else
2502 mmc->has_init = 1;
e9550449
CLC		 2503 return err;
2504}
2505
2506int mmc_init(struct mmc *mmc)
2507{
bd47c135 2508 int err = 0;
ce9eca94 2509 __maybe_unused unsigned start;
c4d660d4 2510#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 2511 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 2512
33fb211d
SG		 2513 upriv->mmc = mmc;
2514#endif
e9550449
CLC		 2515 if (mmc->has_init)
2516 return 0;
d803fea5
MZ		 2517
2518 start = get_timer(0);
2519
e9550449
CLC		 2520 if (!mmc->init_in_progress)
2521 err = mmc_start_init(mmc);
2522
bd47c135 2523 if (!err)
e9550449 2524 err = mmc_complete_init(mmc);
919b4858
JT		 2525 if (err)
2526 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2527
bc897b1d 2528 return err;
272cc70b
AF		 2529}
2530
ab71188c
MN		 2531int mmc_set_dsr(struct mmc *mmc, u16 val)
2532{
2533 mmc->dsr = val;
2534 return 0;
2535}
2536
cee9ab7c
JH		 2537/* CPU-specific MMC initializations */
2538__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 2539{
2540 return -1;
2541}
2542
cee9ab7c
JH		 2543/* board-specific MMC initializations. */
2544__weak int board_mmc_init(bd_t *bis)
2545{
2546 return -1;
2547}
272cc70b 2548
e9550449
CLC		 2549void mmc_set_preinit(struct mmc *mmc, int preinit)
2550{
2551 mmc->preinit = preinit;
2552}
2553
c4d660d4 2554#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
8e3332e2
SS		 2555static int mmc_probe(bd_t *bis)
2556{
2557 return 0;
2558}
c4d660d4 2559#elif CONFIG_IS_ENABLED(DM_MMC)
8e3332e2
SS		 2560static int mmc_probe(bd_t *bis)
2561{
4a1db6d8 2562 int ret, i;
8e3332e2 2563 struct uclass *uc;
4a1db6d8 2564 struct udevice *dev;
8e3332e2
SS		 2565
2566 ret = uclass_get(UCLASS_MMC, &uc);
2567 if (ret)
2568 return ret;
2569
4a1db6d8
SG		 2570 /*
2571 * Try to add them in sequence order. Really with driver model we
2572 * should allow holes, but the current MMC list does not allow that.
2573 * So if we request 0, 1, 3 we will get 0, 1, 2.
2574 */
2575 for (i = 0; ; i++) {
2576 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2577 if (ret == -ENODEV)
2578 break;
2579 }
2580 uclass_foreach_dev(dev, uc) {
2581 ret = device_probe(dev);
8e3332e2 2582 if (ret)
4a1db6d8 2583 printf("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 2584 }
2585
2586 return 0;
2587}
2588#else
2589static int mmc_probe(bd_t *bis)
2590{
2591 if (board_mmc_init(bis) < 0)
2592 cpu_mmc_init(bis);
2593
2594 return 0;
2595}
2596#endif
e9550449 2597
272cc70b
AF		 2598int mmc_initialize(bd_t *bis)
2599{
1b26bab1 2600 static int initialized = 0;
8e3332e2 2601 int ret;
1b26bab1
DK		 2602 if (initialized) /* Avoid initializing mmc multiple times */
2603 return 0;
2604 initialized = 1;
2605
c4d660d4 2606#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 2607#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 2608 mmc_list_init();
b5b838f1 2609#endif
c40fdca6 2610#endif
8e3332e2
SS		 2611 ret = mmc_probe(bis);
2612 if (ret)
2613 return ret;
272cc70b 2614
bb0dc108 2615#ifndef CONFIG_SPL_BUILD
272cc70b 2616 print_mmc_devices(',');
bb0dc108 2617#endif
272cc70b 2618
c40fdca6 2619 mmc_do_preinit();
272cc70b
AF		 2620 return 0;
2621}
cd3d4880
TM		 2622
2623#ifdef CONFIG_CMD_BKOPS_ENABLE
2624int mmc_set_bkops_enable(struct mmc *mmc)
2625{
2626 int err;
2627 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2628
2629 err = mmc_send_ext_csd(mmc, ext_csd);
2630 if (err) {
2631 puts("Could not get ext_csd register values\n");
2632 return err;
2633 }
2634
2635 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2636 puts("Background operations not supported on device\n");
2637 return -EMEDIUMTYPE;
2638 }
2639
2640 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2641 puts("Background operations already enabled\n");
2642 return 0;
2643 }
2644
2645 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2646 if (err) {
2647 puts("Failed to enable manual background operations\n");
2648 return err;
2649 }
2650
2651 puts("Enabled manual background operations\n");
2652
2653 return 0;
2654}
2655#endif
"Das U-Boot" Source Tree