]>
Commit | Line | Data |
---|---|---|
272cc70b AF |
1 | /* |
2 | * Copyright 2008, Freescale Semiconductor, Inc | |
3 | * Andy Fleming | |
4 | * | |
5 | * Based vaguely on the Linux code | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
272cc70b AF |
8 | */ |
9 | ||
10 | #include <config.h> | |
11 | #include <common.h> | |
12 | #include <command.h> | |
8e3332e2 SS |
13 | #include <dm.h> |
14 | #include <dm/device-internal.h> | |
d4622df3 | 15 | #include <errno.h> |
272cc70b AF |
16 | #include <mmc.h> |
17 | #include <part.h> | |
2051aefe | 18 | #include <power/regulator.h> |
272cc70b | 19 | #include <malloc.h> |
cf92e05c | 20 | #include <memalign.h> |
272cc70b | 21 | #include <linux/list.h> |
9b1f942c | 22 | #include <div64.h> |
da61fa5f | 23 | #include "mmc_private.h" |
272cc70b | 24 | |
3697e599 PF |
25 | static const unsigned int sd_au_size[] = { |
26 | 0, SZ_16K / 512, SZ_32K / 512, | |
27 | SZ_64K / 512, SZ_128K / 512, SZ_256K / 512, | |
28 | SZ_512K / 512, SZ_1M / 512, SZ_2M / 512, | |
29 | SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512, | |
30 | SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512, | |
31 | }; | |
32 | ||
b5b838f1 MV |
33 | #if CONFIG_IS_ENABLED(MMC_TINY) |
34 | static struct mmc mmc_static; | |
35 | struct mmc *find_mmc_device(int dev_num) | |
36 | { | |
37 | return &mmc_static; | |
38 | } | |
39 | ||
40 | void mmc_do_preinit(void) | |
41 | { | |
42 | struct mmc *m = &mmc_static; | |
43 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT | |
44 | mmc_set_preinit(m, 1); | |
45 | #endif | |
46 | if (m->preinit) | |
47 | mmc_start_init(m); | |
48 | } | |
49 | ||
50 | struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) | |
51 | { | |
52 | return &mmc->block_dev; | |
53 | } | |
54 | #endif | |
55 | ||
e7881d85 | 56 | #if !CONFIG_IS_ENABLED(DM_MMC) |
750121c3 | 57 | __weak int board_mmc_getwp(struct mmc *mmc) |
d23d8d7e NK |
58 | { |
59 | return -1; | |
60 | } | |
61 | ||
62 | int mmc_getwp(struct mmc *mmc) | |
63 | { | |
64 | int wp; | |
65 | ||
66 | wp = board_mmc_getwp(mmc); | |
67 | ||
d4e1da4e | 68 | if (wp < 0) { |
93bfd616 PA |
69 | if (mmc->cfg->ops->getwp) |
70 | wp = mmc->cfg->ops->getwp(mmc); | |
d4e1da4e PK |
71 | else |
72 | wp = 0; | |
73 | } | |
d23d8d7e NK |
74 | |
75 | return wp; | |
76 | } | |
77 | ||
cee9ab7c JH |
78 | __weak int board_mmc_getcd(struct mmc *mmc) |
79 | { | |
11fdade2 SB |
80 | return -1; |
81 | } | |
8ca51e51 | 82 | #endif |
11fdade2 | 83 | |
c0c76eba SG |
84 | #ifdef CONFIG_MMC_TRACE |
85 | void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) | |
272cc70b | 86 | { |
c0c76eba SG |
87 | printf("CMD_SEND:%d\n", cmd->cmdidx); |
88 | printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); | |
89 | } | |
8635ff9e | 90 | |
c0c76eba SG |
91 | void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) |
92 | { | |
5db2fe3a RR |
93 | int i; |
94 | u8 *ptr; | |
95 | ||
7863ce58 BM |
96 | if (ret) { |
97 | printf("\t\tRET\t\t\t %d\n", ret); | |
98 | } else { | |
99 | switch (cmd->resp_type) { | |
100 | case MMC_RSP_NONE: | |
101 | printf("\t\tMMC_RSP_NONE\n"); | |
102 | break; | |
103 | case MMC_RSP_R1: | |
104 | printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", | |
105 | cmd->response[0]); | |
106 | break; | |
107 | case MMC_RSP_R1b: | |
108 | printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", | |
109 | cmd->response[0]); | |
110 | break; | |
111 | case MMC_RSP_R2: | |
112 | printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", | |
113 | cmd->response[0]); | |
114 | printf("\t\t \t\t 0x%08X \n", | |
115 | cmd->response[1]); | |
116 | printf("\t\t \t\t 0x%08X \n", | |
117 | cmd->response[2]); | |
118 | printf("\t\t \t\t 0x%08X \n", | |
119 | cmd->response[3]); | |
5db2fe3a | 120 | printf("\n"); |
7863ce58 BM |
121 | printf("\t\t\t\t\tDUMPING DATA\n"); |
122 | for (i = 0; i < 4; i++) { | |
123 | int j; | |
124 | printf("\t\t\t\t\t%03d - ", i*4); | |
125 | ptr = (u8 *)&cmd->response[i]; | |
126 | ptr += 3; | |
127 | for (j = 0; j < 4; j++) | |
128 | printf("%02X ", *ptr--); | |
129 | printf("\n"); | |
130 | } | |
131 | break; | |
132 | case MMC_RSP_R3: | |
133 | printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", | |
134 | cmd->response[0]); | |
135 | break; | |
136 | default: | |
137 | printf("\t\tERROR MMC rsp not supported\n"); | |
138 | break; | |
53e8e40b | 139 | } |
5db2fe3a | 140 | } |
c0c76eba SG |
141 | } |
142 | ||
143 | void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) | |
144 | { | |
145 | int status; | |
146 | ||
147 | status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9; | |
148 | printf("CURR STATE:%d\n", status); | |
149 | } | |
5db2fe3a | 150 | #endif |
c0c76eba | 151 | |
35f9e196 JJH |
152 | #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) |
153 | const char *mmc_mode_name(enum bus_mode mode) | |
154 | { | |
155 | static const char *const names[] = { | |
156 | [MMC_LEGACY] = "MMC legacy", | |
157 | [SD_LEGACY] = "SD Legacy", | |
158 | [MMC_HS] = "MMC High Speed (26MHz)", | |
159 | [SD_HS] = "SD High Speed (50MHz)", | |
160 | [UHS_SDR12] = "UHS SDR12 (25MHz)", | |
161 | [UHS_SDR25] = "UHS SDR25 (50MHz)", | |
162 | [UHS_SDR50] = "UHS SDR50 (100MHz)", | |
163 | [UHS_SDR104] = "UHS SDR104 (208MHz)", | |
164 | [UHS_DDR50] = "UHS DDR50 (50MHz)", | |
165 | [MMC_HS_52] = "MMC High Speed (52MHz)", | |
166 | [MMC_DDR_52] = "MMC DDR52 (52MHz)", | |
167 | [MMC_HS_200] = "HS200 (200MHz)", | |
168 | }; | |
169 | ||
170 | if (mode >= MMC_MODES_END) | |
171 | return "Unknown mode"; | |
172 | else | |
173 | return names[mode]; | |
174 | } | |
175 | #endif | |
176 | ||
05038576 JJH |
177 | static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) |
178 | { | |
179 | static const int freqs[] = { | |
180 | [SD_LEGACY] = 25000000, | |
181 | [MMC_HS] = 26000000, | |
182 | [SD_HS] = 50000000, | |
183 | [UHS_SDR12] = 25000000, | |
184 | [UHS_SDR25] = 50000000, | |
185 | [UHS_SDR50] = 100000000, | |
186 | [UHS_SDR104] = 208000000, | |
187 | [UHS_DDR50] = 50000000, | |
188 | [MMC_HS_52] = 52000000, | |
189 | [MMC_DDR_52] = 52000000, | |
190 | [MMC_HS_200] = 200000000, | |
191 | }; | |
192 | ||
193 | if (mode == MMC_LEGACY) | |
194 | return mmc->legacy_speed; | |
195 | else if (mode >= MMC_MODES_END) | |
196 | return 0; | |
197 | else | |
198 | return freqs[mode]; | |
199 | } | |
200 | ||
35f9e196 JJH |
201 | static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode) |
202 | { | |
203 | mmc->selected_mode = mode; | |
05038576 | 204 | mmc->tran_speed = mmc_mode2freq(mmc, mode); |
3862b854 | 205 | mmc->ddr_mode = mmc_is_mode_ddr(mode); |
35f9e196 JJH |
206 | debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode), |
207 | mmc->tran_speed / 1000000); | |
208 | return 0; | |
209 | } | |
210 | ||
e7881d85 | 211 | #if !CONFIG_IS_ENABLED(DM_MMC) |
c0c76eba SG |
212 | int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
213 | { | |
214 | int ret; | |
215 | ||
216 | mmmc_trace_before_send(mmc, cmd); | |
217 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); | |
218 | mmmc_trace_after_send(mmc, cmd, ret); | |
219 | ||
8635ff9e | 220 | return ret; |
272cc70b | 221 | } |
8ca51e51 | 222 | #endif |
272cc70b | 223 | |
da61fa5f | 224 | int mmc_send_status(struct mmc *mmc, int timeout) |
5d4fc8d9 RR |
225 | { |
226 | struct mmc_cmd cmd; | |
d617c426 | 227 | int err, retries = 5; |
5d4fc8d9 RR |
228 | |
229 | cmd.cmdidx = MMC_CMD_SEND_STATUS; | |
230 | cmd.resp_type = MMC_RSP_R1; | |
aaf3d41a MV |
231 | if (!mmc_host_is_spi(mmc)) |
232 | cmd.cmdarg = mmc->rca << 16; | |
5d4fc8d9 | 233 | |
1677eef4 | 234 | while (1) { |
5d4fc8d9 | 235 | err = mmc_send_cmd(mmc, &cmd, NULL); |
d617c426 JK |
236 | if (!err) { |
237 | if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && | |
238 | (cmd.response[0] & MMC_STATUS_CURR_STATE) != | |
239 | MMC_STATE_PRG) | |
240 | break; | |
d0c221fe JJH |
241 | |
242 | if (cmd.response[0] & MMC_STATUS_MASK) { | |
56196826 | 243 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
d617c426 JK |
244 | printf("Status Error: 0x%08X\n", |
245 | cmd.response[0]); | |
56196826 | 246 | #endif |
915ffa52 | 247 | return -ECOMM; |
d617c426 JK |
248 | } |
249 | } else if (--retries < 0) | |
5d4fc8d9 | 250 | return err; |
5d4fc8d9 | 251 | |
1677eef4 AG |
252 | if (timeout-- <= 0) |
253 | break; | |
5d4fc8d9 | 254 | |
1677eef4 AG |
255 | udelay(1000); |
256 | } | |
5d4fc8d9 | 257 | |
c0c76eba | 258 | mmc_trace_state(mmc, &cmd); |
5b0c942f | 259 | if (timeout <= 0) { |
56196826 | 260 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
5d4fc8d9 | 261 | printf("Timeout waiting card ready\n"); |
56196826 | 262 | #endif |
915ffa52 | 263 | return -ETIMEDOUT; |
5d4fc8d9 RR |
264 | } |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
da61fa5f | 269 | int mmc_set_blocklen(struct mmc *mmc, int len) |
272cc70b AF |
270 | { |
271 | struct mmc_cmd cmd; | |
272 | ||
786e8f81 | 273 | if (mmc->ddr_mode) |
d22e3d46 JC |
274 | return 0; |
275 | ||
272cc70b AF |
276 | cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; |
277 | cmd.resp_type = MMC_RSP_R1; | |
278 | cmd.cmdarg = len; | |
272cc70b AF |
279 | |
280 | return mmc_send_cmd(mmc, &cmd, NULL); | |
281 | } | |
282 | ||
ff8fef56 | 283 | static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, |
fdbb873e | 284 | lbaint_t blkcnt) |
272cc70b AF |
285 | { |
286 | struct mmc_cmd cmd; | |
287 | struct mmc_data data; | |
288 | ||
4a1a06bc AS |
289 | if (blkcnt > 1) |
290 | cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; | |
291 | else | |
292 | cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; | |
272cc70b AF |
293 | |
294 | if (mmc->high_capacity) | |
4a1a06bc | 295 | cmd.cmdarg = start; |
272cc70b | 296 | else |
4a1a06bc | 297 | cmd.cmdarg = start * mmc->read_bl_len; |
272cc70b AF |
298 | |
299 | cmd.resp_type = MMC_RSP_R1; | |
272cc70b AF |
300 | |
301 | data.dest = dst; | |
4a1a06bc | 302 | data.blocks = blkcnt; |
272cc70b AF |
303 | data.blocksize = mmc->read_bl_len; |
304 | data.flags = MMC_DATA_READ; | |
305 | ||
4a1a06bc AS |
306 | if (mmc_send_cmd(mmc, &cmd, &data)) |
307 | return 0; | |
272cc70b | 308 | |
4a1a06bc AS |
309 | if (blkcnt > 1) { |
310 | cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; | |
311 | cmd.cmdarg = 0; | |
312 | cmd.resp_type = MMC_RSP_R1b; | |
4a1a06bc | 313 | if (mmc_send_cmd(mmc, &cmd, NULL)) { |
56196826 | 314 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
4a1a06bc | 315 | printf("mmc fail to send stop cmd\n"); |
56196826 | 316 | #endif |
4a1a06bc AS |
317 | return 0; |
318 | } | |
272cc70b AF |
319 | } |
320 | ||
4a1a06bc | 321 | return blkcnt; |
272cc70b AF |
322 | } |
323 | ||
c4d660d4 | 324 | #if CONFIG_IS_ENABLED(BLK) |
7dba0b93 | 325 | ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) |
33fb211d | 326 | #else |
7dba0b93 SG |
327 | ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, |
328 | void *dst) | |
33fb211d | 329 | #endif |
272cc70b | 330 | { |
c4d660d4 | 331 | #if CONFIG_IS_ENABLED(BLK) |
33fb211d SG |
332 | struct blk_desc *block_dev = dev_get_uclass_platdata(dev); |
333 | #endif | |
bcce53d0 | 334 | int dev_num = block_dev->devnum; |
873cc1d7 | 335 | int err; |
4a1a06bc AS |
336 | lbaint_t cur, blocks_todo = blkcnt; |
337 | ||
338 | if (blkcnt == 0) | |
339 | return 0; | |
272cc70b | 340 | |
4a1a06bc | 341 | struct mmc *mmc = find_mmc_device(dev_num); |
272cc70b AF |
342 | if (!mmc) |
343 | return 0; | |
344 | ||
b5b838f1 MV |
345 | if (CONFIG_IS_ENABLED(MMC_TINY)) |
346 | err = mmc_switch_part(mmc, block_dev->hwpart); | |
347 | else | |
348 | err = blk_dselect_hwpart(block_dev, block_dev->hwpart); | |
349 | ||
873cc1d7 SW |
350 | if (err < 0) |
351 | return 0; | |
352 | ||
c40fdca6 | 353 | if ((start + blkcnt) > block_dev->lba) { |
56196826 | 354 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
ff8fef56 | 355 | printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", |
c40fdca6 | 356 | start + blkcnt, block_dev->lba); |
56196826 | 357 | #endif |
d2bf29e3 LW |
358 | return 0; |
359 | } | |
272cc70b | 360 | |
11692991 SG |
361 | if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { |
362 | debug("%s: Failed to set blocklen\n", __func__); | |
272cc70b | 363 | return 0; |
11692991 | 364 | } |
272cc70b | 365 | |
4a1a06bc | 366 | do { |
93bfd616 PA |
367 | cur = (blocks_todo > mmc->cfg->b_max) ? |
368 | mmc->cfg->b_max : blocks_todo; | |
11692991 SG |
369 | if (mmc_read_blocks(mmc, dst, start, cur) != cur) { |
370 | debug("%s: Failed to read blocks\n", __func__); | |
4a1a06bc | 371 | return 0; |
11692991 | 372 | } |
4a1a06bc AS |
373 | blocks_todo -= cur; |
374 | start += cur; | |
375 | dst += cur * mmc->read_bl_len; | |
376 | } while (blocks_todo > 0); | |
272cc70b AF |
377 | |
378 | return blkcnt; | |
379 | } | |
380 | ||
fdbb873e | 381 | static int mmc_go_idle(struct mmc *mmc) |
272cc70b AF |
382 | { |
383 | struct mmc_cmd cmd; | |
384 | int err; | |
385 | ||
386 | udelay(1000); | |
387 | ||
388 | cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; | |
389 | cmd.cmdarg = 0; | |
390 | cmd.resp_type = MMC_RSP_NONE; | |
272cc70b AF |
391 | |
392 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
393 | ||
394 | if (err) | |
395 | return err; | |
396 | ||
397 | udelay(2000); | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
fdbb873e | 402 | static int sd_send_op_cond(struct mmc *mmc) |
272cc70b AF |
403 | { |
404 | int timeout = 1000; | |
405 | int err; | |
406 | struct mmc_cmd cmd; | |
407 | ||
1677eef4 | 408 | while (1) { |
272cc70b AF |
409 | cmd.cmdidx = MMC_CMD_APP_CMD; |
410 | cmd.resp_type = MMC_RSP_R1; | |
411 | cmd.cmdarg = 0; | |
272cc70b AF |
412 | |
413 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
414 | ||
415 | if (err) | |
416 | return err; | |
417 | ||
418 | cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; | |
419 | cmd.resp_type = MMC_RSP_R3; | |
250de12b SB |
420 | |
421 | /* | |
422 | * Most cards do not answer if some reserved bits | |
423 | * in the ocr are set. However, Some controller | |
424 | * can set bit 7 (reserved for low voltages), but | |
425 | * how to manage low voltages SD card is not yet | |
426 | * specified. | |
427 | */ | |
d52ebf10 | 428 | cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : |
93bfd616 | 429 | (mmc->cfg->voltages & 0xff8000); |
272cc70b AF |
430 | |
431 | if (mmc->version == SD_VERSION_2) | |
432 | cmd.cmdarg |= OCR_HCS; | |
433 | ||
434 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
435 | ||
436 | if (err) | |
437 | return err; | |
438 | ||
1677eef4 AG |
439 | if (cmd.response[0] & OCR_BUSY) |
440 | break; | |
441 | ||
442 | if (timeout-- <= 0) | |
915ffa52 | 443 | return -EOPNOTSUPP; |
272cc70b | 444 | |
1677eef4 AG |
445 | udelay(1000); |
446 | } | |
272cc70b AF |
447 | |
448 | if (mmc->version != SD_VERSION_2) | |
449 | mmc->version = SD_VERSION_1_0; | |
450 | ||
d52ebf10 TC |
451 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
452 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
453 | cmd.resp_type = MMC_RSP_R3; | |
454 | cmd.cmdarg = 0; | |
d52ebf10 TC |
455 | |
456 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
457 | ||
458 | if (err) | |
459 | return err; | |
460 | } | |
461 | ||
998be3dd | 462 | mmc->ocr = cmd.response[0]; |
272cc70b AF |
463 | |
464 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
465 | mmc->rca = 0; | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
5289b535 | 470 | static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) |
272cc70b | 471 | { |
5289b535 | 472 | struct mmc_cmd cmd; |
272cc70b AF |
473 | int err; |
474 | ||
5289b535 AG |
475 | cmd.cmdidx = MMC_CMD_SEND_OP_COND; |
476 | cmd.resp_type = MMC_RSP_R3; | |
477 | cmd.cmdarg = 0; | |
5a20397b RH |
478 | if (use_arg && !mmc_host_is_spi(mmc)) |
479 | cmd.cmdarg = OCR_HCS | | |
93bfd616 | 480 | (mmc->cfg->voltages & |
a626c8d4 AG |
481 | (mmc->ocr & OCR_VOLTAGE_MASK)) | |
482 | (mmc->ocr & OCR_ACCESS_MODE); | |
e9550449 | 483 | |
5289b535 | 484 | err = mmc_send_cmd(mmc, &cmd, NULL); |
e9550449 CLC |
485 | if (err) |
486 | return err; | |
5289b535 | 487 | mmc->ocr = cmd.response[0]; |
e9550449 CLC |
488 | return 0; |
489 | } | |
490 | ||
750121c3 | 491 | static int mmc_send_op_cond(struct mmc *mmc) |
e9550449 | 492 | { |
e9550449 CLC |
493 | int err, i; |
494 | ||
272cc70b AF |
495 | /* Some cards seem to need this */ |
496 | mmc_go_idle(mmc); | |
497 | ||
31cacbab | 498 | /* Asking to the card its capabilities */ |
e9550449 | 499 | for (i = 0; i < 2; i++) { |
5289b535 | 500 | err = mmc_send_op_cond_iter(mmc, i != 0); |
e9550449 CLC |
501 | if (err) |
502 | return err; | |
cd6881b5 | 503 | |
e9550449 | 504 | /* exit if not busy (flag seems to be inverted) */ |
a626c8d4 | 505 | if (mmc->ocr & OCR_BUSY) |
bd47c135 | 506 | break; |
e9550449 | 507 | } |
bd47c135 AG |
508 | mmc->op_cond_pending = 1; |
509 | return 0; | |
e9550449 | 510 | } |
cd6881b5 | 511 | |
750121c3 | 512 | static int mmc_complete_op_cond(struct mmc *mmc) |
e9550449 CLC |
513 | { |
514 | struct mmc_cmd cmd; | |
515 | int timeout = 1000; | |
516 | uint start; | |
517 | int err; | |
cd6881b5 | 518 | |
e9550449 | 519 | mmc->op_cond_pending = 0; |
cc17c01f | 520 | if (!(mmc->ocr & OCR_BUSY)) { |
d188b113 YL |
521 | /* Some cards seem to need this */ |
522 | mmc_go_idle(mmc); | |
523 | ||
cc17c01f | 524 | start = get_timer(0); |
1677eef4 | 525 | while (1) { |
cc17c01f AG |
526 | err = mmc_send_op_cond_iter(mmc, 1); |
527 | if (err) | |
528 | return err; | |
1677eef4 AG |
529 | if (mmc->ocr & OCR_BUSY) |
530 | break; | |
cc17c01f | 531 | if (get_timer(start) > timeout) |
915ffa52 | 532 | return -EOPNOTSUPP; |
cc17c01f | 533 | udelay(100); |
1677eef4 | 534 | } |
cc17c01f | 535 | } |
272cc70b | 536 | |
d52ebf10 TC |
537 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
538 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
539 | cmd.resp_type = MMC_RSP_R3; | |
540 | cmd.cmdarg = 0; | |
d52ebf10 TC |
541 | |
542 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
543 | ||
544 | if (err) | |
545 | return err; | |
a626c8d4 AG |
546 | |
547 | mmc->ocr = cmd.response[0]; | |
d52ebf10 TC |
548 | } |
549 | ||
272cc70b | 550 | mmc->version = MMC_VERSION_UNKNOWN; |
272cc70b AF |
551 | |
552 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
def816a2 | 553 | mmc->rca = 1; |
272cc70b AF |
554 | |
555 | return 0; | |
556 | } | |
557 | ||
558 | ||
fdbb873e | 559 | static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) |
272cc70b AF |
560 | { |
561 | struct mmc_cmd cmd; | |
562 | struct mmc_data data; | |
563 | int err; | |
564 | ||
565 | /* Get the Card Status Register */ | |
566 | cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; | |
567 | cmd.resp_type = MMC_RSP_R1; | |
568 | cmd.cmdarg = 0; | |
272cc70b | 569 | |
cdfd1ac6 | 570 | data.dest = (char *)ext_csd; |
272cc70b | 571 | data.blocks = 1; |
8bfa195e | 572 | data.blocksize = MMC_MAX_BLOCK_LEN; |
272cc70b AF |
573 | data.flags = MMC_DATA_READ; |
574 | ||
575 | err = mmc_send_cmd(mmc, &cmd, &data); | |
576 | ||
577 | return err; | |
578 | } | |
579 | ||
c40704f4 | 580 | int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) |
272cc70b AF |
581 | { |
582 | struct mmc_cmd cmd; | |
5d4fc8d9 | 583 | int timeout = 1000; |
a9003dc6 | 584 | int retries = 3; |
5d4fc8d9 | 585 | int ret; |
272cc70b AF |
586 | |
587 | cmd.cmdidx = MMC_CMD_SWITCH; | |
588 | cmd.resp_type = MMC_RSP_R1b; | |
589 | cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | | |
5d4fc8d9 RR |
590 | (index << 16) | |
591 | (value << 8); | |
272cc70b | 592 | |
a9003dc6 MR |
593 | while (retries > 0) { |
594 | ret = mmc_send_cmd(mmc, &cmd, NULL); | |
5d4fc8d9 | 595 | |
a9003dc6 MR |
596 | /* Waiting for the ready status */ |
597 | if (!ret) { | |
598 | ret = mmc_send_status(mmc, timeout); | |
599 | return ret; | |
600 | } | |
601 | ||
602 | retries--; | |
603 | } | |
5d4fc8d9 RR |
604 | |
605 | return ret; | |
606 | ||
272cc70b AF |
607 | } |
608 | ||
3862b854 | 609 | static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) |
272cc70b | 610 | { |
272cc70b | 611 | int err; |
3862b854 JJH |
612 | int speed_bits; |
613 | ||
614 | ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); | |
615 | ||
616 | switch (mode) { | |
617 | case MMC_HS: | |
618 | case MMC_HS_52: | |
619 | case MMC_DDR_52: | |
620 | speed_bits = EXT_CSD_TIMING_HS; | |
621 | case MMC_LEGACY: | |
622 | speed_bits = EXT_CSD_TIMING_LEGACY; | |
623 | break; | |
624 | default: | |
625 | return -EINVAL; | |
626 | } | |
627 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, | |
628 | speed_bits); | |
629 | if (err) | |
630 | return err; | |
631 | ||
632 | if ((mode == MMC_HS) || (mode == MMC_HS_52)) { | |
633 | /* Now check to see that it worked */ | |
634 | err = mmc_send_ext_csd(mmc, test_csd); | |
635 | if (err) | |
636 | return err; | |
637 | ||
638 | /* No high-speed support */ | |
639 | if (!test_csd[EXT_CSD_HS_TIMING]) | |
640 | return -ENOTSUPP; | |
641 | } | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | static int mmc_get_capabilities(struct mmc *mmc) | |
647 | { | |
648 | u8 *ext_csd = mmc->ext_csd; | |
649 | char cardtype; | |
272cc70b | 650 | |
d0c221fe | 651 | mmc->card_caps = MMC_MODE_1BIT; |
272cc70b | 652 | |
d52ebf10 TC |
653 | if (mmc_host_is_spi(mmc)) |
654 | return 0; | |
655 | ||
272cc70b AF |
656 | /* Only version 4 supports high-speed */ |
657 | if (mmc->version < MMC_VERSION_4) | |
658 | return 0; | |
659 | ||
3862b854 JJH |
660 | if (!ext_csd) { |
661 | printf("No ext_csd found!\n"); /* this should enver happen */ | |
662 | return -ENOTSUPP; | |
663 | } | |
272cc70b | 664 | |
3862b854 | 665 | mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; |
272cc70b | 666 | |
0560db18 | 667 | cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; |
272cc70b | 668 | |
272cc70b | 669 | /* High Speed is set, there are two types: 52MHz and 26MHz */ |
d22e3d46 | 670 | if (cardtype & EXT_CSD_CARD_TYPE_52) { |
3862b854 | 671 | if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) |
d22e3d46 | 672 | mmc->card_caps |= MMC_MODE_DDR_52MHz; |
3862b854 | 673 | mmc->card_caps |= MMC_MODE_HS_52MHz; |
d22e3d46 | 674 | } |
3862b854 JJH |
675 | if (cardtype & EXT_CSD_CARD_TYPE_26) |
676 | mmc->card_caps |= MMC_MODE_HS; | |
272cc70b AF |
677 | |
678 | return 0; | |
679 | } | |
680 | ||
f866a46d SW |
681 | static int mmc_set_capacity(struct mmc *mmc, int part_num) |
682 | { | |
683 | switch (part_num) { | |
684 | case 0: | |
685 | mmc->capacity = mmc->capacity_user; | |
686 | break; | |
687 | case 1: | |
688 | case 2: | |
689 | mmc->capacity = mmc->capacity_boot; | |
690 | break; | |
691 | case 3: | |
692 | mmc->capacity = mmc->capacity_rpmb; | |
693 | break; | |
694 | case 4: | |
695 | case 5: | |
696 | case 6: | |
697 | case 7: | |
698 | mmc->capacity = mmc->capacity_gp[part_num - 4]; | |
699 | break; | |
700 | default: | |
701 | return -1; | |
702 | } | |
703 | ||
c40fdca6 | 704 | mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); |
f866a46d SW |
705 | |
706 | return 0; | |
707 | } | |
708 | ||
7dba0b93 | 709 | int mmc_switch_part(struct mmc *mmc, unsigned int part_num) |
bc897b1d | 710 | { |
f866a46d | 711 | int ret; |
bc897b1d | 712 | |
f866a46d SW |
713 | ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, |
714 | (mmc->part_config & ~PART_ACCESS_MASK) | |
715 | | (part_num & PART_ACCESS_MASK)); | |
f866a46d | 716 | |
6dc93e70 PB |
717 | /* |
718 | * Set the capacity if the switch succeeded or was intended | |
719 | * to return to representing the raw device. | |
720 | */ | |
873cc1d7 | 721 | if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { |
6dc93e70 | 722 | ret = mmc_set_capacity(mmc, part_num); |
fdbb139f | 723 | mmc_get_blk_desc(mmc)->hwpart = part_num; |
873cc1d7 | 724 | } |
6dc93e70 PB |
725 | |
726 | return ret; | |
bc897b1d LW |
727 | } |
728 | ||
ac9da0e0 DSC |
729 | int mmc_hwpart_config(struct mmc *mmc, |
730 | const struct mmc_hwpart_conf *conf, | |
731 | enum mmc_hwpart_conf_mode mode) | |
732 | { | |
733 | u8 part_attrs = 0; | |
734 | u32 enh_size_mult; | |
735 | u32 enh_start_addr; | |
736 | u32 gp_size_mult[4]; | |
737 | u32 max_enh_size_mult; | |
738 | u32 tot_enh_size_mult = 0; | |
8dda5b0e | 739 | u8 wr_rel_set; |
ac9da0e0 DSC |
740 | int i, pidx, err; |
741 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); | |
742 | ||
743 | if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) | |
744 | return -EINVAL; | |
745 | ||
746 | if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { | |
747 | printf("eMMC >= 4.4 required for enhanced user data area\n"); | |
748 | return -EMEDIUMTYPE; | |
749 | } | |
750 | ||
751 | if (!(mmc->part_support & PART_SUPPORT)) { | |
752 | printf("Card does not support partitioning\n"); | |
753 | return -EMEDIUMTYPE; | |
754 | } | |
755 | ||
756 | if (!mmc->hc_wp_grp_size) { | |
757 | printf("Card does not define HC WP group size\n"); | |
758 | return -EMEDIUMTYPE; | |
759 | } | |
760 | ||
761 | /* check partition alignment and total enhanced size */ | |
762 | if (conf->user.enh_size) { | |
763 | if (conf->user.enh_size % mmc->hc_wp_grp_size || | |
764 | conf->user.enh_start % mmc->hc_wp_grp_size) { | |
765 | printf("User data enhanced area not HC WP group " | |
766 | "size aligned\n"); | |
767 | return -EINVAL; | |
768 | } | |
769 | part_attrs |= EXT_CSD_ENH_USR; | |
770 | enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; | |
771 | if (mmc->high_capacity) { | |
772 | enh_start_addr = conf->user.enh_start; | |
773 | } else { | |
774 | enh_start_addr = (conf->user.enh_start << 9); | |
775 | } | |
776 | } else { | |
777 | enh_size_mult = 0; | |
778 | enh_start_addr = 0; | |
779 | } | |
780 | tot_enh_size_mult += enh_size_mult; | |
781 | ||
782 | for (pidx = 0; pidx < 4; pidx++) { | |
783 | if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { | |
784 | printf("GP%i partition not HC WP group size " | |
785 | "aligned\n", pidx+1); | |
786 | return -EINVAL; | |
787 | } | |
788 | gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; | |
789 | if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { | |
790 | part_attrs |= EXT_CSD_ENH_GP(pidx); | |
791 | tot_enh_size_mult += gp_size_mult[pidx]; | |
792 | } | |
793 | } | |
794 | ||
795 | if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { | |
796 | printf("Card does not support enhanced attribute\n"); | |
797 | return -EMEDIUMTYPE; | |
798 | } | |
799 | ||
800 | err = mmc_send_ext_csd(mmc, ext_csd); | |
801 | if (err) | |
802 | return err; | |
803 | ||
804 | max_enh_size_mult = | |
805 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + | |
806 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + | |
807 | ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; | |
808 | if (tot_enh_size_mult > max_enh_size_mult) { | |
809 | printf("Total enhanced size exceeds maximum (%u > %u)\n", | |
810 | tot_enh_size_mult, max_enh_size_mult); | |
811 | return -EMEDIUMTYPE; | |
812 | } | |
813 | ||
8dda5b0e DSC |
814 | /* The default value of EXT_CSD_WR_REL_SET is device |
815 | * dependent, the values can only be changed if the | |
816 | * EXT_CSD_HS_CTRL_REL bit is set. The values can be | |
817 | * changed only once and before partitioning is completed. */ | |
818 | wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
819 | if (conf->user.wr_rel_change) { | |
820 | if (conf->user.wr_rel_set) | |
821 | wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; | |
822 | else | |
823 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; | |
824 | } | |
825 | for (pidx = 0; pidx < 4; pidx++) { | |
826 | if (conf->gp_part[pidx].wr_rel_change) { | |
827 | if (conf->gp_part[pidx].wr_rel_set) | |
828 | wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); | |
829 | else | |
830 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); | |
831 | } | |
832 | } | |
833 | ||
834 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && | |
835 | !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { | |
836 | puts("Card does not support host controlled partition write " | |
837 | "reliability settings\n"); | |
838 | return -EMEDIUMTYPE; | |
839 | } | |
840 | ||
ac9da0e0 DSC |
841 | if (ext_csd[EXT_CSD_PARTITION_SETTING] & |
842 | EXT_CSD_PARTITION_SETTING_COMPLETED) { | |
843 | printf("Card already partitioned\n"); | |
844 | return -EPERM; | |
845 | } | |
846 | ||
847 | if (mode == MMC_HWPART_CONF_CHECK) | |
848 | return 0; | |
849 | ||
850 | /* Partitioning requires high-capacity size definitions */ | |
851 | if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { | |
852 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
853 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
854 | ||
855 | if (err) | |
856 | return err; | |
857 | ||
858 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
859 | ||
860 | /* update erase group size to be high-capacity */ | |
861 | mmc->erase_grp_size = | |
862 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; | |
863 | ||
864 | } | |
865 | ||
866 | /* all OK, write the configuration */ | |
867 | for (i = 0; i < 4; i++) { | |
868 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
869 | EXT_CSD_ENH_START_ADDR+i, | |
870 | (enh_start_addr >> (i*8)) & 0xFF); | |
871 | if (err) | |
872 | return err; | |
873 | } | |
874 | for (i = 0; i < 3; i++) { | |
875 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
876 | EXT_CSD_ENH_SIZE_MULT+i, | |
877 | (enh_size_mult >> (i*8)) & 0xFF); | |
878 | if (err) | |
879 | return err; | |
880 | } | |
881 | for (pidx = 0; pidx < 4; pidx++) { | |
882 | for (i = 0; i < 3; i++) { | |
883 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
884 | EXT_CSD_GP_SIZE_MULT+pidx*3+i, | |
885 | (gp_size_mult[pidx] >> (i*8)) & 0xFF); | |
886 | if (err) | |
887 | return err; | |
888 | } | |
889 | } | |
890 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
891 | EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); | |
892 | if (err) | |
893 | return err; | |
894 | ||
895 | if (mode == MMC_HWPART_CONF_SET) | |
896 | return 0; | |
897 | ||
8dda5b0e DSC |
898 | /* The WR_REL_SET is a write-once register but shall be |
899 | * written before setting PART_SETTING_COMPLETED. As it is | |
900 | * write-once we can only write it when completing the | |
901 | * partitioning. */ | |
902 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { | |
903 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
904 | EXT_CSD_WR_REL_SET, wr_rel_set); | |
905 | if (err) | |
906 | return err; | |
907 | } | |
908 | ||
ac9da0e0 DSC |
909 | /* Setting PART_SETTING_COMPLETED confirms the partition |
910 | * configuration but it only becomes effective after power | |
911 | * cycle, so we do not adjust the partition related settings | |
912 | * in the mmc struct. */ | |
913 | ||
914 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
915 | EXT_CSD_PARTITION_SETTING, | |
916 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
917 | if (err) | |
918 | return err; | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
e7881d85 | 923 | #if !CONFIG_IS_ENABLED(DM_MMC) |
48972d90 TR |
924 | int mmc_getcd(struct mmc *mmc) |
925 | { | |
926 | int cd; | |
927 | ||
928 | cd = board_mmc_getcd(mmc); | |
929 | ||
d4e1da4e | 930 | if (cd < 0) { |
93bfd616 PA |
931 | if (mmc->cfg->ops->getcd) |
932 | cd = mmc->cfg->ops->getcd(mmc); | |
d4e1da4e PK |
933 | else |
934 | cd = 1; | |
935 | } | |
48972d90 TR |
936 | |
937 | return cd; | |
938 | } | |
8ca51e51 | 939 | #endif |
48972d90 | 940 | |
fdbb873e | 941 | static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) |
272cc70b AF |
942 | { |
943 | struct mmc_cmd cmd; | |
944 | struct mmc_data data; | |
945 | ||
946 | /* Switch the frequency */ | |
947 | cmd.cmdidx = SD_CMD_SWITCH_FUNC; | |
948 | cmd.resp_type = MMC_RSP_R1; | |
949 | cmd.cmdarg = (mode << 31) | 0xffffff; | |
950 | cmd.cmdarg &= ~(0xf << (group * 4)); | |
951 | cmd.cmdarg |= value << (group * 4); | |
272cc70b AF |
952 | |
953 | data.dest = (char *)resp; | |
954 | data.blocksize = 64; | |
955 | data.blocks = 1; | |
956 | data.flags = MMC_DATA_READ; | |
957 | ||
958 | return mmc_send_cmd(mmc, &cmd, &data); | |
959 | } | |
960 | ||
961 | ||
d0c221fe | 962 | static int sd_get_capabilities(struct mmc *mmc) |
272cc70b AF |
963 | { |
964 | int err; | |
965 | struct mmc_cmd cmd; | |
18e7c8f6 SM |
966 | ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2); |
967 | ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16); | |
272cc70b AF |
968 | struct mmc_data data; |
969 | int timeout; | |
970 | ||
d0c221fe | 971 | mmc->card_caps = MMC_MODE_1BIT; |
272cc70b | 972 | |
d52ebf10 TC |
973 | if (mmc_host_is_spi(mmc)) |
974 | return 0; | |
975 | ||
272cc70b AF |
976 | /* Read the SCR to find out if this card supports higher speeds */ |
977 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
978 | cmd.resp_type = MMC_RSP_R1; | |
979 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
980 | |
981 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
982 | ||
983 | if (err) | |
984 | return err; | |
985 | ||
986 | cmd.cmdidx = SD_CMD_APP_SEND_SCR; | |
987 | cmd.resp_type = MMC_RSP_R1; | |
988 | cmd.cmdarg = 0; | |
272cc70b AF |
989 | |
990 | timeout = 3; | |
991 | ||
992 | retry_scr: | |
f781dd38 | 993 | data.dest = (char *)scr; |
272cc70b AF |
994 | data.blocksize = 8; |
995 | data.blocks = 1; | |
996 | data.flags = MMC_DATA_READ; | |
997 | ||
998 | err = mmc_send_cmd(mmc, &cmd, &data); | |
999 | ||
1000 | if (err) { | |
1001 | if (timeout--) | |
1002 | goto retry_scr; | |
1003 | ||
1004 | return err; | |
1005 | } | |
1006 | ||
4e3d89ba YK |
1007 | mmc->scr[0] = __be32_to_cpu(scr[0]); |
1008 | mmc->scr[1] = __be32_to_cpu(scr[1]); | |
272cc70b AF |
1009 | |
1010 | switch ((mmc->scr[0] >> 24) & 0xf) { | |
53e8e40b BM |
1011 | case 0: |
1012 | mmc->version = SD_VERSION_1_0; | |
1013 | break; | |
1014 | case 1: | |
1015 | mmc->version = SD_VERSION_1_10; | |
1016 | break; | |
1017 | case 2: | |
1018 | mmc->version = SD_VERSION_2; | |
1019 | if ((mmc->scr[0] >> 15) & 0x1) | |
1020 | mmc->version = SD_VERSION_3; | |
1021 | break; | |
1022 | default: | |
1023 | mmc->version = SD_VERSION_1_0; | |
1024 | break; | |
272cc70b AF |
1025 | } |
1026 | ||
b44c7083 AS |
1027 | if (mmc->scr[0] & SD_DATA_4BIT) |
1028 | mmc->card_caps |= MMC_MODE_4BIT; | |
1029 | ||
272cc70b AF |
1030 | /* Version 1.0 doesn't support switching */ |
1031 | if (mmc->version == SD_VERSION_1_0) | |
1032 | return 0; | |
1033 | ||
1034 | timeout = 4; | |
1035 | while (timeout--) { | |
1036 | err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, | |
f781dd38 | 1037 | (u8 *)switch_status); |
272cc70b AF |
1038 | |
1039 | if (err) | |
1040 | return err; | |
1041 | ||
1042 | /* The high-speed function is busy. Try again */ | |
4e3d89ba | 1043 | if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) |
272cc70b AF |
1044 | break; |
1045 | } | |
1046 | ||
272cc70b | 1047 | /* If high-speed isn't supported, we return */ |
d0c221fe JJH |
1048 | if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED) |
1049 | mmc->card_caps |= MMC_CAP(SD_HS); | |
272cc70b | 1050 | |
d0c221fe JJH |
1051 | return 0; |
1052 | } | |
1053 | ||
1054 | static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode) | |
1055 | { | |
1056 | int err; | |
1057 | ||
1058 | ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); | |
2c3fbf4c | 1059 | |
f781dd38 | 1060 | err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); |
d0c221fe JJH |
1061 | if (err) |
1062 | return err; | |
1063 | ||
1064 | if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) != 0x01000000) | |
1065 | return -ENOTSUPP; | |
272cc70b | 1066 | |
d0c221fe JJH |
1067 | return 0; |
1068 | } | |
1069 | ||
1070 | int sd_select_bus_width(struct mmc *mmc, int w) | |
1071 | { | |
1072 | int err; | |
1073 | struct mmc_cmd cmd; | |
1074 | ||
1075 | if ((w != 4) && (w != 1)) | |
1076 | return -EINVAL; | |
1077 | ||
1078 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
1079 | cmd.resp_type = MMC_RSP_R1; | |
1080 | cmd.cmdarg = mmc->rca << 16; | |
1081 | ||
1082 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
272cc70b AF |
1083 | if (err) |
1084 | return err; | |
1085 | ||
d0c221fe JJH |
1086 | cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; |
1087 | cmd.resp_type = MMC_RSP_R1; | |
1088 | if (w == 4) | |
1089 | cmd.cmdarg = 2; | |
1090 | else if (w == 1) | |
1091 | cmd.cmdarg = 0; | |
1092 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1093 | if (err) | |
1094 | return err; | |
272cc70b AF |
1095 | |
1096 | return 0; | |
1097 | } | |
1098 | ||
3697e599 PF |
1099 | static int sd_read_ssr(struct mmc *mmc) |
1100 | { | |
1101 | int err, i; | |
1102 | struct mmc_cmd cmd; | |
1103 | ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16); | |
1104 | struct mmc_data data; | |
1105 | int timeout = 3; | |
1106 | unsigned int au, eo, et, es; | |
1107 | ||
1108 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
1109 | cmd.resp_type = MMC_RSP_R1; | |
1110 | cmd.cmdarg = mmc->rca << 16; | |
1111 | ||
1112 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1113 | if (err) | |
1114 | return err; | |
1115 | ||
1116 | cmd.cmdidx = SD_CMD_APP_SD_STATUS; | |
1117 | cmd.resp_type = MMC_RSP_R1; | |
1118 | cmd.cmdarg = 0; | |
1119 | ||
1120 | retry_ssr: | |
1121 | data.dest = (char *)ssr; | |
1122 | data.blocksize = 64; | |
1123 | data.blocks = 1; | |
1124 | data.flags = MMC_DATA_READ; | |
1125 | ||
1126 | err = mmc_send_cmd(mmc, &cmd, &data); | |
1127 | if (err) { | |
1128 | if (timeout--) | |
1129 | goto retry_ssr; | |
1130 | ||
1131 | return err; | |
1132 | } | |
1133 | ||
1134 | for (i = 0; i < 16; i++) | |
1135 | ssr[i] = be32_to_cpu(ssr[i]); | |
1136 | ||
1137 | au = (ssr[2] >> 12) & 0xF; | |
1138 | if ((au <= 9) || (mmc->version == SD_VERSION_3)) { | |
1139 | mmc->ssr.au = sd_au_size[au]; | |
1140 | es = (ssr[3] >> 24) & 0xFF; | |
1141 | es |= (ssr[2] & 0xFF) << 8; | |
1142 | et = (ssr[3] >> 18) & 0x3F; | |
1143 | if (es && et) { | |
1144 | eo = (ssr[3] >> 16) & 0x3; | |
1145 | mmc->ssr.erase_timeout = (et * 1000) / es; | |
1146 | mmc->ssr.erase_offset = eo * 1000; | |
1147 | } | |
1148 | } else { | |
1149 | debug("Invalid Allocation Unit Size.\n"); | |
1150 | } | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
272cc70b AF |
1155 | /* frequency bases */ |
1156 | /* divided by 10 to be nice to platforms without floating point */ | |
5f837c2c | 1157 | static const int fbase[] = { |
272cc70b AF |
1158 | 10000, |
1159 | 100000, | |
1160 | 1000000, | |
1161 | 10000000, | |
1162 | }; | |
1163 | ||
1164 | /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice | |
1165 | * to platforms without floating point. | |
1166 | */ | |
61fe076f | 1167 | static const u8 multipliers[] = { |
272cc70b AF |
1168 | 0, /* reserved */ |
1169 | 10, | |
1170 | 12, | |
1171 | 13, | |
1172 | 15, | |
1173 | 20, | |
1174 | 25, | |
1175 | 30, | |
1176 | 35, | |
1177 | 40, | |
1178 | 45, | |
1179 | 50, | |
1180 | 55, | |
1181 | 60, | |
1182 | 70, | |
1183 | 80, | |
1184 | }; | |
1185 | ||
d0c221fe JJH |
1186 | static inline int bus_width(uint cap) |
1187 | { | |
1188 | if (cap == MMC_MODE_8BIT) | |
1189 | return 8; | |
1190 | if (cap == MMC_MODE_4BIT) | |
1191 | return 4; | |
1192 | if (cap == MMC_MODE_1BIT) | |
1193 | return 1; | |
1194 | printf("invalid bus witdh capability 0x%x\n", cap); | |
1195 | return 0; | |
1196 | } | |
1197 | ||
e7881d85 | 1198 | #if !CONFIG_IS_ENABLED(DM_MMC) |
2a4d212f | 1199 | static int mmc_set_ios(struct mmc *mmc) |
272cc70b | 1200 | { |
2a4d212f KVA |
1201 | int ret = 0; |
1202 | ||
93bfd616 | 1203 | if (mmc->cfg->ops->set_ios) |
2a4d212f KVA |
1204 | ret = mmc->cfg->ops->set_ios(mmc); |
1205 | ||
1206 | return ret; | |
272cc70b | 1207 | } |
8ca51e51 | 1208 | #endif |
272cc70b | 1209 | |
2a4d212f | 1210 | int mmc_set_clock(struct mmc *mmc, uint clock) |
272cc70b | 1211 | { |
93bfd616 PA |
1212 | if (clock > mmc->cfg->f_max) |
1213 | clock = mmc->cfg->f_max; | |
272cc70b | 1214 | |
93bfd616 PA |
1215 | if (clock < mmc->cfg->f_min) |
1216 | clock = mmc->cfg->f_min; | |
272cc70b AF |
1217 | |
1218 | mmc->clock = clock; | |
1219 | ||
2a4d212f | 1220 | return mmc_set_ios(mmc); |
272cc70b AF |
1221 | } |
1222 | ||
2a4d212f | 1223 | static int mmc_set_bus_width(struct mmc *mmc, uint width) |
272cc70b AF |
1224 | { |
1225 | mmc->bus_width = width; | |
1226 | ||
2a4d212f | 1227 | return mmc_set_ios(mmc); |
272cc70b AF |
1228 | } |
1229 | ||
4c9d2aaa JJH |
1230 | #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) |
1231 | /* | |
1232 | * helper function to display the capabilities in a human | |
1233 | * friendly manner. The capabilities include bus width and | |
1234 | * supported modes. | |
1235 | */ | |
1236 | void mmc_dump_capabilities(const char *text, uint caps) | |
1237 | { | |
1238 | enum bus_mode mode; | |
1239 | ||
1240 | printf("%s: widths [", text); | |
1241 | if (caps & MMC_MODE_8BIT) | |
1242 | printf("8, "); | |
1243 | if (caps & MMC_MODE_4BIT) | |
1244 | printf("4, "); | |
d0c221fe JJH |
1245 | if (caps & MMC_MODE_1BIT) |
1246 | printf("1, "); | |
1247 | printf("\b\b] modes ["); | |
4c9d2aaa JJH |
1248 | for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++) |
1249 | if (MMC_CAP(mode) & caps) | |
1250 | printf("%s, ", mmc_mode_name(mode)); | |
1251 | printf("\b\b]\n"); | |
1252 | } | |
1253 | #endif | |
1254 | ||
d0c221fe JJH |
1255 | struct mode_width_tuning { |
1256 | enum bus_mode mode; | |
1257 | uint widths; | |
1258 | }; | |
1259 | ||
1260 | static const struct mode_width_tuning sd_modes_by_pref[] = { | |
1261 | { | |
1262 | .mode = SD_HS, | |
1263 | .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, | |
1264 | }, | |
1265 | { | |
1266 | .mode = SD_LEGACY, | |
1267 | .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, | |
1268 | } | |
1269 | }; | |
1270 | ||
1271 | #define for_each_sd_mode_by_pref(caps, mwt) \ | |
1272 | for (mwt = sd_modes_by_pref;\ | |
1273 | mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\ | |
1274 | mwt++) \ | |
1275 | if (caps & MMC_CAP(mwt->mode)) | |
1276 | ||
1277 | static int sd_select_mode_and_width(struct mmc *mmc) | |
8ac8a263 JJH |
1278 | { |
1279 | int err; | |
d0c221fe JJH |
1280 | uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT}; |
1281 | const struct mode_width_tuning *mwt; | |
8ac8a263 | 1282 | |
d0c221fe | 1283 | err = sd_get_capabilities(mmc); |
8ac8a263 JJH |
1284 | if (err) |
1285 | return err; | |
8ac8a263 | 1286 | /* Restrict card's capabilities by what the host can do */ |
d0c221fe JJH |
1287 | mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT); |
1288 | ||
1289 | for_each_sd_mode_by_pref(mmc->card_caps, mwt) { | |
1290 | uint *w; | |
1291 | ||
1292 | for (w = widths; w < widths + ARRAY_SIZE(widths); w++) { | |
1293 | if (*w & mmc->card_caps & mwt->widths) { | |
1294 | debug("trying mode %s width %d (at %d MHz)\n", | |
1295 | mmc_mode_name(mwt->mode), | |
1296 | bus_width(*w), | |
1297 | mmc_mode2freq(mmc, mwt->mode) / 1000000); | |
1298 | ||
1299 | /* configure the bus width (card + host) */ | |
1300 | err = sd_select_bus_width(mmc, bus_width(*w)); | |
1301 | if (err) | |
1302 | goto error; | |
1303 | mmc_set_bus_width(mmc, bus_width(*w)); | |
1304 | ||
1305 | /* configure the bus mode (card) */ | |
1306 | err = sd_set_card_speed(mmc, mwt->mode); | |
1307 | if (err) | |
1308 | goto error; | |
1309 | ||
1310 | /* configure the bus mode (host) */ | |
1311 | mmc_select_mode(mmc, mwt->mode); | |
1312 | mmc_set_clock(mmc, mmc->tran_speed); | |
1313 | ||
1314 | err = sd_read_ssr(mmc); | |
1315 | if (!err) | |
1316 | return 0; | |
1317 | ||
1318 | printf("bad ssr\n"); | |
1319 | ||
1320 | error: | |
1321 | /* revert to a safer bus speed */ | |
1322 | mmc_select_mode(mmc, SD_LEGACY); | |
1323 | mmc_set_clock(mmc, mmc->tran_speed); | |
1324 | } | |
1325 | } | |
8ac8a263 JJH |
1326 | } |
1327 | ||
d0c221fe JJH |
1328 | printf("unable to select a mode\n"); |
1329 | return -ENOTSUPP; | |
8ac8a263 JJH |
1330 | } |
1331 | ||
7382e691 JJH |
1332 | /* |
1333 | * read the compare the part of ext csd that is constant. | |
1334 | * This can be used to check that the transfer is working | |
1335 | * as expected. | |
1336 | */ | |
1337 | static int mmc_read_and_compare_ext_csd(struct mmc *mmc) | |
8ac8a263 | 1338 | { |
7382e691 | 1339 | int err; |
dfda9d88 | 1340 | const u8 *ext_csd = mmc->ext_csd; |
7382e691 JJH |
1341 | ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); |
1342 | ||
1343 | err = mmc_send_ext_csd(mmc, test_csd); | |
1344 | if (err) | |
1345 | return err; | |
1346 | ||
1347 | /* Only compare read only fields */ | |
1348 | if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] | |
1349 | == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && | |
1350 | ext_csd[EXT_CSD_HC_WP_GRP_SIZE] | |
1351 | == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && | |
1352 | ext_csd[EXT_CSD_REV] | |
1353 | == test_csd[EXT_CSD_REV] && | |
1354 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1355 | == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && | |
1356 | memcmp(&ext_csd[EXT_CSD_SEC_CNT], | |
1357 | &test_csd[EXT_CSD_SEC_CNT], 4) == 0) | |
1358 | return 0; | |
1359 | ||
1360 | return -EBADMSG; | |
1361 | } | |
1362 | ||
3862b854 JJH |
1363 | static const struct mode_width_tuning mmc_modes_by_pref[] = { |
1364 | { | |
1365 | .mode = MMC_HS_200, | |
1366 | .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, | |
1367 | }, | |
1368 | { | |
1369 | .mode = MMC_DDR_52, | |
1370 | .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, | |
1371 | }, | |
1372 | { | |
1373 | .mode = MMC_HS_52, | |
1374 | .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, | |
1375 | }, | |
1376 | { | |
1377 | .mode = MMC_HS, | |
1378 | .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, | |
1379 | }, | |
1380 | { | |
1381 | .mode = MMC_LEGACY, | |
1382 | .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, | |
1383 | } | |
1384 | }; | |
1385 | ||
1386 | #define for_each_mmc_mode_by_pref(caps, mwt) \ | |
1387 | for (mwt = mmc_modes_by_pref;\ | |
1388 | mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\ | |
1389 | mwt++) \ | |
1390 | if (caps & MMC_CAP(mwt->mode)) | |
1391 | ||
1392 | static const struct ext_csd_bus_width { | |
1393 | uint cap; | |
1394 | bool is_ddr; | |
1395 | uint ext_csd_bits; | |
1396 | } ext_csd_bus_width[] = { | |
1397 | {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8}, | |
1398 | {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4}, | |
1399 | {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8}, | |
1400 | {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4}, | |
1401 | {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1}, | |
1402 | }; | |
1403 | ||
1404 | #define for_each_supported_width(caps, ddr, ecbv) \ | |
1405 | for (ecbv = ext_csd_bus_width;\ | |
1406 | ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\ | |
1407 | ecbv++) \ | |
1408 | if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap)) | |
1409 | ||
1410 | static int mmc_select_mode_and_width(struct mmc *mmc) | |
7382e691 | 1411 | { |
8ac8a263 | 1412 | int err; |
3862b854 JJH |
1413 | const struct mode_width_tuning *mwt; |
1414 | const struct ext_csd_bus_width *ecbw; | |
8ac8a263 | 1415 | |
3862b854 | 1416 | err = mmc_get_capabilities(mmc); |
8ac8a263 JJH |
1417 | if (err) |
1418 | return err; | |
1419 | ||
1420 | /* Restrict card's capabilities by what the host can do */ | |
d0c221fe | 1421 | mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT); |
8ac8a263 JJH |
1422 | |
1423 | /* Only version 4 of MMC supports wider bus widths */ | |
1424 | if (mmc->version < MMC_VERSION_4) | |
1425 | return 0; | |
1426 | ||
dfda9d88 JJH |
1427 | if (!mmc->ext_csd) { |
1428 | debug("No ext_csd found!\n"); /* this should enver happen */ | |
1429 | return -ENOTSUPP; | |
1430 | } | |
1431 | ||
3862b854 JJH |
1432 | for_each_mmc_mode_by_pref(mmc->card_caps, mwt) { |
1433 | for_each_supported_width(mmc->card_caps & mwt->widths, | |
1434 | mmc_is_mode_ddr(mwt->mode), ecbw) { | |
1435 | debug("trying mode %s width %d (at %d MHz)\n", | |
1436 | mmc_mode_name(mwt->mode), | |
1437 | bus_width(ecbw->cap), | |
1438 | mmc_mode2freq(mmc, mwt->mode) / 1000000); | |
1439 | /* configure the bus width (card + host) */ | |
1440 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
1441 | EXT_CSD_BUS_WIDTH, | |
1442 | ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG); | |
1443 | if (err) | |
1444 | goto error; | |
1445 | mmc_set_bus_width(mmc, bus_width(ecbw->cap)); | |
8ac8a263 | 1446 | |
3862b854 JJH |
1447 | /* configure the bus speed (card) */ |
1448 | err = mmc_set_card_speed(mmc, mwt->mode); | |
1449 | if (err) | |
1450 | goto error; | |
1451 | ||
1452 | /* | |
1453 | * configure the bus width AND the ddr mode (card) | |
1454 | * The host side will be taken care of in the next step | |
1455 | */ | |
1456 | if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { | |
1457 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
1458 | EXT_CSD_BUS_WIDTH, | |
1459 | ecbw->ext_csd_bits); | |
1460 | if (err) | |
1461 | goto error; | |
1462 | } | |
8ac8a263 | 1463 | |
3862b854 JJH |
1464 | /* configure the bus mode (host) */ |
1465 | mmc_select_mode(mmc, mwt->mode); | |
1466 | mmc_set_clock(mmc, mmc->tran_speed); | |
8ac8a263 | 1467 | |
3862b854 JJH |
1468 | /* do a transfer to check the configuration */ |
1469 | err = mmc_read_and_compare_ext_csd(mmc); | |
1470 | if (!err) | |
1471 | return 0; | |
1472 | error: | |
1473 | /* if an error occured, revert to a safer bus mode */ | |
1474 | mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
1475 | EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1); | |
1476 | mmc_select_mode(mmc, MMC_LEGACY); | |
1477 | mmc_set_bus_width(mmc, 1); | |
1478 | } | |
8ac8a263 JJH |
1479 | } |
1480 | ||
3862b854 | 1481 | printf("unable to select a mode\n"); |
8ac8a263 | 1482 | |
3862b854 | 1483 | return -ENOTSUPP; |
8ac8a263 JJH |
1484 | } |
1485 | ||
dfda9d88 | 1486 | static int mmc_startup_v4(struct mmc *mmc) |
c744b6f6 JJH |
1487 | { |
1488 | int err, i; | |
1489 | u64 capacity; | |
1490 | bool has_parts = false; | |
1491 | bool part_completed; | |
dfda9d88 | 1492 | u8 *ext_csd; |
c744b6f6 JJH |
1493 | |
1494 | if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4)) | |
1495 | return 0; | |
1496 | ||
dfda9d88 JJH |
1497 | ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN); |
1498 | if (!ext_csd) | |
1499 | return -ENOMEM; | |
1500 | ||
1501 | mmc->ext_csd = ext_csd; | |
1502 | ||
c744b6f6 JJH |
1503 | /* check ext_csd version and capacity */ |
1504 | err = mmc_send_ext_csd(mmc, ext_csd); | |
1505 | if (err) | |
1506 | return err; | |
1507 | if (ext_csd[EXT_CSD_REV] >= 2) { | |
1508 | /* | |
1509 | * According to the JEDEC Standard, the value of | |
1510 | * ext_csd's capacity is valid if the value is more | |
1511 | * than 2GB | |
1512 | */ | |
1513 | capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 | |
1514 | | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | |
1515 | | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | |
1516 | | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; | |
1517 | capacity *= MMC_MAX_BLOCK_LEN; | |
1518 | if ((capacity >> 20) > 2 * 1024) | |
1519 | mmc->capacity_user = capacity; | |
1520 | } | |
1521 | ||
1522 | switch (ext_csd[EXT_CSD_REV]) { | |
1523 | case 1: | |
1524 | mmc->version = MMC_VERSION_4_1; | |
1525 | break; | |
1526 | case 2: | |
1527 | mmc->version = MMC_VERSION_4_2; | |
1528 | break; | |
1529 | case 3: | |
1530 | mmc->version = MMC_VERSION_4_3; | |
1531 | break; | |
1532 | case 5: | |
1533 | mmc->version = MMC_VERSION_4_41; | |
1534 | break; | |
1535 | case 6: | |
1536 | mmc->version = MMC_VERSION_4_5; | |
1537 | break; | |
1538 | case 7: | |
1539 | mmc->version = MMC_VERSION_5_0; | |
1540 | break; | |
1541 | case 8: | |
1542 | mmc->version = MMC_VERSION_5_1; | |
1543 | break; | |
1544 | } | |
1545 | ||
1546 | /* The partition data may be non-zero but it is only | |
1547 | * effective if PARTITION_SETTING_COMPLETED is set in | |
1548 | * EXT_CSD, so ignore any data if this bit is not set, | |
1549 | * except for enabling the high-capacity group size | |
1550 | * definition (see below). | |
1551 | */ | |
1552 | part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & | |
1553 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
1554 | ||
1555 | /* store the partition info of emmc */ | |
1556 | mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; | |
1557 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || | |
1558 | ext_csd[EXT_CSD_BOOT_MULT]) | |
1559 | mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; | |
1560 | if (part_completed && | |
1561 | (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) | |
1562 | mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; | |
1563 | ||
1564 | mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; | |
1565 | ||
1566 | mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; | |
1567 | ||
1568 | for (i = 0; i < 4; i++) { | |
1569 | int idx = EXT_CSD_GP_SIZE_MULT + i * 3; | |
1570 | uint mult = (ext_csd[idx + 2] << 16) + | |
1571 | (ext_csd[idx + 1] << 8) + ext_csd[idx]; | |
1572 | if (mult) | |
1573 | has_parts = true; | |
1574 | if (!part_completed) | |
1575 | continue; | |
1576 | mmc->capacity_gp[i] = mult; | |
1577 | mmc->capacity_gp[i] *= | |
1578 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1579 | mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
1580 | mmc->capacity_gp[i] <<= 19; | |
1581 | } | |
1582 | ||
1583 | if (part_completed) { | |
1584 | mmc->enh_user_size = | |
1585 | (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) + | |
1586 | (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) + | |
1587 | ext_csd[EXT_CSD_ENH_SIZE_MULT]; | |
1588 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1589 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
1590 | mmc->enh_user_size <<= 19; | |
1591 | mmc->enh_user_start = | |
1592 | (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) + | |
1593 | (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) + | |
1594 | (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) + | |
1595 | ext_csd[EXT_CSD_ENH_START_ADDR]; | |
1596 | if (mmc->high_capacity) | |
1597 | mmc->enh_user_start <<= 9; | |
1598 | } | |
1599 | ||
1600 | /* | |
1601 | * Host needs to enable ERASE_GRP_DEF bit if device is | |
1602 | * partitioned. This bit will be lost every time after a reset | |
1603 | * or power off. This will affect erase size. | |
1604 | */ | |
1605 | if (part_completed) | |
1606 | has_parts = true; | |
1607 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && | |
1608 | (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) | |
1609 | has_parts = true; | |
1610 | if (has_parts) { | |
1611 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
1612 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
1613 | ||
1614 | if (err) | |
1615 | return err; | |
1616 | ||
1617 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
1618 | } | |
1619 | ||
1620 | if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { | |
1621 | /* Read out group size from ext_csd */ | |
1622 | mmc->erase_grp_size = | |
1623 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; | |
1624 | /* | |
1625 | * if high capacity and partition setting completed | |
1626 | * SEC_COUNT is valid even if it is smaller than 2 GiB | |
1627 | * JEDEC Standard JESD84-B45, 6.2.4 | |
1628 | */ | |
1629 | if (mmc->high_capacity && part_completed) { | |
1630 | capacity = (ext_csd[EXT_CSD_SEC_CNT]) | | |
1631 | (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | | |
1632 | (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | | |
1633 | (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); | |
1634 | capacity *= MMC_MAX_BLOCK_LEN; | |
1635 | mmc->capacity_user = capacity; | |
1636 | } | |
1637 | } else { | |
1638 | /* Calculate the group size from the csd value. */ | |
1639 | int erase_gsz, erase_gmul; | |
1640 | ||
1641 | erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; | |
1642 | erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; | |
1643 | mmc->erase_grp_size = (erase_gsz + 1) | |
1644 | * (erase_gmul + 1); | |
1645 | } | |
1646 | ||
1647 | mmc->hc_wp_grp_size = 1024 | |
1648 | * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1649 | * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
1650 | ||
1651 | mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
fdbb873e | 1656 | static int mmc_startup(struct mmc *mmc) |
272cc70b | 1657 | { |
f866a46d | 1658 | int err, i; |
272cc70b | 1659 | uint mult, freq; |
c744b6f6 | 1660 | u64 cmult, csize; |
272cc70b | 1661 | struct mmc_cmd cmd; |
c40fdca6 | 1662 | struct blk_desc *bdesc; |
272cc70b | 1663 | |
d52ebf10 TC |
1664 | #ifdef CONFIG_MMC_SPI_CRC_ON |
1665 | if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ | |
1666 | cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; | |
1667 | cmd.resp_type = MMC_RSP_R1; | |
1668 | cmd.cmdarg = 1; | |
d52ebf10 TC |
1669 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1670 | ||
1671 | if (err) | |
1672 | return err; | |
1673 | } | |
1674 | #endif | |
1675 | ||
272cc70b | 1676 | /* Put the Card in Identify Mode */ |
d52ebf10 TC |
1677 | cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : |
1678 | MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ | |
272cc70b AF |
1679 | cmd.resp_type = MMC_RSP_R2; |
1680 | cmd.cmdarg = 0; | |
272cc70b AF |
1681 | |
1682 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1683 | ||
1684 | if (err) | |
1685 | return err; | |
1686 | ||
1687 | memcpy(mmc->cid, cmd.response, 16); | |
1688 | ||
1689 | /* | |
1690 | * For MMC cards, set the Relative Address. | |
1691 | * For SD cards, get the Relatvie Address. | |
1692 | * This also puts the cards into Standby State | |
1693 | */ | |
d52ebf10 TC |
1694 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1695 | cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; | |
1696 | cmd.cmdarg = mmc->rca << 16; | |
1697 | cmd.resp_type = MMC_RSP_R6; | |
272cc70b | 1698 | |
d52ebf10 | 1699 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1700 | |
d52ebf10 TC |
1701 | if (err) |
1702 | return err; | |
272cc70b | 1703 | |
d52ebf10 TC |
1704 | if (IS_SD(mmc)) |
1705 | mmc->rca = (cmd.response[0] >> 16) & 0xffff; | |
1706 | } | |
272cc70b AF |
1707 | |
1708 | /* Get the Card-Specific Data */ | |
1709 | cmd.cmdidx = MMC_CMD_SEND_CSD; | |
1710 | cmd.resp_type = MMC_RSP_R2; | |
1711 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1712 | |
1713 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1714 | ||
1715 | if (err) | |
1716 | return err; | |
1717 | ||
998be3dd RV |
1718 | mmc->csd[0] = cmd.response[0]; |
1719 | mmc->csd[1] = cmd.response[1]; | |
1720 | mmc->csd[2] = cmd.response[2]; | |
1721 | mmc->csd[3] = cmd.response[3]; | |
272cc70b AF |
1722 | |
1723 | if (mmc->version == MMC_VERSION_UNKNOWN) { | |
0b453ffe | 1724 | int version = (cmd.response[0] >> 26) & 0xf; |
272cc70b AF |
1725 | |
1726 | switch (version) { | |
53e8e40b BM |
1727 | case 0: |
1728 | mmc->version = MMC_VERSION_1_2; | |
1729 | break; | |
1730 | case 1: | |
1731 | mmc->version = MMC_VERSION_1_4; | |
1732 | break; | |
1733 | case 2: | |
1734 | mmc->version = MMC_VERSION_2_2; | |
1735 | break; | |
1736 | case 3: | |
1737 | mmc->version = MMC_VERSION_3; | |
1738 | break; | |
1739 | case 4: | |
1740 | mmc->version = MMC_VERSION_4; | |
1741 | break; | |
1742 | default: | |
1743 | mmc->version = MMC_VERSION_1_2; | |
1744 | break; | |
272cc70b AF |
1745 | } |
1746 | } | |
1747 | ||
1748 | /* divide frequency by 10, since the mults are 10x bigger */ | |
0b453ffe RV |
1749 | freq = fbase[(cmd.response[0] & 0x7)]; |
1750 | mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; | |
272cc70b | 1751 | |
35f9e196 | 1752 | mmc->legacy_speed = freq * mult; |
35f9e196 | 1753 | mmc_select_mode(mmc, MMC_LEGACY); |
272cc70b | 1754 | |
ab71188c | 1755 | mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); |
998be3dd | 1756 | mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); |
272cc70b AF |
1757 | |
1758 | if (IS_SD(mmc)) | |
1759 | mmc->write_bl_len = mmc->read_bl_len; | |
1760 | else | |
998be3dd | 1761 | mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); |
272cc70b AF |
1762 | |
1763 | if (mmc->high_capacity) { | |
1764 | csize = (mmc->csd[1] & 0x3f) << 16 | |
1765 | | (mmc->csd[2] & 0xffff0000) >> 16; | |
1766 | cmult = 8; | |
1767 | } else { | |
1768 | csize = (mmc->csd[1] & 0x3ff) << 2 | |
1769 | | (mmc->csd[2] & 0xc0000000) >> 30; | |
1770 | cmult = (mmc->csd[2] & 0x00038000) >> 15; | |
1771 | } | |
1772 | ||
f866a46d SW |
1773 | mmc->capacity_user = (csize + 1) << (cmult + 2); |
1774 | mmc->capacity_user *= mmc->read_bl_len; | |
1775 | mmc->capacity_boot = 0; | |
1776 | mmc->capacity_rpmb = 0; | |
1777 | for (i = 0; i < 4; i++) | |
1778 | mmc->capacity_gp[i] = 0; | |
272cc70b | 1779 | |
8bfa195e SG |
1780 | if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) |
1781 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1782 | |
8bfa195e SG |
1783 | if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) |
1784 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1785 | |
ab71188c MN |
1786 | if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { |
1787 | cmd.cmdidx = MMC_CMD_SET_DSR; | |
1788 | cmd.cmdarg = (mmc->dsr & 0xffff) << 16; | |
1789 | cmd.resp_type = MMC_RSP_NONE; | |
1790 | if (mmc_send_cmd(mmc, &cmd, NULL)) | |
1791 | printf("MMC: SET_DSR failed\n"); | |
1792 | } | |
1793 | ||
272cc70b | 1794 | /* Select the card, and put it into Transfer Mode */ |
d52ebf10 TC |
1795 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1796 | cmd.cmdidx = MMC_CMD_SELECT_CARD; | |
fe8f7066 | 1797 | cmd.resp_type = MMC_RSP_R1; |
d52ebf10 | 1798 | cmd.cmdarg = mmc->rca << 16; |
d52ebf10 | 1799 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1800 | |
d52ebf10 TC |
1801 | if (err) |
1802 | return err; | |
1803 | } | |
272cc70b | 1804 | |
e6f99a56 LW |
1805 | /* |
1806 | * For SD, its erase group is always one sector | |
1807 | */ | |
1808 | mmc->erase_grp_size = 1; | |
bc897b1d | 1809 | mmc->part_config = MMCPART_NOAVAILABLE; |
1937e5aa | 1810 | |
dfda9d88 | 1811 | err = mmc_startup_v4(mmc); |
c744b6f6 JJH |
1812 | if (err) |
1813 | return err; | |
d23e2c09 | 1814 | |
c40fdca6 | 1815 | err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); |
f866a46d SW |
1816 | if (err) |
1817 | return err; | |
1818 | ||
272cc70b | 1819 | if (IS_SD(mmc)) |
d0c221fe | 1820 | err = sd_select_mode_and_width(mmc); |
272cc70b | 1821 | else |
3862b854 | 1822 | err = mmc_select_mode_and_width(mmc); |
272cc70b AF |
1823 | |
1824 | if (err) | |
1825 | return err; | |
1826 | ||
ad5fd922 | 1827 | |
5af8f45c AG |
1828 | /* Fix the block length for DDR mode */ |
1829 | if (mmc->ddr_mode) { | |
1830 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
1831 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
1832 | } | |
1833 | ||
272cc70b | 1834 | /* fill in device description */ |
c40fdca6 SG |
1835 | bdesc = mmc_get_blk_desc(mmc); |
1836 | bdesc->lun = 0; | |
1837 | bdesc->hwpart = 0; | |
1838 | bdesc->type = 0; | |
1839 | bdesc->blksz = mmc->read_bl_len; | |
1840 | bdesc->log2blksz = LOG2(bdesc->blksz); | |
1841 | bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); | |
fc011f64 SS |
1842 | #if !defined(CONFIG_SPL_BUILD) || \ |
1843 | (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ | |
1844 | !defined(CONFIG_USE_TINY_PRINTF)) | |
c40fdca6 | 1845 | sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", |
babce5f6 TH |
1846 | mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), |
1847 | (mmc->cid[3] >> 16) & 0xffff); | |
c40fdca6 | 1848 | sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, |
babce5f6 TH |
1849 | (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, |
1850 | (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, | |
1851 | (mmc->cid[2] >> 24) & 0xff); | |
c40fdca6 | 1852 | sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, |
babce5f6 | 1853 | (mmc->cid[2] >> 16) & 0xf); |
56196826 | 1854 | #else |
c40fdca6 SG |
1855 | bdesc->vendor[0] = 0; |
1856 | bdesc->product[0] = 0; | |
1857 | bdesc->revision[0] = 0; | |
56196826 | 1858 | #endif |
122efd43 | 1859 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) |
c40fdca6 | 1860 | part_init(bdesc); |
122efd43 | 1861 | #endif |
272cc70b AF |
1862 | |
1863 | return 0; | |
1864 | } | |
1865 | ||
fdbb873e | 1866 | static int mmc_send_if_cond(struct mmc *mmc) |
272cc70b AF |
1867 | { |
1868 | struct mmc_cmd cmd; | |
1869 | int err; | |
1870 | ||
1871 | cmd.cmdidx = SD_CMD_SEND_IF_COND; | |
1872 | /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ | |
93bfd616 | 1873 | cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; |
272cc70b | 1874 | cmd.resp_type = MMC_RSP_R7; |
272cc70b AF |
1875 | |
1876 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1877 | ||
1878 | if (err) | |
1879 | return err; | |
1880 | ||
998be3dd | 1881 | if ((cmd.response[0] & 0xff) != 0xaa) |
915ffa52 | 1882 | return -EOPNOTSUPP; |
272cc70b AF |
1883 | else |
1884 | mmc->version = SD_VERSION_2; | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
c4d660d4 | 1889 | #if !CONFIG_IS_ENABLED(DM_MMC) |
95de9ab2 PK |
1890 | /* board-specific MMC power initializations. */ |
1891 | __weak void board_mmc_power_init(void) | |
1892 | { | |
1893 | } | |
05cbeb7c | 1894 | #endif |
95de9ab2 | 1895 | |
2051aefe PF |
1896 | static int mmc_power_init(struct mmc *mmc) |
1897 | { | |
c4d660d4 | 1898 | #if CONFIG_IS_ENABLED(DM_MMC) |
06ec045f | 1899 | #if CONFIG_IS_ENABLED(DM_REGULATOR) |
2051aefe PF |
1900 | int ret; |
1901 | ||
1902 | ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", | |
06ec045f JJH |
1903 | &mmc->vmmc_supply); |
1904 | if (ret) | |
288db7c7 | 1905 | debug("%s: No vmmc supply\n", mmc->dev->name); |
2051aefe | 1906 | |
06ec045f JJH |
1907 | ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply", |
1908 | &mmc->vqmmc_supply); | |
1909 | if (ret) | |
1910 | debug("%s: No vqmmc supply\n", mmc->dev->name); | |
1911 | ||
1912 | if (mmc->vmmc_supply) { | |
1913 | ret = regulator_set_enable(mmc->vmmc_supply, true); | |
1914 | if (ret) { | |
1915 | puts("Error enabling VMMC supply\n"); | |
1916 | return ret; | |
1917 | } | |
2051aefe | 1918 | } |
05cbeb7c SG |
1919 | #endif |
1920 | #else /* !CONFIG_DM_MMC */ | |
1921 | /* | |
1922 | * Driver model should use a regulator, as above, rather than calling | |
1923 | * out to board code. | |
1924 | */ | |
1925 | board_mmc_power_init(); | |
2051aefe PF |
1926 | #endif |
1927 | return 0; | |
1928 | } | |
1929 | ||
e9550449 | 1930 | int mmc_start_init(struct mmc *mmc) |
272cc70b | 1931 | { |
8ca51e51 | 1932 | bool no_card; |
afd5932b | 1933 | int err; |
272cc70b | 1934 | |
ab769f22 | 1935 | /* we pretend there's no card when init is NULL */ |
8ca51e51 | 1936 | no_card = mmc_getcd(mmc) == 0; |
e7881d85 | 1937 | #if !CONFIG_IS_ENABLED(DM_MMC) |
8ca51e51 SG |
1938 | no_card = no_card || (mmc->cfg->ops->init == NULL); |
1939 | #endif | |
1940 | if (no_card) { | |
48972d90 | 1941 | mmc->has_init = 0; |
56196826 | 1942 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
48972d90 | 1943 | printf("MMC: no card present\n"); |
56196826 | 1944 | #endif |
915ffa52 | 1945 | return -ENOMEDIUM; |
48972d90 TR |
1946 | } |
1947 | ||
bc897b1d LW |
1948 | if (mmc->has_init) |
1949 | return 0; | |
1950 | ||
5a8dbdc6 YL |
1951 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
1952 | mmc_adapter_card_type_ident(); | |
1953 | #endif | |
2051aefe PF |
1954 | err = mmc_power_init(mmc); |
1955 | if (err) | |
1956 | return err; | |
95de9ab2 | 1957 | |
e7881d85 | 1958 | #if CONFIG_IS_ENABLED(DM_MMC) |
8ca51e51 SG |
1959 | /* The device has already been probed ready for use */ |
1960 | #else | |
ab769f22 | 1961 | /* made sure it's not NULL earlier */ |
93bfd616 | 1962 | err = mmc->cfg->ops->init(mmc); |
272cc70b AF |
1963 | if (err) |
1964 | return err; | |
8ca51e51 | 1965 | #endif |
786e8f81 | 1966 | mmc->ddr_mode = 0; |
b86b85e2 IY |
1967 | mmc_set_bus_width(mmc, 1); |
1968 | mmc_set_clock(mmc, 1); | |
1969 | ||
272cc70b AF |
1970 | /* Reset the Card */ |
1971 | err = mmc_go_idle(mmc); | |
1972 | ||
1973 | if (err) | |
1974 | return err; | |
1975 | ||
bc897b1d | 1976 | /* The internal partition reset to user partition(0) at every CMD0*/ |
c40fdca6 | 1977 | mmc_get_blk_desc(mmc)->hwpart = 0; |
bc897b1d | 1978 | |
272cc70b | 1979 | /* Test for SD version 2 */ |
afd5932b | 1980 | err = mmc_send_if_cond(mmc); |
272cc70b | 1981 | |
272cc70b AF |
1982 | /* Now try to get the SD card's operating condition */ |
1983 | err = sd_send_op_cond(mmc); | |
1984 | ||
1985 | /* If the command timed out, we check for an MMC card */ | |
915ffa52 | 1986 | if (err == -ETIMEDOUT) { |
272cc70b AF |
1987 | err = mmc_send_op_cond(mmc); |
1988 | ||
bd47c135 | 1989 | if (err) { |
56196826 | 1990 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 1991 | printf("Card did not respond to voltage select!\n"); |
56196826 | 1992 | #endif |
915ffa52 | 1993 | return -EOPNOTSUPP; |
272cc70b AF |
1994 | } |
1995 | } | |
1996 | ||
bd47c135 | 1997 | if (!err) |
e9550449 CLC |
1998 | mmc->init_in_progress = 1; |
1999 | ||
2000 | return err; | |
2001 | } | |
2002 | ||
2003 | static int mmc_complete_init(struct mmc *mmc) | |
2004 | { | |
2005 | int err = 0; | |
2006 | ||
bd47c135 | 2007 | mmc->init_in_progress = 0; |
e9550449 CLC |
2008 | if (mmc->op_cond_pending) |
2009 | err = mmc_complete_op_cond(mmc); | |
2010 | ||
2011 | if (!err) | |
2012 | err = mmc_startup(mmc); | |
bc897b1d LW |
2013 | if (err) |
2014 | mmc->has_init = 0; | |
2015 | else | |
2016 | mmc->has_init = 1; | |
e9550449 CLC |
2017 | return err; |
2018 | } | |
2019 | ||
2020 | int mmc_init(struct mmc *mmc) | |
2021 | { | |
bd47c135 | 2022 | int err = 0; |
ce9eca94 | 2023 | __maybe_unused unsigned start; |
c4d660d4 | 2024 | #if CONFIG_IS_ENABLED(DM_MMC) |
33fb211d | 2025 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); |
e9550449 | 2026 | |
33fb211d SG |
2027 | upriv->mmc = mmc; |
2028 | #endif | |
e9550449 CLC |
2029 | if (mmc->has_init) |
2030 | return 0; | |
d803fea5 MZ |
2031 | |
2032 | start = get_timer(0); | |
2033 | ||
e9550449 CLC |
2034 | if (!mmc->init_in_progress) |
2035 | err = mmc_start_init(mmc); | |
2036 | ||
bd47c135 | 2037 | if (!err) |
e9550449 | 2038 | err = mmc_complete_init(mmc); |
919b4858 JT |
2039 | if (err) |
2040 | printf("%s: %d, time %lu\n", __func__, err, get_timer(start)); | |
2041 | ||
bc897b1d | 2042 | return err; |
272cc70b AF |
2043 | } |
2044 | ||
ab71188c MN |
2045 | int mmc_set_dsr(struct mmc *mmc, u16 val) |
2046 | { | |
2047 | mmc->dsr = val; | |
2048 | return 0; | |
2049 | } | |
2050 | ||
cee9ab7c JH |
2051 | /* CPU-specific MMC initializations */ |
2052 | __weak int cpu_mmc_init(bd_t *bis) | |
272cc70b AF |
2053 | { |
2054 | return -1; | |
2055 | } | |
2056 | ||
cee9ab7c JH |
2057 | /* board-specific MMC initializations. */ |
2058 | __weak int board_mmc_init(bd_t *bis) | |
2059 | { | |
2060 | return -1; | |
2061 | } | |
272cc70b | 2062 | |
e9550449 CLC |
2063 | void mmc_set_preinit(struct mmc *mmc, int preinit) |
2064 | { | |
2065 | mmc->preinit = preinit; | |
2066 | } | |
2067 | ||
c4d660d4 | 2068 | #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD) |
8e3332e2 SS |
2069 | static int mmc_probe(bd_t *bis) |
2070 | { | |
2071 | return 0; | |
2072 | } | |
c4d660d4 | 2073 | #elif CONFIG_IS_ENABLED(DM_MMC) |
8e3332e2 SS |
2074 | static int mmc_probe(bd_t *bis) |
2075 | { | |
4a1db6d8 | 2076 | int ret, i; |
8e3332e2 | 2077 | struct uclass *uc; |
4a1db6d8 | 2078 | struct udevice *dev; |
8e3332e2 SS |
2079 | |
2080 | ret = uclass_get(UCLASS_MMC, &uc); | |
2081 | if (ret) | |
2082 | return ret; | |
2083 | ||
4a1db6d8 SG |
2084 | /* |
2085 | * Try to add them in sequence order. Really with driver model we | |
2086 | * should allow holes, but the current MMC list does not allow that. | |
2087 | * So if we request 0, 1, 3 we will get 0, 1, 2. | |
2088 | */ | |
2089 | for (i = 0; ; i++) { | |
2090 | ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); | |
2091 | if (ret == -ENODEV) | |
2092 | break; | |
2093 | } | |
2094 | uclass_foreach_dev(dev, uc) { | |
2095 | ret = device_probe(dev); | |
8e3332e2 | 2096 | if (ret) |
4a1db6d8 | 2097 | printf("%s - probe failed: %d\n", dev->name, ret); |
8e3332e2 SS |
2098 | } |
2099 | ||
2100 | return 0; | |
2101 | } | |
2102 | #else | |
2103 | static int mmc_probe(bd_t *bis) | |
2104 | { | |
2105 | if (board_mmc_init(bis) < 0) | |
2106 | cpu_mmc_init(bis); | |
2107 | ||
2108 | return 0; | |
2109 | } | |
2110 | #endif | |
e9550449 | 2111 | |
272cc70b AF |
2112 | int mmc_initialize(bd_t *bis) |
2113 | { | |
1b26bab1 | 2114 | static int initialized = 0; |
8e3332e2 | 2115 | int ret; |
1b26bab1 DK |
2116 | if (initialized) /* Avoid initializing mmc multiple times */ |
2117 | return 0; | |
2118 | initialized = 1; | |
2119 | ||
c4d660d4 | 2120 | #if !CONFIG_IS_ENABLED(BLK) |
b5b838f1 | 2121 | #if !CONFIG_IS_ENABLED(MMC_TINY) |
c40fdca6 | 2122 | mmc_list_init(); |
b5b838f1 | 2123 | #endif |
c40fdca6 | 2124 | #endif |
8e3332e2 SS |
2125 | ret = mmc_probe(bis); |
2126 | if (ret) | |
2127 | return ret; | |
272cc70b | 2128 | |
bb0dc108 | 2129 | #ifndef CONFIG_SPL_BUILD |
272cc70b | 2130 | print_mmc_devices(','); |
bb0dc108 | 2131 | #endif |
272cc70b | 2132 | |
c40fdca6 | 2133 | mmc_do_preinit(); |
272cc70b AF |
2134 | return 0; |
2135 | } | |
cd3d4880 TM |
2136 | |
2137 | #ifdef CONFIG_CMD_BKOPS_ENABLE | |
2138 | int mmc_set_bkops_enable(struct mmc *mmc) | |
2139 | { | |
2140 | int err; | |
2141 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); | |
2142 | ||
2143 | err = mmc_send_ext_csd(mmc, ext_csd); | |
2144 | if (err) { | |
2145 | puts("Could not get ext_csd register values\n"); | |
2146 | return err; | |
2147 | } | |
2148 | ||
2149 | if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) { | |
2150 | puts("Background operations not supported on device\n"); | |
2151 | return -EMEDIUMTYPE; | |
2152 | } | |
2153 | ||
2154 | if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { | |
2155 | puts("Background operations already enabled\n"); | |
2156 | return 0; | |
2157 | } | |
2158 | ||
2159 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); | |
2160 | if (err) { | |
2161 | puts("Failed to enable manual background operations\n"); | |
2162 | return err; | |
2163 | } | |
2164 | ||
2165 | puts("Enabled manual background operations\n"); | |
2166 | ||
2167 | return 0; | |
2168 | } | |
2169 | #endif |