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mmc: Retry some MMC cmds on failure
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
2051aefe 18#include <power/regulator.h>
272cc70b 19#include <malloc.h>
cf92e05c 20#include <memalign.h>
272cc70b 21#include <linux/list.h>
9b1f942c 22#include <div64.h>
da61fa5f 23#include "mmc_private.h"
272cc70b 24
3697e599
PF		 25static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31};
32
aff5d3c8 33static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
fb7c3beb 34static int mmc_power_cycle(struct mmc *mmc);
01298da3 35static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
aff5d3c8 36
b5b838f1
MV		 37#if CONFIG_IS_ENABLED(MMC_TINY)
38static struct mmc mmc_static;
39struct mmc *find_mmc_device(int dev_num)
40{
41 return &mmc_static;
42}
43
44void mmc_do_preinit(void)
45{
46 struct mmc *m = &mmc_static;
47#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
48 mmc_set_preinit(m, 1);
49#endif
50 if (m->preinit)
51 mmc_start_init(m);
52}
53
54struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
55{
56 return &mmc->block_dev;
57}
58#endif
59
e7881d85 60#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6
JJH		 61
62static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
63{
64 return -ENOSYS;
65}
66
750121c3 67__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 68{
69 return -1;
70}
71
72int mmc_getwp(struct mmc *mmc)
73{
74 int wp;
75
76 wp = board_mmc_getwp(mmc);
77
d4e1da4e 78 if (wp < 0) {
93bfd616
PA		 79 if (mmc->cfg->ops->getwp)
80 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 81 else
82 wp = 0;
83 }
d23d8d7e
NK		 84
85 return wp;
86}
87
cee9ab7c
JH		 88__weak int board_mmc_getcd(struct mmc *mmc)
89{
11fdade2
SB		 90 return -1;
91}
8ca51e51 92#endif
11fdade2 93
c0c76eba
SG		 94#ifdef CONFIG_MMC_TRACE
95void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 96{
c0c76eba
SG		 97 printf("CMD_SEND:%d\n", cmd->cmdidx);
98 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
99}
8635ff9e 100
c0c76eba
SG		 101void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
102{
5db2fe3a
RR		 103 int i;
104 u8 *ptr;
105
7863ce58
BM		 106 if (ret) {
107 printf("\t\tRET\t\t\t %d\n", ret);
108 } else {
109 switch (cmd->resp_type) {
110 case MMC_RSP_NONE:
111 printf("\t\tMMC_RSP_NONE\n");
112 break;
113 case MMC_RSP_R1:
114 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
115 cmd->response[0]);
116 break;
117 case MMC_RSP_R1b:
118 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
119 cmd->response[0]);
120 break;
121 case MMC_RSP_R2:
122 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
123 cmd->response[0]);
124 printf("\t\t \t\t 0x%08X \n",
125 cmd->response[1]);
126 printf("\t\t \t\t 0x%08X \n",
127 cmd->response[2]);
128 printf("\t\t \t\t 0x%08X \n",
129 cmd->response[3]);
5db2fe3a 130 printf("\n");
7863ce58
BM		 131 printf("\t\t\t\t\tDUMPING DATA\n");
132 for (i = 0; i < 4; i++) {
133 int j;
134 printf("\t\t\t\t\t%03d - ", i*4);
135 ptr = (u8 *)&cmd->response[i];
136 ptr += 3;
137 for (j = 0; j < 4; j++)
138 printf("%02X ", *ptr--);
139 printf("\n");
140 }
141 break;
142 case MMC_RSP_R3:
143 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
144 cmd->response[0]);
145 break;
146 default:
147 printf("\t\tERROR MMC rsp not supported\n");
148 break;
53e8e40b 149 }
5db2fe3a 150 }
c0c76eba
SG		 151}
152
153void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
154{
155 int status;
156
157 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
158 printf("CURR STATE:%d\n", status);
159}
5db2fe3a 160#endif
c0c76eba 161
35f9e196
JJH		 162#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
163const char *mmc_mode_name(enum bus_mode mode)
164{
165 static const char *const names[] = {
166 [MMC_LEGACY] = "MMC legacy",
167 [SD_LEGACY] = "SD Legacy",
168 [MMC_HS] = "MMC High Speed (26MHz)",
169 [SD_HS] = "SD High Speed (50MHz)",
170 [UHS_SDR12] = "UHS SDR12 (25MHz)",
171 [UHS_SDR25] = "UHS SDR25 (50MHz)",
172 [UHS_SDR50] = "UHS SDR50 (100MHz)",
173 [UHS_SDR104] = "UHS SDR104 (208MHz)",
174 [UHS_DDR50] = "UHS DDR50 (50MHz)",
175 [MMC_HS_52] = "MMC High Speed (52MHz)",
176 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
177 [MMC_HS_200] = "HS200 (200MHz)",
178 };
179
180 if (mode >= MMC_MODES_END)
181 return "Unknown mode";
182 else
183 return names[mode];
184}
185#endif
186
05038576
JJH		 187static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
188{
189 static const int freqs[] = {
190 [SD_LEGACY] = 25000000,
191 [MMC_HS] = 26000000,
192 [SD_HS] = 50000000,
193 [UHS_SDR12] = 25000000,
194 [UHS_SDR25] = 50000000,
195 [UHS_SDR50] = 100000000,
196 [UHS_SDR104] = 208000000,
197 [UHS_DDR50] = 50000000,
198 [MMC_HS_52] = 52000000,
199 [MMC_DDR_52] = 52000000,
200 [MMC_HS_200] = 200000000,
201 };
202
203 if (mode == MMC_LEGACY)
204 return mmc->legacy_speed;
205 else if (mode >= MMC_MODES_END)
206 return 0;
207 else
208 return freqs[mode];
209}
210
35f9e196
JJH		 211static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
212{
213 mmc->selected_mode = mode;
05038576 214 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 215 mmc->ddr_mode = mmc_is_mode_ddr(mode);
35f9e196
JJH		 216 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
217 mmc->tran_speed / 1000000);
218 return 0;
219}
220
e7881d85 221#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 222int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
223{
224 int ret;
225
226 mmmc_trace_before_send(mmc, cmd);
227 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
228 mmmc_trace_after_send(mmc, cmd, ret);
229
8635ff9e 230 return ret;
272cc70b 231}
8ca51e51 232#endif
272cc70b 233
da61fa5f 234int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 235{
236 struct mmc_cmd cmd;
d617c426 237 int err, retries = 5;
5d4fc8d9
RR		 238
239 cmd.cmdidx = MMC_CMD_SEND_STATUS;
240 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 241 if (!mmc_host_is_spi(mmc))
242 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 243
1677eef4 244 while (1) {
5d4fc8d9 245 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 246 if (!err) {
247 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
248 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
249 MMC_STATE_PRG)
250 break;
d0c221fe
JJH		 251
252 if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 253#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 254 printf("Status Error: 0x%08X\n",
255 cmd.response[0]);
56196826 256#endif
915ffa52 257 return -ECOMM;
d617c426
JK		 258 }
259 } else if (--retries < 0)
5d4fc8d9 260 return err;
5d4fc8d9 261
1677eef4
AG		 262 if (timeout-- <= 0)
263 break;
5d4fc8d9 264
1677eef4
AG		 265 udelay(1000);
266 }
5d4fc8d9 267
c0c76eba 268 mmc_trace_state(mmc, &cmd);
5b0c942f 269 if (timeout <= 0) {
56196826 270#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 271 printf("Timeout waiting card ready\n");
56196826 272#endif
915ffa52 273 return -ETIMEDOUT;
5d4fc8d9
RR		 274 }
275
276 return 0;
277}
278
da61fa5f 279int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 280{
281 struct mmc_cmd cmd;
83dc4227 282 int err;
272cc70b 283
786e8f81 284 if (mmc->ddr_mode)
d22e3d46
JC		 285 return 0;
286
272cc70b
AF		 287 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
288 cmd.resp_type = MMC_RSP_R1;
289 cmd.cmdarg = len;
272cc70b 290
83dc4227
KVA		 291 err = mmc_send_cmd(mmc, &cmd, NULL);
292
293#ifdef CONFIG_MMC_QUIRKS
294 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
295 int retries = 4;
296 /*
297 * It has been seen that SET_BLOCKLEN may fail on the first
298 * attempt, let's try a few more time
299 */
300 do {
301 err = mmc_send_cmd(mmc, &cmd, NULL);
302 if (!err)
303 break;
304 } while (retries--);
305 }
306#endif
307
308 return err;
272cc70b
AF		 309}
310
ff8fef56 311static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 312 lbaint_t blkcnt)
272cc70b
AF		 313{
314 struct mmc_cmd cmd;
315 struct mmc_data data;
316
4a1a06bc
AS		 317 if (blkcnt > 1)
318 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
319 else
320 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 321
322 if (mmc->high_capacity)
4a1a06bc 323 cmd.cmdarg = start;
272cc70b 324 else
4a1a06bc 325 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 326
327 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 328
329 data.dest = dst;
4a1a06bc 330 data.blocks = blkcnt;
272cc70b
AF		 331 data.blocksize = mmc->read_bl_len;
332 data.flags = MMC_DATA_READ;
333
4a1a06bc
AS		 334 if (mmc_send_cmd(mmc, &cmd, &data))
335 return 0;
272cc70b 336
4a1a06bc
AS		 337 if (blkcnt > 1) {
338 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
339 cmd.cmdarg = 0;
340 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 341 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 342#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 343 printf("mmc fail to send stop cmd\n");
56196826 344#endif
4a1a06bc
AS		 345 return 0;
346 }
272cc70b
AF		 347 }
348
4a1a06bc 349 return blkcnt;
272cc70b
AF		 350}
351
c4d660d4 352#if CONFIG_IS_ENABLED(BLK)
7dba0b93 353ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 354#else
7dba0b93
SG		 355ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
356 void *dst)
33fb211d 357#endif
272cc70b 358{
c4d660d4 359#if CONFIG_IS_ENABLED(BLK)
33fb211d
SG		 360 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
361#endif
bcce53d0 362 int dev_num = block_dev->devnum;
873cc1d7 363 int err;
4a1a06bc
AS		 364 lbaint_t cur, blocks_todo = blkcnt;
365
366 if (blkcnt == 0)
367 return 0;
272cc70b 368
4a1a06bc 369 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 370 if (!mmc)
371 return 0;
372
b5b838f1
MV		 373 if (CONFIG_IS_ENABLED(MMC_TINY))
374 err = mmc_switch_part(mmc, block_dev->hwpart);
375 else
376 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
377
873cc1d7
SW		 378 if (err < 0)
379 return 0;
380
c40fdca6 381 if ((start + blkcnt) > block_dev->lba) {
56196826 382#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 383 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
c40fdca6 384 start + blkcnt, block_dev->lba);
56196826 385#endif
d2bf29e3
LW		 386 return 0;
387 }
272cc70b 388
11692991
SG		 389 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
390 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 391 return 0;
11692991 392 }
272cc70b 393
4a1a06bc 394 do {
93bfd616
PA		 395 cur = (blocks_todo > mmc->cfg->b_max) ?
396 mmc->cfg->b_max : blocks_todo;
11692991
SG		 397 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
398 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 399 return 0;
11692991 400 }
4a1a06bc
AS		 401 blocks_todo -= cur;
402 start += cur;
403 dst += cur * mmc->read_bl_len;
404 } while (blocks_todo > 0);
272cc70b
AF		 405
406 return blkcnt;
407}
408
fdbb873e 409static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 410{
411 struct mmc_cmd cmd;
412 int err;
413
414 udelay(1000);
415
416 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
417 cmd.cmdarg = 0;
418 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 419
420 err = mmc_send_cmd(mmc, &cmd, NULL);
421
422 if (err)
423 return err;
424
425 udelay(2000);
426
427 return 0;
428}
429
c10b85d6
JJH		 430static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
431{
432 struct mmc_cmd cmd;
433 int err = 0;
434
435 /*
436 * Send CMD11 only if the request is to switch the card to
437 * 1.8V signalling.
438 */
439 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
440 return mmc_set_signal_voltage(mmc, signal_voltage);
441
442 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
443 cmd.cmdarg = 0;
444 cmd.resp_type = MMC_RSP_R1;
445
446 err = mmc_send_cmd(mmc, &cmd, NULL);
447 if (err)
448 return err;
449
450 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
451 return -EIO;
452
453 /*
454 * The card should drive cmd and dat[0:3] low immediately
455 * after the response of cmd11, but wait 100 us to be sure
456 */
457 err = mmc_wait_dat0(mmc, 0, 100);
458 if (err == -ENOSYS)
459 udelay(100);
460 else if (err)
461 return -ETIMEDOUT;
462
463 /*
464 * During a signal voltage level switch, the clock must be gated
465 * for 5 ms according to the SD spec
466 */
467 mmc_set_clock(mmc, mmc->clock, true);
468
469 err = mmc_set_signal_voltage(mmc, signal_voltage);
470 if (err)
471 return err;
472
473 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
474 mdelay(10);
475 mmc_set_clock(mmc, mmc->clock, false);
476
477 /*
478 * Failure to switch is indicated by the card holding
479 * dat[0:3] low. Wait for at least 1 ms according to spec
480 */
481 err = mmc_wait_dat0(mmc, 1, 1000);
482 if (err == -ENOSYS)
483 udelay(1000);
484 else if (err)
485 return -ETIMEDOUT;
486
487 return 0;
488}
489
490static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 491{
492 int timeout = 1000;
493 int err;
494 struct mmc_cmd cmd;
495
1677eef4 496 while (1) {
272cc70b
AF		 497 cmd.cmdidx = MMC_CMD_APP_CMD;
498 cmd.resp_type = MMC_RSP_R1;
499 cmd.cmdarg = 0;
272cc70b
AF		 500
501 err = mmc_send_cmd(mmc, &cmd, NULL);
502
503 if (err)
504 return err;
505
506 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
507 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 508
509 /*
510 * Most cards do not answer if some reserved bits
511 * in the ocr are set. However, Some controller
512 * can set bit 7 (reserved for low voltages), but
513 * how to manage low voltages SD card is not yet
514 * specified.
515 */
d52ebf10 516 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 517 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 518
519 if (mmc->version == SD_VERSION_2)
520 cmd.cmdarg |= OCR_HCS;
521
c10b85d6
JJH		 522 if (uhs_en)
523 cmd.cmdarg |= OCR_S18R;
524
272cc70b
AF		 525 err = mmc_send_cmd(mmc, &cmd, NULL);
526
527 if (err)
528 return err;
529
1677eef4
AG		 530 if (cmd.response[0] & OCR_BUSY)
531 break;
532
533 if (timeout-- <= 0)
915ffa52 534 return -EOPNOTSUPP;
272cc70b 535
1677eef4
AG		 536 udelay(1000);
537 }
272cc70b
AF		 538
539 if (mmc->version != SD_VERSION_2)
540 mmc->version = SD_VERSION_1_0;
541
d52ebf10
TC		 542 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
543 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
544 cmd.resp_type = MMC_RSP_R3;
545 cmd.cmdarg = 0;
d52ebf10
TC		 546
547 err = mmc_send_cmd(mmc, &cmd, NULL);
548
549 if (err)
550 return err;
551 }
552
998be3dd 553 mmc->ocr = cmd.response[0];
272cc70b 554
c10b85d6
JJH		 555 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
556 == 0x41000000) {
557 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
558 if (err)
559 return err;
560 }
561
272cc70b
AF		 562 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
563 mmc->rca = 0;
564
565 return 0;
566}
567
5289b535 568static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 569{
5289b535 570 struct mmc_cmd cmd;
272cc70b
AF		 571 int err;
572
5289b535
AG		 573 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
574 cmd.resp_type = MMC_RSP_R3;
575 cmd.cmdarg = 0;
5a20397b
RH		 576 if (use_arg && !mmc_host_is_spi(mmc))
577 cmd.cmdarg = OCR_HCS |
93bfd616 578 (mmc->cfg->voltages &
a626c8d4
AG		 579 (mmc->ocr & OCR_VOLTAGE_MASK)) |
580 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 581
5289b535 582 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 583 if (err)
584 return err;
5289b535 585 mmc->ocr = cmd.response[0];
e9550449
CLC		 586 return 0;
587}
588
750121c3 589static int mmc_send_op_cond(struct mmc *mmc)
e9550449 590{
e9550449
CLC		 591 int err, i;
592
272cc70b
AF		 593 /* Some cards seem to need this */
594 mmc_go_idle(mmc);
595
31cacbab 596 /* Asking to the card its capabilities */
e9550449 597 for (i = 0; i < 2; i++) {
5289b535 598 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 599 if (err)
600 return err;
cd6881b5 601
e9550449 602 /* exit if not busy (flag seems to be inverted) */
a626c8d4 603 if (mmc->ocr & OCR_BUSY)
bd47c135 604 break;
e9550449 605 }
bd47c135
AG		 606 mmc->op_cond_pending = 1;
607 return 0;
e9550449 608}
cd6881b5 609
750121c3 610static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 611{
612 struct mmc_cmd cmd;
613 int timeout = 1000;
614 uint start;
615 int err;
cd6881b5 616
e9550449 617 mmc->op_cond_pending = 0;
cc17c01f 618 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 619 /* Some cards seem to need this */
620 mmc_go_idle(mmc);
621
cc17c01f 622 start = get_timer(0);
1677eef4 623 while (1) {
cc17c01f
AG		 624 err = mmc_send_op_cond_iter(mmc, 1);
625 if (err)
626 return err;
1677eef4
AG		 627 if (mmc->ocr & OCR_BUSY)
628 break;
cc17c01f 629 if (get_timer(start) > timeout)
915ffa52 630 return -EOPNOTSUPP;
cc17c01f 631 udelay(100);
1677eef4 632 }
cc17c01f 633 }
272cc70b 634
d52ebf10
TC		 635 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
636 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
637 cmd.resp_type = MMC_RSP_R3;
638 cmd.cmdarg = 0;
d52ebf10
TC		 639
640 err = mmc_send_cmd(mmc, &cmd, NULL);
641
642 if (err)
643 return err;
a626c8d4
AG		 644
645 mmc->ocr = cmd.response[0];
d52ebf10
TC		 646 }
647
272cc70b 648 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 649
650 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 651 mmc->rca = 1;
272cc70b
AF		 652
653 return 0;
654}
655
656
fdbb873e 657static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 658{
659 struct mmc_cmd cmd;
660 struct mmc_data data;
661 int err;
662
663 /* Get the Card Status Register */
664 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
665 cmd.resp_type = MMC_RSP_R1;
666 cmd.cmdarg = 0;
272cc70b 667
cdfd1ac6 668 data.dest = (char *)ext_csd;
272cc70b 669 data.blocks = 1;
8bfa195e 670 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 671 data.flags = MMC_DATA_READ;
672
673 err = mmc_send_cmd(mmc, &cmd, &data);
674
675 return err;
676}
677
c40704f4 678int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 679{
680 struct mmc_cmd cmd;
5d4fc8d9 681 int timeout = 1000;
a9003dc6 682 int retries = 3;
5d4fc8d9 683 int ret;
272cc70b
AF		 684
685 cmd.cmdidx = MMC_CMD_SWITCH;
686 cmd.resp_type = MMC_RSP_R1b;
687 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 688 (index << 16) |
689 (value << 8);
272cc70b 690
a9003dc6
MR		 691 while (retries > 0) {
692 ret = mmc_send_cmd(mmc, &cmd, NULL);
5d4fc8d9 693
a9003dc6
MR		 694 /* Waiting for the ready status */
695 if (!ret) {
696 ret = mmc_send_status(mmc, timeout);
697 return ret;
698 }
699
700 retries--;
701 }
5d4fc8d9
RR		 702
703 return ret;
704
272cc70b
AF		 705}
706
3862b854 707static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
272cc70b 708{
272cc70b 709 int err;
3862b854
JJH		 710 int speed_bits;
711
712 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
713
714 switch (mode) {
715 case MMC_HS:
716 case MMC_HS_52:
717 case MMC_DDR_52:
718 speed_bits = EXT_CSD_TIMING_HS;
634d4849
KVA		 719 break;
720 case MMC_HS_200:
721 speed_bits = EXT_CSD_TIMING_HS200;
722 break;
3862b854
JJH		 723 case MMC_LEGACY:
724 speed_bits = EXT_CSD_TIMING_LEGACY;
725 break;
726 default:
727 return -EINVAL;
728 }
729 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
730 speed_bits);
731 if (err)
732 return err;
733
734 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
735 /* Now check to see that it worked */
736 err = mmc_send_ext_csd(mmc, test_csd);
737 if (err)
738 return err;
739
740 /* No high-speed support */
741 if (!test_csd[EXT_CSD_HS_TIMING])
742 return -ENOTSUPP;
743 }
744
745 return 0;
746}
747
748static int mmc_get_capabilities(struct mmc *mmc)
749{
750 u8 *ext_csd = mmc->ext_csd;
751 char cardtype;
272cc70b 752
d0c221fe 753 mmc->card_caps = MMC_MODE_1BIT;
272cc70b 754
d52ebf10
TC		 755 if (mmc_host_is_spi(mmc))
756 return 0;
757
272cc70b
AF		 758 /* Only version 4 supports high-speed */
759 if (mmc->version < MMC_VERSION_4)
760 return 0;
761
3862b854
JJH		 762 if (!ext_csd) {
763 printf("No ext_csd found!\n"); /* this should enver happen */
764 return -ENOTSUPP;
765 }
272cc70b 766
3862b854 767 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 768
634d4849 769 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
272cc70b 770
634d4849
KVA		 771 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
772 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
773 mmc->card_caps |= MMC_MODE_HS200;
774 }
d22e3d46 775 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 776 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 777 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 778 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 779 }
3862b854
JJH		 780 if (cardtype & EXT_CSD_CARD_TYPE_26)
781 mmc->card_caps |= MMC_MODE_HS;
272cc70b
AF		 782
783 return 0;
784}
785
f866a46d
SW		 786static int mmc_set_capacity(struct mmc *mmc, int part_num)
787{
788 switch (part_num) {
789 case 0:
790 mmc->capacity = mmc->capacity_user;
791 break;
792 case 1:
793 case 2:
794 mmc->capacity = mmc->capacity_boot;
795 break;
796 case 3:
797 mmc->capacity = mmc->capacity_rpmb;
798 break;
799 case 4:
800 case 5:
801 case 6:
802 case 7:
803 mmc->capacity = mmc->capacity_gp[part_num - 4];
804 break;
805 default:
806 return -1;
807 }
808
c40fdca6 809 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 810
811 return 0;
812}
813
01298da3
JJH		 814static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
815{
816 int forbidden = 0;
817 bool change = false;
818
819 if (part_num & PART_ACCESS_MASK)
820 forbidden = MMC_CAP(MMC_HS_200);
821
822 if (MMC_CAP(mmc->selected_mode) & forbidden) {
823 debug("selected mode (%s) is forbidden for part %d\n",
824 mmc_mode_name(mmc->selected_mode), part_num);
825 change = true;
826 } else if (mmc->selected_mode != mmc->best_mode) {
827 debug("selected mode is not optimal\n");
828 change = true;
829 }
830
831 if (change)
832 return mmc_select_mode_and_width(mmc,
833 mmc->card_caps & ~forbidden);
834
835 return 0;
836}
837
7dba0b93 838int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 839{
f866a46d 840 int ret;
bc897b1d 841
01298da3
JJH		 842 ret = mmc_boot_part_access_chk(mmc, part_num);
843 if (ret)
844 return ret;
845
f866a46d
SW		 846 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
847 (mmc->part_config & ~PART_ACCESS_MASK)
848 | (part_num & PART_ACCESS_MASK));
f866a46d 849
6dc93e70
PB		 850 /*
851 * Set the capacity if the switch succeeded or was intended
852 * to return to representing the raw device.
853 */
873cc1d7 854 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 855 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 856 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 857 }
6dc93e70
PB		 858
859 return ret;
bc897b1d
LW		 860}
861
ac9da0e0
DSC		 862int mmc_hwpart_config(struct mmc *mmc,
863 const struct mmc_hwpart_conf *conf,
864 enum mmc_hwpart_conf_mode mode)
865{
866 u8 part_attrs = 0;
867 u32 enh_size_mult;
868 u32 enh_start_addr;
869 u32 gp_size_mult[4];
870 u32 max_enh_size_mult;
871 u32 tot_enh_size_mult = 0;
8dda5b0e 872 u8 wr_rel_set;
ac9da0e0
DSC		 873 int i, pidx, err;
874 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
875
876 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
877 return -EINVAL;
878
879 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
880 printf("eMMC >= 4.4 required for enhanced user data area\n");
881 return -EMEDIUMTYPE;
882 }
883
884 if (!(mmc->part_support & PART_SUPPORT)) {
885 printf("Card does not support partitioning\n");
886 return -EMEDIUMTYPE;
887 }
888
889 if (!mmc->hc_wp_grp_size) {
890 printf("Card does not define HC WP group size\n");
891 return -EMEDIUMTYPE;
892 }
893
894 /* check partition alignment and total enhanced size */
895 if (conf->user.enh_size) {
896 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
897 conf->user.enh_start % mmc->hc_wp_grp_size) {
898 printf("User data enhanced area not HC WP group "
899 "size aligned\n");
900 return -EINVAL;
901 }
902 part_attrs |= EXT_CSD_ENH_USR;
903 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
904 if (mmc->high_capacity) {
905 enh_start_addr = conf->user.enh_start;
906 } else {
907 enh_start_addr = (conf->user.enh_start << 9);
908 }
909 } else {
910 enh_size_mult = 0;
911 enh_start_addr = 0;
912 }
913 tot_enh_size_mult += enh_size_mult;
914
915 for (pidx = 0; pidx < 4; pidx++) {
916 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
917 printf("GP%i partition not HC WP group size "
918 "aligned\n", pidx+1);
919 return -EINVAL;
920 }
921 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
922 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
923 part_attrs |= EXT_CSD_ENH_GP(pidx);
924 tot_enh_size_mult += gp_size_mult[pidx];
925 }
926 }
927
928 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
929 printf("Card does not support enhanced attribute\n");
930 return -EMEDIUMTYPE;
931 }
932
933 err = mmc_send_ext_csd(mmc, ext_csd);
934 if (err)
935 return err;
936
937 max_enh_size_mult =
938 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
939 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
940 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
941 if (tot_enh_size_mult > max_enh_size_mult) {
942 printf("Total enhanced size exceeds maximum (%u > %u)\n",
943 tot_enh_size_mult, max_enh_size_mult);
944 return -EMEDIUMTYPE;
945 }
946
8dda5b0e
DSC		 947 /* The default value of EXT_CSD_WR_REL_SET is device
948 * dependent, the values can only be changed if the
949 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
950 * changed only once and before partitioning is completed. */
951 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
952 if (conf->user.wr_rel_change) {
953 if (conf->user.wr_rel_set)
954 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
955 else
956 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
957 }
958 for (pidx = 0; pidx < 4; pidx++) {
959 if (conf->gp_part[pidx].wr_rel_change) {
960 if (conf->gp_part[pidx].wr_rel_set)
961 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
962 else
963 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
964 }
965 }
966
967 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
968 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
969 puts("Card does not support host controlled partition write "
970 "reliability settings\n");
971 return -EMEDIUMTYPE;
972 }
973
ac9da0e0
DSC		 974 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
975 EXT_CSD_PARTITION_SETTING_COMPLETED) {
976 printf("Card already partitioned\n");
977 return -EPERM;
978 }
979
980 if (mode == MMC_HWPART_CONF_CHECK)
981 return 0;
982
983 /* Partitioning requires high-capacity size definitions */
984 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
985 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
986 EXT_CSD_ERASE_GROUP_DEF, 1);
987
988 if (err)
989 return err;
990
991 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
992
993 /* update erase group size to be high-capacity */
994 mmc->erase_grp_size =
995 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
996
997 }
998
999 /* all OK, write the configuration */
1000 for (i = 0; i < 4; i++) {
1001 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1002 EXT_CSD_ENH_START_ADDR+i,
1003 (enh_start_addr >> (i*8)) & 0xFF);
1004 if (err)
1005 return err;
1006 }
1007 for (i = 0; i < 3; i++) {
1008 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1009 EXT_CSD_ENH_SIZE_MULT+i,
1010 (enh_size_mult >> (i*8)) & 0xFF);
1011 if (err)
1012 return err;
1013 }
1014 for (pidx = 0; pidx < 4; pidx++) {
1015 for (i = 0; i < 3; i++) {
1016 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1017 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1018 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1019 if (err)
1020 return err;
1021 }
1022 }
1023 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1024 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1025 if (err)
1026 return err;
1027
1028 if (mode == MMC_HWPART_CONF_SET)
1029 return 0;
1030
8dda5b0e
DSC		 1031 /* The WR_REL_SET is a write-once register but shall be
1032 * written before setting PART_SETTING_COMPLETED. As it is
1033 * write-once we can only write it when completing the
1034 * partitioning. */
1035 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1036 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1037 EXT_CSD_WR_REL_SET, wr_rel_set);
1038 if (err)
1039 return err;
1040 }
1041
ac9da0e0
DSC		 1042 /* Setting PART_SETTING_COMPLETED confirms the partition
1043 * configuration but it only becomes effective after power
1044 * cycle, so we do not adjust the partition related settings
1045 * in the mmc struct. */
1046
1047 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1048 EXT_CSD_PARTITION_SETTING,
1049 EXT_CSD_PARTITION_SETTING_COMPLETED);
1050 if (err)
1051 return err;
1052
1053 return 0;
1054}
1055
e7881d85 1056#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1057int mmc_getcd(struct mmc *mmc)
1058{
1059 int cd;
1060
1061 cd = board_mmc_getcd(mmc);
1062
d4e1da4e 1063 if (cd < 0) {
93bfd616
PA		 1064 if (mmc->cfg->ops->getcd)
1065 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1066 else
1067 cd = 1;
1068 }
48972d90
TR		 1069
1070 return cd;
1071}
8ca51e51 1072#endif
48972d90 1073
fdbb873e 1074static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1075{
1076 struct mmc_cmd cmd;
1077 struct mmc_data data;
1078
1079 /* Switch the frequency */
1080 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1081 cmd.resp_type = MMC_RSP_R1;
1082 cmd.cmdarg = (mode << 31) | 0xffffff;
1083 cmd.cmdarg &= ~(0xf << (group * 4));
1084 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1085
1086 data.dest = (char *)resp;
1087 data.blocksize = 64;
1088 data.blocks = 1;
1089 data.flags = MMC_DATA_READ;
1090
1091 return mmc_send_cmd(mmc, &cmd, &data);
1092}
1093
1094
d0c221fe 1095static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1096{
1097 int err;
1098 struct mmc_cmd cmd;
18e7c8f6
SM		 1099 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1100 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1101 struct mmc_data data;
1102 int timeout;
c10b85d6 1103 u32 sd3_bus_mode;
272cc70b 1104
d0c221fe 1105 mmc->card_caps = MMC_MODE_1BIT;
272cc70b 1106
d52ebf10
TC		 1107 if (mmc_host_is_spi(mmc))
1108 return 0;
1109
272cc70b
AF		 1110 /* Read the SCR to find out if this card supports higher speeds */
1111 cmd.cmdidx = MMC_CMD_APP_CMD;
1112 cmd.resp_type = MMC_RSP_R1;
1113 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1114
1115 err = mmc_send_cmd(mmc, &cmd, NULL);
1116
1117 if (err)
1118 return err;
1119
1120 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1121 cmd.resp_type = MMC_RSP_R1;
1122 cmd.cmdarg = 0;
272cc70b
AF		 1123
1124 timeout = 3;
1125
1126retry_scr:
f781dd38 1127 data.dest = (char *)scr;
272cc70b
AF		 1128 data.blocksize = 8;
1129 data.blocks = 1;
1130 data.flags = MMC_DATA_READ;
1131
1132 err = mmc_send_cmd(mmc, &cmd, &data);
1133
1134 if (err) {
1135 if (timeout--)
1136 goto retry_scr;
1137
1138 return err;
1139 }
1140
4e3d89ba
YK		 1141 mmc->scr[0] = __be32_to_cpu(scr[0]);
1142 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1143
1144 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1145 case 0:
1146 mmc->version = SD_VERSION_1_0;
1147 break;
1148 case 1:
1149 mmc->version = SD_VERSION_1_10;
1150 break;
1151 case 2:
1152 mmc->version = SD_VERSION_2;
1153 if ((mmc->scr[0] >> 15) & 0x1)
1154 mmc->version = SD_VERSION_3;
1155 break;
1156 default:
1157 mmc->version = SD_VERSION_1_0;
1158 break;
272cc70b
AF		 1159 }
1160
b44c7083
AS		 1161 if (mmc->scr[0] & SD_DATA_4BIT)
1162 mmc->card_caps |= MMC_MODE_4BIT;
1163
272cc70b
AF		 1164 /* Version 1.0 doesn't support switching */
1165 if (mmc->version == SD_VERSION_1_0)
1166 return 0;
1167
1168 timeout = 4;
1169 while (timeout--) {
1170 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1171 (u8 *)switch_status);
272cc70b
AF		 1172
1173 if (err)
1174 return err;
1175
1176 /* The high-speed function is busy. Try again */
4e3d89ba 1177 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1178 break;
1179 }
1180
272cc70b 1181 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1182 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1183 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1184
c10b85d6
JJH		 1185 /* Version before 3.0 don't support UHS modes */
1186 if (mmc->version < SD_VERSION_3)
1187 return 0;
1188
1189 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1190 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1191 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1192 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1193 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1194 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1195 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1196 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1197 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1198 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1199 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1200
d0c221fe
JJH		 1201 return 0;
1202}
1203
1204static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1205{
1206 int err;
1207
1208 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1209 int speed;
2c3fbf4c 1210
c10b85d6
JJH		 1211 switch (mode) {
1212 case SD_LEGACY:
1213 case UHS_SDR12:
1214 speed = UHS_SDR12_BUS_SPEED;
1215 break;
1216 case SD_HS:
1217 case UHS_SDR25:
1218 speed = UHS_SDR25_BUS_SPEED;
1219 break;
1220 case UHS_SDR50:
1221 speed = UHS_SDR50_BUS_SPEED;
1222 break;
1223 case UHS_DDR50:
1224 speed = UHS_DDR50_BUS_SPEED;
1225 break;
1226 case UHS_SDR104:
1227 speed = UHS_SDR104_BUS_SPEED;
1228 break;
1229 default:
1230 return -EINVAL;
1231 }
1232
1233 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1234 if (err)
1235 return err;
1236
c10b85d6 1237 if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
d0c221fe 1238 return -ENOTSUPP;
272cc70b 1239
d0c221fe
JJH		 1240 return 0;
1241}
1242
1243int sd_select_bus_width(struct mmc *mmc, int w)
1244{
1245 int err;
1246 struct mmc_cmd cmd;
1247
1248 if ((w != 4) && (w != 1))
1249 return -EINVAL;
1250
1251 cmd.cmdidx = MMC_CMD_APP_CMD;
1252 cmd.resp_type = MMC_RSP_R1;
1253 cmd.cmdarg = mmc->rca << 16;
1254
1255 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1256 if (err)
1257 return err;
1258
d0c221fe
JJH		 1259 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1260 cmd.resp_type = MMC_RSP_R1;
1261 if (w == 4)
1262 cmd.cmdarg = 2;
1263 else if (w == 1)
1264 cmd.cmdarg = 0;
1265 err = mmc_send_cmd(mmc, &cmd, NULL);
1266 if (err)
1267 return err;
272cc70b
AF		 1268
1269 return 0;
1270}
1271
3697e599
PF		 1272static int sd_read_ssr(struct mmc *mmc)
1273{
1274 int err, i;
1275 struct mmc_cmd cmd;
1276 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1277 struct mmc_data data;
1278 int timeout = 3;
1279 unsigned int au, eo, et, es;
1280
1281 cmd.cmdidx = MMC_CMD_APP_CMD;
1282 cmd.resp_type = MMC_RSP_R1;
1283 cmd.cmdarg = mmc->rca << 16;
1284
1285 err = mmc_send_cmd(mmc, &cmd, NULL);
1286 if (err)
1287 return err;
1288
1289 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1290 cmd.resp_type = MMC_RSP_R1;
1291 cmd.cmdarg = 0;
1292
1293retry_ssr:
1294 data.dest = (char *)ssr;
1295 data.blocksize = 64;
1296 data.blocks = 1;
1297 data.flags = MMC_DATA_READ;
1298
1299 err = mmc_send_cmd(mmc, &cmd, &data);
1300 if (err) {
1301 if (timeout--)
1302 goto retry_ssr;
1303
1304 return err;
1305 }
1306
1307 for (i = 0; i < 16; i++)
1308 ssr[i] = be32_to_cpu(ssr[i]);
1309
1310 au = (ssr[2] >> 12) & 0xF;
1311 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1312 mmc->ssr.au = sd_au_size[au];
1313 es = (ssr[3] >> 24) & 0xFF;
1314 es |= (ssr[2] & 0xFF) << 8;
1315 et = (ssr[3] >> 18) & 0x3F;
1316 if (es && et) {
1317 eo = (ssr[3] >> 16) & 0x3;
1318 mmc->ssr.erase_timeout = (et * 1000) / es;
1319 mmc->ssr.erase_offset = eo * 1000;
1320 }
1321 } else {
1322 debug("Invalid Allocation Unit Size.\n");
1323 }
1324
1325 return 0;
1326}
1327
272cc70b
AF		 1328/* frequency bases */
1329/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1330static const int fbase[] = {
272cc70b
AF		 1331 10000,
1332 100000,
1333 1000000,
1334 10000000,
1335};
1336
1337/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1338 * to platforms without floating point.
1339 */
61fe076f 1340static const u8 multipliers[] = {
272cc70b
AF		 1341 0, /* reserved */
1342 10,
1343 12,
1344 13,
1345 15,
1346 20,
1347 25,
1348 30,
1349 35,
1350 40,
1351 45,
1352 50,
1353 55,
1354 60,
1355 70,
1356 80,
1357};
1358
d0c221fe
JJH		 1359static inline int bus_width(uint cap)
1360{
1361 if (cap == MMC_MODE_8BIT)
1362 return 8;
1363 if (cap == MMC_MODE_4BIT)
1364 return 4;
1365 if (cap == MMC_MODE_1BIT)
1366 return 1;
1367 printf("invalid bus witdh capability 0x%x\n", cap);
1368 return 0;
1369}
1370
e7881d85 1371#if !CONFIG_IS_ENABLED(DM_MMC)
ec841209
KVA		 1372static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1373{
1374 return -ENOTSUPP;
1375}
1376
318a7a57
JJH		 1377static void mmc_send_init_stream(struct mmc *mmc)
1378{
1379}
1380
2a4d212f 1381static int mmc_set_ios(struct mmc *mmc)
272cc70b 1382{
2a4d212f
KVA		 1383 int ret = 0;
1384
93bfd616 1385 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1386 ret = mmc->cfg->ops->set_ios(mmc);
1387
1388 return ret;
272cc70b 1389}
8ca51e51 1390#endif
272cc70b 1391
35f67820 1392int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1393{
93bfd616
PA		 1394 if (clock > mmc->cfg->f_max)
1395 clock = mmc->cfg->f_max;
272cc70b 1396
93bfd616
PA		 1397 if (clock < mmc->cfg->f_min)
1398 clock = mmc->cfg->f_min;
272cc70b
AF		 1399
1400 mmc->clock = clock;
35f67820 1401 mmc->clk_disable = disable;
272cc70b 1402
2a4d212f 1403 return mmc_set_ios(mmc);
272cc70b
AF		 1404}
1405
2a4d212f 1406static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1407{
1408 mmc->bus_width = width;
1409
2a4d212f 1410 return mmc_set_ios(mmc);
272cc70b
AF		 1411}
1412
4c9d2aaa
JJH		 1413#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1414/*
1415 * helper function to display the capabilities in a human
1416 * friendly manner. The capabilities include bus width and
1417 * supported modes.
1418 */
1419void mmc_dump_capabilities(const char *text, uint caps)
1420{
1421 enum bus_mode mode;
1422
1423 printf("%s: widths [", text);
1424 if (caps & MMC_MODE_8BIT)
1425 printf("8, ");
1426 if (caps & MMC_MODE_4BIT)
1427 printf("4, ");
d0c221fe
JJH		 1428 if (caps & MMC_MODE_1BIT)
1429 printf("1, ");
1430 printf("\b\b] modes [");
4c9d2aaa
JJH		 1431 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1432 if (MMC_CAP(mode) & caps)
1433 printf("%s, ", mmc_mode_name(mode));
1434 printf("\b\b]\n");
1435}
1436#endif
1437
d0c221fe
JJH		 1438struct mode_width_tuning {
1439 enum bus_mode mode;
1440 uint widths;
634d4849 1441 uint tuning;
d0c221fe
JJH		 1442};
1443
aff5d3c8
KVA		 1444static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1445{
1446 mmc->signal_voltage = signal_voltage;
1447 return mmc_set_ios(mmc);
1448}
1449
d0c221fe 1450static const struct mode_width_tuning sd_modes_by_pref[] = {
c10b85d6
JJH		 1451 {
1452 .mode = UHS_SDR104,
1453 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1454 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1455 },
1456 {
1457 .mode = UHS_SDR50,
1458 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1459 },
1460 {
1461 .mode = UHS_DDR50,
1462 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1463 },
1464 {
1465 .mode = UHS_SDR25,
1466 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1467 },
d0c221fe
JJH		 1468 {
1469 .mode = SD_HS,
1470 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1471 },
c10b85d6
JJH		 1472 {
1473 .mode = UHS_SDR12,
1474 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1475 },
d0c221fe
JJH		 1476 {
1477 .mode = SD_LEGACY,
1478 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1479 }
1480};
1481
1482#define for_each_sd_mode_by_pref(caps, mwt) \
1483 for (mwt = sd_modes_by_pref;\
1484 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1485 mwt++) \
1486 if (caps & MMC_CAP(mwt->mode))
1487
01298da3 1488static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1489{
1490 int err;
d0c221fe
JJH		 1491 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1492 const struct mode_width_tuning *mwt;
c10b85d6
JJH		 1493 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1494 uint caps;
1495
8ac8a263 1496
8ac8a263 1497 /* Restrict card's capabilities by what the host can do */
01298da3 1498 caps = card_caps & (mmc->host_caps | MMC_MODE_1BIT);
d0c221fe 1499
c10b85d6
JJH		 1500 if (!uhs_en)
1501 caps &= ~UHS_CAPS;
1502
1503 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1504 uint *w;
1505
1506 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1507 if (*w & caps & mwt->widths) {
d0c221fe
JJH		 1508 debug("trying mode %s width %d (at %d MHz)\n",
1509 mmc_mode_name(mwt->mode),
1510 bus_width(*w),
1511 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1512
1513 /* configure the bus width (card + host) */
1514 err = sd_select_bus_width(mmc, bus_width(*w));
1515 if (err)
1516 goto error;
1517 mmc_set_bus_width(mmc, bus_width(*w));
1518
1519 /* configure the bus mode (card) */
1520 err = sd_set_card_speed(mmc, mwt->mode);
1521 if (err)
1522 goto error;
1523
1524 /* configure the bus mode (host) */
1525 mmc_select_mode(mmc, mwt->mode);
35f67820 1526 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe 1527
c10b85d6
JJH		 1528 /* execute tuning if needed */
1529 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1530 err = mmc_execute_tuning(mmc,
1531 mwt->tuning);
1532 if (err) {
1533 debug("tuning failed\n");
1534 goto error;
1535 }
1536 }
1537
d0c221fe
JJH		 1538 err = sd_read_ssr(mmc);
1539 if (!err)
1540 return 0;
1541
1542 printf("bad ssr\n");
1543
1544error:
1545 /* revert to a safer bus speed */
1546 mmc_select_mode(mmc, SD_LEGACY);
35f67820 1547 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe
JJH		 1548 }
1549 }
8ac8a263
JJH		 1550 }
1551
d0c221fe
JJH		 1552 printf("unable to select a mode\n");
1553 return -ENOTSUPP;
8ac8a263
JJH		 1554}
1555
7382e691
JJH		 1556/*
1557 * read the compare the part of ext csd that is constant.
1558 * This can be used to check that the transfer is working
1559 * as expected.
1560 */
1561static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1562{
7382e691 1563 int err;
dfda9d88 1564 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1565 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1566
1567 err = mmc_send_ext_csd(mmc, test_csd);
1568 if (err)
1569 return err;
1570
1571 /* Only compare read only fields */
1572 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1573 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1574 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1575 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1576 ext_csd[EXT_CSD_REV]
1577 == test_csd[EXT_CSD_REV] &&
1578 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1579 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1580 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1581 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1582 return 0;
1583
1584 return -EBADMSG;
1585}
1586
3862b854
JJH		 1587static const struct mode_width_tuning mmc_modes_by_pref[] = {
1588 {
1589 .mode = MMC_HS_200,
1590 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1591 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854
JJH		 1592 },
1593 {
1594 .mode = MMC_DDR_52,
1595 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1596 },
1597 {
1598 .mode = MMC_HS_52,
1599 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1600 },
1601 {
1602 .mode = MMC_HS,
1603 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1604 },
1605 {
1606 .mode = MMC_LEGACY,
1607 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1608 }
1609};
1610
1611#define for_each_mmc_mode_by_pref(caps, mwt) \
1612 for (mwt = mmc_modes_by_pref;\
1613 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1614 mwt++) \
1615 if (caps & MMC_CAP(mwt->mode))
1616
1617static const struct ext_csd_bus_width {
1618 uint cap;
1619 bool is_ddr;
1620 uint ext_csd_bits;
1621} ext_csd_bus_width[] = {
1622 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1623 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1624 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1625 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1626 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1627};
1628
1629#define for_each_supported_width(caps, ddr, ecbv) \
1630 for (ecbv = ext_csd_bus_width;\
1631 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1632 ecbv++) \
1633 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1634
01298da3 1635static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 1636{
8ac8a263 1637 int err;
3862b854
JJH		 1638 const struct mode_width_tuning *mwt;
1639 const struct ext_csd_bus_width *ecbw;
8ac8a263 1640
8ac8a263 1641 /* Restrict card's capabilities by what the host can do */
01298da3 1642 card_caps &= (mmc->host_caps | MMC_MODE_1BIT);
8ac8a263
JJH		 1643
1644 /* Only version 4 of MMC supports wider bus widths */
1645 if (mmc->version < MMC_VERSION_4)
1646 return 0;
1647
dfda9d88
JJH		 1648 if (!mmc->ext_csd) {
1649 debug("No ext_csd found!\n"); /* this should enver happen */
1650 return -ENOTSUPP;
1651 }
1652
01298da3
JJH		 1653 mmc_set_clock(mmc, mmc->legacy_speed, false);
1654
1655 for_each_mmc_mode_by_pref(card_caps, mwt) {
1656 for_each_supported_width(card_caps & mwt->widths,
3862b854
JJH		 1657 mmc_is_mode_ddr(mwt->mode), ecbw) {
1658 debug("trying mode %s width %d (at %d MHz)\n",
1659 mmc_mode_name(mwt->mode),
1660 bus_width(ecbw->cap),
1661 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1662 /* configure the bus width (card + host) */
1663 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1664 EXT_CSD_BUS_WIDTH,
1665 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1666 if (err)
1667 goto error;
1668 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 1669
3862b854
JJH		 1670 /* configure the bus speed (card) */
1671 err = mmc_set_card_speed(mmc, mwt->mode);
1672 if (err)
1673 goto error;
1674
1675 /*
1676 * configure the bus width AND the ddr mode (card)
1677 * The host side will be taken care of in the next step
1678 */
1679 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1680 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1681 EXT_CSD_BUS_WIDTH,
1682 ecbw->ext_csd_bits);
1683 if (err)
1684 goto error;
1685 }
8ac8a263 1686
3862b854
JJH		 1687 /* configure the bus mode (host) */
1688 mmc_select_mode(mmc, mwt->mode);
35f67820 1689 mmc_set_clock(mmc, mmc->tran_speed, false);
8ac8a263 1690
634d4849
KVA		 1691 /* execute tuning if needed */
1692 if (mwt->tuning) {
1693 err = mmc_execute_tuning(mmc, mwt->tuning);
1694 if (err) {
1695 debug("tuning failed\n");
1696 goto error;
1697 }
1698 }
1699
3862b854
JJH		 1700 /* do a transfer to check the configuration */
1701 err = mmc_read_and_compare_ext_csd(mmc);
1702 if (!err)
1703 return 0;
1704error:
1705 /* if an error occured, revert to a safer bus mode */
1706 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1707 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1708 mmc_select_mode(mmc, MMC_LEGACY);
1709 mmc_set_bus_width(mmc, 1);
1710 }
8ac8a263
JJH		 1711 }
1712
3862b854 1713 printf("unable to select a mode\n");
8ac8a263 1714
3862b854 1715 return -ENOTSUPP;
8ac8a263
JJH		 1716}
1717
dfda9d88 1718static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 1719{
1720 int err, i;
1721 u64 capacity;
1722 bool has_parts = false;
1723 bool part_completed;
dfda9d88 1724 u8 *ext_csd;
c744b6f6
JJH		 1725
1726 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1727 return 0;
1728
dfda9d88
JJH		 1729 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1730 if (!ext_csd)
1731 return -ENOMEM;
1732
1733 mmc->ext_csd = ext_csd;
1734
c744b6f6
JJH		 1735 /* check ext_csd version and capacity */
1736 err = mmc_send_ext_csd(mmc, ext_csd);
1737 if (err)
1738 return err;
1739 if (ext_csd[EXT_CSD_REV] >= 2) {
1740 /*
1741 * According to the JEDEC Standard, the value of
1742 * ext_csd's capacity is valid if the value is more
1743 * than 2GB
1744 */
1745 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1746 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1747 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1748 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1749 capacity *= MMC_MAX_BLOCK_LEN;
1750 if ((capacity >> 20) > 2 * 1024)
1751 mmc->capacity_user = capacity;
1752 }
1753
1754 switch (ext_csd[EXT_CSD_REV]) {
1755 case 1:
1756 mmc->version = MMC_VERSION_4_1;
1757 break;
1758 case 2:
1759 mmc->version = MMC_VERSION_4_2;
1760 break;
1761 case 3:
1762 mmc->version = MMC_VERSION_4_3;
1763 break;
1764 case 5:
1765 mmc->version = MMC_VERSION_4_41;
1766 break;
1767 case 6:
1768 mmc->version = MMC_VERSION_4_5;
1769 break;
1770 case 7:
1771 mmc->version = MMC_VERSION_5_0;
1772 break;
1773 case 8:
1774 mmc->version = MMC_VERSION_5_1;
1775 break;
1776 }
1777
1778 /* The partition data may be non-zero but it is only
1779 * effective if PARTITION_SETTING_COMPLETED is set in
1780 * EXT_CSD, so ignore any data if this bit is not set,
1781 * except for enabling the high-capacity group size
1782 * definition (see below).
1783 */
1784 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1785 EXT_CSD_PARTITION_SETTING_COMPLETED);
1786
1787 /* store the partition info of emmc */
1788 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1789 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1790 ext_csd[EXT_CSD_BOOT_MULT])
1791 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1792 if (part_completed &&
1793 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1794 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1795
1796 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1797
1798 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1799
1800 for (i = 0; i < 4; i++) {
1801 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1802 uint mult = (ext_csd[idx + 2] << 16) +
1803 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1804 if (mult)
1805 has_parts = true;
1806 if (!part_completed)
1807 continue;
1808 mmc->capacity_gp[i] = mult;
1809 mmc->capacity_gp[i] *=
1810 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1811 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1812 mmc->capacity_gp[i] <<= 19;
1813 }
1814
1815 if (part_completed) {
1816 mmc->enh_user_size =
1817 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1818 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1819 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1820 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1821 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1822 mmc->enh_user_size <<= 19;
1823 mmc->enh_user_start =
1824 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1825 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1826 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1827 ext_csd[EXT_CSD_ENH_START_ADDR];
1828 if (mmc->high_capacity)
1829 mmc->enh_user_start <<= 9;
1830 }
1831
1832 /*
1833 * Host needs to enable ERASE_GRP_DEF bit if device is
1834 * partitioned. This bit will be lost every time after a reset
1835 * or power off. This will affect erase size.
1836 */
1837 if (part_completed)
1838 has_parts = true;
1839 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1840 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1841 has_parts = true;
1842 if (has_parts) {
1843 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1844 EXT_CSD_ERASE_GROUP_DEF, 1);
1845
1846 if (err)
1847 return err;
1848
1849 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1850 }
1851
1852 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1853 /* Read out group size from ext_csd */
1854 mmc->erase_grp_size =
1855 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1856 /*
1857 * if high capacity and partition setting completed
1858 * SEC_COUNT is valid even if it is smaller than 2 GiB
1859 * JEDEC Standard JESD84-B45, 6.2.4
1860 */
1861 if (mmc->high_capacity && part_completed) {
1862 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1863 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1864 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1865 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1866 capacity *= MMC_MAX_BLOCK_LEN;
1867 mmc->capacity_user = capacity;
1868 }
1869 } else {
1870 /* Calculate the group size from the csd value. */
1871 int erase_gsz, erase_gmul;
1872
1873 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1874 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1875 mmc->erase_grp_size = (erase_gsz + 1)
1876 * (erase_gmul + 1);
1877 }
1878
1879 mmc->hc_wp_grp_size = 1024
1880 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1881 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1882
1883 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1884
1885 return 0;
1886}
1887
fdbb873e 1888static int mmc_startup(struct mmc *mmc)
272cc70b 1889{
f866a46d 1890 int err, i;
272cc70b 1891 uint mult, freq;
c744b6f6 1892 u64 cmult, csize;
272cc70b 1893 struct mmc_cmd cmd;
c40fdca6 1894 struct blk_desc *bdesc;
272cc70b 1895
d52ebf10
TC		 1896#ifdef CONFIG_MMC_SPI_CRC_ON
1897 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1898 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1899 cmd.resp_type = MMC_RSP_R1;
1900 cmd.cmdarg = 1;
d52ebf10 1901 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 1902 if (err)
1903 return err;
1904 }
1905#endif
1906
272cc70b 1907 /* Put the Card in Identify Mode */
d52ebf10
TC		 1908 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1909 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1910 cmd.resp_type = MMC_RSP_R2;
1911 cmd.cmdarg = 0;
272cc70b
AF		 1912
1913 err = mmc_send_cmd(mmc, &cmd, NULL);
1914
83dc4227
KVA		 1915#ifdef CONFIG_MMC_QUIRKS
1916 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
1917 int retries = 4;
1918 /*
1919 * It has been seen that SEND_CID may fail on the first
1920 * attempt, let's try a few more time
1921 */
1922 do {
1923 err = mmc_send_cmd(mmc, &cmd, NULL);
1924 if (!err)
1925 break;
1926 } while (retries--);
1927 }
1928#endif
1929
272cc70b
AF		 1930 if (err)
1931 return err;
1932
1933 memcpy(mmc->cid, cmd.response, 16);
1934
1935 /*
1936 * For MMC cards, set the Relative Address.
1937 * For SD cards, get the Relatvie Address.
1938 * This also puts the cards into Standby State
1939 */
d52ebf10
TC		 1940 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1941 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1942 cmd.cmdarg = mmc->rca << 16;
1943 cmd.resp_type = MMC_RSP_R6;
272cc70b 1944
d52ebf10 1945 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1946
d52ebf10
TC		 1947 if (err)
1948 return err;
272cc70b 1949
d52ebf10
TC		 1950 if (IS_SD(mmc))
1951 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1952 }
272cc70b
AF		 1953
1954 /* Get the Card-Specific Data */
1955 cmd.cmdidx = MMC_CMD_SEND_CSD;
1956 cmd.resp_type = MMC_RSP_R2;
1957 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1958
1959 err = mmc_send_cmd(mmc, &cmd, NULL);
1960
1961 if (err)
1962 return err;
1963
998be3dd
RV		 1964 mmc->csd[0] = cmd.response[0];
1965 mmc->csd[1] = cmd.response[1];
1966 mmc->csd[2] = cmd.response[2];
1967 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1968
1969 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1970 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1971
1972 switch (version) {
53e8e40b
BM		 1973 case 0:
1974 mmc->version = MMC_VERSION_1_2;
1975 break;
1976 case 1:
1977 mmc->version = MMC_VERSION_1_4;
1978 break;
1979 case 2:
1980 mmc->version = MMC_VERSION_2_2;
1981 break;
1982 case 3:
1983 mmc->version = MMC_VERSION_3;
1984 break;
1985 case 4:
1986 mmc->version = MMC_VERSION_4;
1987 break;
1988 default:
1989 mmc->version = MMC_VERSION_1_2;
1990 break;
272cc70b
AF		 1991 }
1992 }
1993
1994 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1995 freq = fbase[(cmd.response[0] & 0x7)];
1996 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 1997
35f9e196 1998 mmc->legacy_speed = freq * mult;
35f9e196 1999 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2000
ab71188c 2001 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2002 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 2003
2004 if (IS_SD(mmc))
2005 mmc->write_bl_len = mmc->read_bl_len;
2006 else
998be3dd 2007 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 2008
2009 if (mmc->high_capacity) {
2010 csize = (mmc->csd[1] & 0x3f) << 16
2011 | (mmc->csd[2] & 0xffff0000) >> 16;
2012 cmult = 8;
2013 } else {
2014 csize = (mmc->csd[1] & 0x3ff) << 2
2015 | (mmc->csd[2] & 0xc0000000) >> 30;
2016 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2017 }
2018
f866a46d
SW		 2019 mmc->capacity_user = (csize + 1) << (cmult + 2);
2020 mmc->capacity_user *= mmc->read_bl_len;
2021 mmc->capacity_boot = 0;
2022 mmc->capacity_rpmb = 0;
2023 for (i = 0; i < 4; i++)
2024 mmc->capacity_gp[i] = 0;
272cc70b 2025
8bfa195e
SG		 2026 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2027 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2028
8bfa195e
SG		 2029 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2030 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2031
ab71188c
MN		 2032 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2033 cmd.cmdidx = MMC_CMD_SET_DSR;
2034 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2035 cmd.resp_type = MMC_RSP_NONE;
2036 if (mmc_send_cmd(mmc, &cmd, NULL))
2037 printf("MMC: SET_DSR failed\n");
2038 }
2039
272cc70b 2040 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2041 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2042 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2043 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2044 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2045 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2046
d52ebf10
TC		 2047 if (err)
2048 return err;
2049 }
272cc70b 2050
e6f99a56
LW		 2051 /*
2052 * For SD, its erase group is always one sector
2053 */
2054 mmc->erase_grp_size = 1;
bc897b1d 2055 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2056
dfda9d88 2057 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2058 if (err)
2059 return err;
d23e2c09 2060
c40fdca6 2061 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2062 if (err)
2063 return err;
2064
01298da3
JJH		 2065 if (IS_SD(mmc)) {
2066 err = sd_get_capabilities(mmc);
2067 if (err)
2068 return err;
2069 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2070 } else {
2071 err = mmc_get_capabilities(mmc);
2072 if (err)
2073 return err;
2074 mmc_select_mode_and_width(mmc, mmc->card_caps);
2075 }
272cc70b
AF		 2076
2077 if (err)
2078 return err;
2079
01298da3 2080 mmc->best_mode = mmc->selected_mode;
ad5fd922 2081
5af8f45c
AG		 2082 /* Fix the block length for DDR mode */
2083 if (mmc->ddr_mode) {
2084 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2085 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2086 }
2087
272cc70b 2088 /* fill in device description */
c40fdca6
SG		 2089 bdesc = mmc_get_blk_desc(mmc);
2090 bdesc->lun = 0;
2091 bdesc->hwpart = 0;
2092 bdesc->type = 0;
2093 bdesc->blksz = mmc->read_bl_len;
2094 bdesc->log2blksz = LOG2(bdesc->blksz);
2095 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2096#if !defined(CONFIG_SPL_BUILD) || \
2097 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2098 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 2099 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2100 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2101 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2102 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2103 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2104 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2105 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2106 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2107 (mmc->cid[2] >> 16) & 0xf);
56196826 2108#else
c40fdca6
SG		 2109 bdesc->vendor[0] = 0;
2110 bdesc->product[0] = 0;
2111 bdesc->revision[0] = 0;
56196826 2112#endif
122efd43 2113#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
c40fdca6 2114 part_init(bdesc);
122efd43 2115#endif
272cc70b
AF		 2116
2117 return 0;
2118}
2119
fdbb873e 2120static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2121{
2122 struct mmc_cmd cmd;
2123 int err;
2124
2125 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2126 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2127 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2128 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2129
2130 err = mmc_send_cmd(mmc, &cmd, NULL);
2131
2132 if (err)
2133 return err;
2134
998be3dd 2135 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2136 return -EOPNOTSUPP;
272cc70b
AF		 2137 else
2138 mmc->version = SD_VERSION_2;
2139
2140 return 0;
2141}
2142
c4d660d4 2143#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2144/* board-specific MMC power initializations. */
2145__weak void board_mmc_power_init(void)
2146{
2147}
05cbeb7c 2148#endif
95de9ab2 2149
2051aefe
PF		 2150static int mmc_power_init(struct mmc *mmc)
2151{
c4d660d4 2152#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2153#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2154 int ret;
2155
2156 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2157 &mmc->vmmc_supply);
2158 if (ret)
288db7c7 2159 debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2160
06ec045f
JJH		 2161 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2162 &mmc->vqmmc_supply);
2163 if (ret)
2164 debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2165#endif
2166#else /* !CONFIG_DM_MMC */
2167 /*
2168 * Driver model should use a regulator, as above, rather than calling
2169 * out to board code.
2170 */
2171 board_mmc_power_init();
2172#endif
2173 return 0;
2174}
2175
2176/*
2177 * put the host in the initial state:
2178 * - turn on Vdd (card power supply)
2179 * - configure the bus width and clock to minimal values
2180 */
2181static void mmc_set_initial_state(struct mmc *mmc)
2182{
2183 int err;
2184
2185 /* First try to set 3.3V. If it fails set to 1.8V */
2186 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2187 if (err != 0)
2188 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2189 if (err != 0)
2190 printf("mmc: failed to set signal voltage\n");
2191
2192 mmc_select_mode(mmc, MMC_LEGACY);
2193 mmc_set_bus_width(mmc, 1);
35f67820 2194 mmc_set_clock(mmc, 0, false);
fb7c3beb 2195}
06ec045f 2196
fb7c3beb
KVA		 2197static int mmc_power_on(struct mmc *mmc)
2198{
2199#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2200 if (mmc->vmmc_supply) {
fb7c3beb
KVA		 2201 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2202
06ec045f
JJH		 2203 if (ret) {
2204 puts("Error enabling VMMC supply\n");
2205 return ret;
2206 }
2051aefe 2207 }
05cbeb7c 2208#endif
fb7c3beb
KVA		 2209 return 0;
2210}
2211
2212static int mmc_power_off(struct mmc *mmc)
2213{
2e7410d7 2214 mmc_set_clock(mmc, 1, true);
fb7c3beb
KVA		 2215#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2216 if (mmc->vmmc_supply) {
2217 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2218
2219 if (ret) {
c10b85d6 2220 debug("Error disabling VMMC supply\n");
fb7c3beb
KVA		 2221 return ret;
2222 }
2223 }
2051aefe
PF		 2224#endif
2225 return 0;
2226}
2227
fb7c3beb
KVA		 2228static int mmc_power_cycle(struct mmc *mmc)
2229{
2230 int ret;
2231
2232 ret = mmc_power_off(mmc);
2233 if (ret)
2234 return ret;
2235 /*
2236 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2237 * to be on the safer side.
2238 */
2239 udelay(2000);
2240 return mmc_power_on(mmc);
2241}
2242
e9550449 2243int mmc_start_init(struct mmc *mmc)
272cc70b 2244{
8ca51e51 2245 bool no_card;
c10b85d6 2246 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2247 int err;
272cc70b 2248
04a2ea24
JJH		 2249 mmc->host_caps = mmc->cfg->host_caps;
2250
ab769f22 2251 /* we pretend there's no card when init is NULL */
8ca51e51 2252 no_card = mmc_getcd(mmc) == 0;
e7881d85 2253#if !CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2254 no_card = no_card || (mmc->cfg->ops->init == NULL);
2255#endif
2256 if (no_card) {
48972d90 2257 mmc->has_init = 0;
56196826 2258#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 2259 printf("MMC: no card present\n");
56196826 2260#endif
915ffa52 2261 return -ENOMEDIUM;
48972d90
TR		 2262 }
2263
bc897b1d
LW		 2264 if (mmc->has_init)
2265 return 0;
2266
5a8dbdc6
YL		 2267#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2268 mmc_adapter_card_type_ident();
2269#endif
2051aefe
PF		 2270 err = mmc_power_init(mmc);
2271 if (err)
2272 return err;
95de9ab2 2273
83dc4227
KVA		 2274#ifdef CONFIG_MMC_QUIRKS
2275 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2276 MMC_QUIRK_RETRY_SEND_CID;
2277#endif
2278
04a2ea24
JJH		 2279 err = mmc_power_cycle(mmc);
2280 if (err) {
2281 /*
2282 * if power cycling is not supported, we should not try
2283 * to use the UHS modes, because we wouldn't be able to
2284 * recover from an error during the UHS initialization.
2285 */
2286 debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2287 uhs_en = false;
2288 mmc->host_caps &= ~UHS_CAPS;
2289 err = mmc_power_on(mmc);
2290 }
fb7c3beb
KVA		 2291 if (err)
2292 return err;
2293
e7881d85 2294#if CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2295 /* The device has already been probed ready for use */
2296#else
ab769f22 2297 /* made sure it's not NULL earlier */
93bfd616 2298 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 2299 if (err)
2300 return err;
8ca51e51 2301#endif
786e8f81 2302 mmc->ddr_mode = 0;
aff5d3c8 2303
c10b85d6 2304retry:
fb7c3beb 2305 mmc_set_initial_state(mmc);
318a7a57
JJH		 2306 mmc_send_init_stream(mmc);
2307
272cc70b
AF		 2308 /* Reset the Card */
2309 err = mmc_go_idle(mmc);
2310
2311 if (err)
2312 return err;
2313
bc897b1d 2314 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 2315 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2316
272cc70b 2317 /* Test for SD version 2 */
afd5932b 2318 err = mmc_send_if_cond(mmc);
272cc70b 2319
272cc70b 2320 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2321 err = sd_send_op_cond(mmc, uhs_en);
2322 if (err && uhs_en) {
2323 uhs_en = false;
2324 mmc_power_cycle(mmc);
2325 goto retry;
2326 }
272cc70b
AF		 2327
2328 /* If the command timed out, we check for an MMC card */
915ffa52 2329 if (err == -ETIMEDOUT) {
272cc70b
AF		 2330 err = mmc_send_op_cond(mmc);
2331
bd47c135 2332 if (err) {
56196826 2333#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 2334 printf("Card did not respond to voltage select!\n");
56196826 2335#endif
915ffa52 2336 return -EOPNOTSUPP;
272cc70b
AF		 2337 }
2338 }
2339
bd47c135 2340 if (!err)
e9550449
CLC		 2341 mmc->init_in_progress = 1;
2342
2343 return err;
2344}
2345
2346static int mmc_complete_init(struct mmc *mmc)
2347{
2348 int err = 0;
2349
bd47c135 2350 mmc->init_in_progress = 0;
e9550449
CLC		 2351 if (mmc->op_cond_pending)
2352 err = mmc_complete_op_cond(mmc);
2353
2354 if (!err)
2355 err = mmc_startup(mmc);
bc897b1d
LW		 2356 if (err)
2357 mmc->has_init = 0;
2358 else
2359 mmc->has_init = 1;
e9550449
CLC		 2360 return err;
2361}
2362
2363int mmc_init(struct mmc *mmc)
2364{
bd47c135 2365 int err = 0;
ce9eca94 2366 __maybe_unused unsigned start;
c4d660d4 2367#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 2368 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 2369
33fb211d
SG		 2370 upriv->mmc = mmc;
2371#endif
e9550449
CLC		 2372 if (mmc->has_init)
2373 return 0;
d803fea5
MZ		 2374
2375 start = get_timer(0);
2376
e9550449
CLC		 2377 if (!mmc->init_in_progress)
2378 err = mmc_start_init(mmc);
2379
bd47c135 2380 if (!err)
e9550449 2381 err = mmc_complete_init(mmc);
919b4858
JT		 2382 if (err)
2383 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2384
bc897b1d 2385 return err;
272cc70b
AF		 2386}
2387
ab71188c
MN		 2388int mmc_set_dsr(struct mmc *mmc, u16 val)
2389{
2390 mmc->dsr = val;
2391 return 0;
2392}
2393
cee9ab7c
JH		 2394/* CPU-specific MMC initializations */
2395__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 2396{
2397 return -1;
2398}
2399
cee9ab7c
JH		 2400/* board-specific MMC initializations. */
2401__weak int board_mmc_init(bd_t *bis)
2402{
2403 return -1;
2404}
272cc70b 2405
e9550449
CLC		 2406void mmc_set_preinit(struct mmc *mmc, int preinit)
2407{
2408 mmc->preinit = preinit;
2409}
2410
c4d660d4 2411#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
8e3332e2
SS		 2412static int mmc_probe(bd_t *bis)
2413{
2414 return 0;
2415}
c4d660d4 2416#elif CONFIG_IS_ENABLED(DM_MMC)
8e3332e2
SS		 2417static int mmc_probe(bd_t *bis)
2418{
4a1db6d8 2419 int ret, i;
8e3332e2 2420 struct uclass *uc;
4a1db6d8 2421 struct udevice *dev;
8e3332e2
SS		 2422
2423 ret = uclass_get(UCLASS_MMC, &uc);
2424 if (ret)
2425 return ret;
2426
4a1db6d8
SG		 2427 /*
2428 * Try to add them in sequence order. Really with driver model we
2429 * should allow holes, but the current MMC list does not allow that.
2430 * So if we request 0, 1, 3 we will get 0, 1, 2.
2431 */
2432 for (i = 0; ; i++) {
2433 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2434 if (ret == -ENODEV)
2435 break;
2436 }
2437 uclass_foreach_dev(dev, uc) {
2438 ret = device_probe(dev);
8e3332e2 2439 if (ret)
4a1db6d8 2440 printf("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 2441 }
2442
2443 return 0;
2444}
2445#else
2446static int mmc_probe(bd_t *bis)
2447{
2448 if (board_mmc_init(bis) < 0)
2449 cpu_mmc_init(bis);
2450
2451 return 0;
2452}
2453#endif
e9550449 2454
272cc70b
AF		 2455int mmc_initialize(bd_t *bis)
2456{
1b26bab1 2457 static int initialized = 0;
8e3332e2 2458 int ret;
1b26bab1
DK		 2459 if (initialized) /* Avoid initializing mmc multiple times */
2460 return 0;
2461 initialized = 1;
2462
c4d660d4 2463#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 2464#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 2465 mmc_list_init();
b5b838f1 2466#endif
c40fdca6 2467#endif
8e3332e2
SS		 2468 ret = mmc_probe(bis);
2469 if (ret)
2470 return ret;
272cc70b 2471
bb0dc108 2472#ifndef CONFIG_SPL_BUILD
272cc70b 2473 print_mmc_devices(',');
bb0dc108 2474#endif
272cc70b 2475
c40fdca6 2476 mmc_do_preinit();
272cc70b
AF		 2477 return 0;
2478}
cd3d4880
TM		 2479
2480#ifdef CONFIG_CMD_BKOPS_ENABLE
2481int mmc_set_bkops_enable(struct mmc *mmc)
2482{
2483 int err;
2484 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2485
2486 err = mmc_send_ext_csd(mmc, ext_csd);
2487 if (err) {
2488 puts("Could not get ext_csd register values\n");
2489 return err;
2490 }
2491
2492 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2493 puts("Background operations not supported on device\n");
2494 return -EMEDIUMTYPE;
2495 }
2496
2497 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2498 puts("Background operations already enabled\n");
2499 return 0;
2500 }
2501
2502 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2503 if (err) {
2504 puts("Failed to enable manual background operations\n");
2505 return err;
2506 }
2507
2508 puts("Enabled manual background operations\n");
2509
2510 return 0;
2511}
2512#endif
"Das U-Boot" Source Tree