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mmc: atmel: when sending a data command, use the provided block size
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
2051aefe 18#include <power/regulator.h>
272cc70b 19#include <malloc.h>
cf92e05c 20#include <memalign.h>
272cc70b 21#include <linux/list.h>
9b1f942c 22#include <div64.h>
da61fa5f 23#include "mmc_private.h"
272cc70b 24
3697e599
PF		 25static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31};
32
aff5d3c8 33static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
fb7c3beb 34static int mmc_power_cycle(struct mmc *mmc);
01298da3 35static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
aff5d3c8 36
b5b838f1
MV		 37#if CONFIG_IS_ENABLED(MMC_TINY)
38static struct mmc mmc_static;
39struct mmc *find_mmc_device(int dev_num)
40{
41 return &mmc_static;
42}
43
44void mmc_do_preinit(void)
45{
46 struct mmc *m = &mmc_static;
47#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
48 mmc_set_preinit(m, 1);
49#endif
50 if (m->preinit)
51 mmc_start_init(m);
52}
53
54struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
55{
56 return &mmc->block_dev;
57}
58#endif
59
e7881d85 60#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6 61
f99c2efe 62#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 63static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
64{
65 return -ENOSYS;
66}
f99c2efe 67#endif
c10b85d6 68
750121c3 69__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 70{
71 return -1;
72}
73
74int mmc_getwp(struct mmc *mmc)
75{
76 int wp;
77
78 wp = board_mmc_getwp(mmc);
79
d4e1da4e 80 if (wp < 0) {
93bfd616
PA		 81 if (mmc->cfg->ops->getwp)
82 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 83 else
84 wp = 0;
85 }
d23d8d7e
NK		 86
87 return wp;
88}
89
cee9ab7c
JH		 90__weak int board_mmc_getcd(struct mmc *mmc)
91{
11fdade2
SB		 92 return -1;
93}
8ca51e51 94#endif
11fdade2 95
c0c76eba
SG		 96#ifdef CONFIG_MMC_TRACE
97void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 98{
c0c76eba
SG		 99 printf("CMD_SEND:%d\n", cmd->cmdidx);
100 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
101}
8635ff9e 102
c0c76eba
SG		 103void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
104{
5db2fe3a
RR		 105 int i;
106 u8 *ptr;
107
7863ce58
BM		 108 if (ret) {
109 printf("\t\tRET\t\t\t %d\n", ret);
110 } else {
111 switch (cmd->resp_type) {
112 case MMC_RSP_NONE:
113 printf("\t\tMMC_RSP_NONE\n");
114 break;
115 case MMC_RSP_R1:
116 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
117 cmd->response[0]);
118 break;
119 case MMC_RSP_R1b:
120 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
121 cmd->response[0]);
122 break;
123 case MMC_RSP_R2:
124 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
125 cmd->response[0]);
126 printf("\t\t \t\t 0x%08X \n",
127 cmd->response[1]);
128 printf("\t\t \t\t 0x%08X \n",
129 cmd->response[2]);
130 printf("\t\t \t\t 0x%08X \n",
131 cmd->response[3]);
5db2fe3a 132 printf("\n");
7863ce58
BM		 133 printf("\t\t\t\t\tDUMPING DATA\n");
134 for (i = 0; i < 4; i++) {
135 int j;
136 printf("\t\t\t\t\t%03d - ", i*4);
137 ptr = (u8 *)&cmd->response[i];
138 ptr += 3;
139 for (j = 0; j < 4; j++)
140 printf("%02X ", *ptr--);
141 printf("\n");
142 }
143 break;
144 case MMC_RSP_R3:
145 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
146 cmd->response[0]);
147 break;
148 default:
149 printf("\t\tERROR MMC rsp not supported\n");
150 break;
53e8e40b 151 }
5db2fe3a 152 }
c0c76eba
SG		 153}
154
155void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
156{
157 int status;
158
159 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
160 printf("CURR STATE:%d\n", status);
161}
5db2fe3a 162#endif
c0c76eba 163
35f9e196
JJH		 164#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
165const char *mmc_mode_name(enum bus_mode mode)
166{
167 static const char *const names[] = {
168 [MMC_LEGACY] = "MMC legacy",
169 [SD_LEGACY] = "SD Legacy",
170 [MMC_HS] = "MMC High Speed (26MHz)",
171 [SD_HS] = "SD High Speed (50MHz)",
172 [UHS_SDR12] = "UHS SDR12 (25MHz)",
173 [UHS_SDR25] = "UHS SDR25 (50MHz)",
174 [UHS_SDR50] = "UHS SDR50 (100MHz)",
175 [UHS_SDR104] = "UHS SDR104 (208MHz)",
176 [UHS_DDR50] = "UHS DDR50 (50MHz)",
177 [MMC_HS_52] = "MMC High Speed (52MHz)",
178 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
179 [MMC_HS_200] = "HS200 (200MHz)",
180 };
181
182 if (mode >= MMC_MODES_END)
183 return "Unknown mode";
184 else
185 return names[mode];
186}
187#endif
188
05038576
JJH		 189static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
190{
191 static const int freqs[] = {
192 [SD_LEGACY] = 25000000,
193 [MMC_HS] = 26000000,
194 [SD_HS] = 50000000,
f99c2efe 195#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
05038576
JJH		 196 [UHS_SDR12] = 25000000,
197 [UHS_SDR25] = 50000000,
198 [UHS_SDR50] = 100000000,
05038576 199 [UHS_DDR50] = 50000000,
f99c2efe
JJH		 200#ifdef MMC_SUPPORTS_TUNING
201 [UHS_SDR104] = 208000000,
202#endif
203#endif
05038576
JJH		 204 [MMC_HS_52] = 52000000,
205 [MMC_DDR_52] = 52000000,
f99c2efe 206#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
05038576 207 [MMC_HS_200] = 200000000,
f99c2efe 208#endif
05038576
JJH		 209 };
210
211 if (mode == MMC_LEGACY)
212 return mmc->legacy_speed;
213 else if (mode >= MMC_MODES_END)
214 return 0;
215 else
216 return freqs[mode];
217}
218
35f9e196
JJH		 219static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
220{
221 mmc->selected_mode = mode;
05038576 222 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 223 mmc->ddr_mode = mmc_is_mode_ddr(mode);
35f9e196
JJH		 224 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
225 mmc->tran_speed / 1000000);
226 return 0;
227}
228
e7881d85 229#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 230int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
231{
232 int ret;
233
234 mmmc_trace_before_send(mmc, cmd);
235 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
236 mmmc_trace_after_send(mmc, cmd, ret);
237
8635ff9e 238 return ret;
272cc70b 239}
8ca51e51 240#endif
272cc70b 241
da61fa5f 242int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 243{
244 struct mmc_cmd cmd;
d617c426 245 int err, retries = 5;
5d4fc8d9
RR		 246
247 cmd.cmdidx = MMC_CMD_SEND_STATUS;
248 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 249 if (!mmc_host_is_spi(mmc))
250 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 251
1677eef4 252 while (1) {
5d4fc8d9 253 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 254 if (!err) {
255 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
256 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
257 MMC_STATE_PRG)
258 break;
d0c221fe
JJH		 259
260 if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 261#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420
JJH		 262 pr_err("Status Error: 0x%08X\n",
263 cmd.response[0]);
56196826 264#endif
915ffa52 265 return -ECOMM;
d617c426
JK		 266 }
267 } else if (--retries < 0)
5d4fc8d9 268 return err;
5d4fc8d9 269
1677eef4
AG		 270 if (timeout-- <= 0)
271 break;
5d4fc8d9 272
1677eef4
AG		 273 udelay(1000);
274 }
5d4fc8d9 275
c0c76eba 276 mmc_trace_state(mmc, &cmd);
5b0c942f 277 if (timeout <= 0) {
56196826 278#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 279 pr_err("Timeout waiting card ready\n");
56196826 280#endif
915ffa52 281 return -ETIMEDOUT;
5d4fc8d9
RR		 282 }
283
284 return 0;
285}
286
da61fa5f 287int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 288{
289 struct mmc_cmd cmd;
83dc4227 290 int err;
272cc70b 291
786e8f81 292 if (mmc->ddr_mode)
d22e3d46
JC		 293 return 0;
294
272cc70b
AF		 295 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
296 cmd.resp_type = MMC_RSP_R1;
297 cmd.cmdarg = len;
272cc70b 298
83dc4227
KVA		 299 err = mmc_send_cmd(mmc, &cmd, NULL);
300
301#ifdef CONFIG_MMC_QUIRKS
302 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
303 int retries = 4;
304 /*
305 * It has been seen that SET_BLOCKLEN may fail on the first
306 * attempt, let's try a few more time
307 */
308 do {
309 err = mmc_send_cmd(mmc, &cmd, NULL);
310 if (!err)
311 break;
312 } while (retries--);
313 }
314#endif
315
316 return err;
272cc70b
AF		 317}
318
f99c2efe 319#ifdef MMC_SUPPORTS_TUNING
9815e3ba
JJH		 320static const u8 tuning_blk_pattern_4bit[] = {
321 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
322 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
323 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
324 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
325 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
326 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
327 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
328 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
329};
330
331static const u8 tuning_blk_pattern_8bit[] = {
332 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
333 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
334 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
335 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
336 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
337 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
338 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
339 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
340 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
341 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
342 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
343 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
344 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
345 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
346 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
347 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
348};
349
350int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
351{
352 struct mmc_cmd cmd;
353 struct mmc_data data;
354 const u8 *tuning_block_pattern;
355 int size, err;
356
357 if (mmc->bus_width == 8) {
358 tuning_block_pattern = tuning_blk_pattern_8bit;
359 size = sizeof(tuning_blk_pattern_8bit);
360 } else if (mmc->bus_width == 4) {
361 tuning_block_pattern = tuning_blk_pattern_4bit;
362 size = sizeof(tuning_blk_pattern_4bit);
363 } else {
364 return -EINVAL;
365 }
366
367 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
368
369 cmd.cmdidx = opcode;
370 cmd.cmdarg = 0;
371 cmd.resp_type = MMC_RSP_R1;
372
373 data.dest = (void *)data_buf;
374 data.blocks = 1;
375 data.blocksize = size;
376 data.flags = MMC_DATA_READ;
377
378 err = mmc_send_cmd(mmc, &cmd, &data);
379 if (err)
380 return err;
381
382 if (memcmp(data_buf, tuning_block_pattern, size))
383 return -EIO;
384
385 return 0;
386}
f99c2efe 387#endif
9815e3ba 388
ff8fef56 389static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 390 lbaint_t blkcnt)
272cc70b
AF		 391{
392 struct mmc_cmd cmd;
393 struct mmc_data data;
394
4a1a06bc
AS		 395 if (blkcnt > 1)
396 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
397 else
398 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 399
400 if (mmc->high_capacity)
4a1a06bc 401 cmd.cmdarg = start;
272cc70b 402 else
4a1a06bc 403 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 404
405 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 406
407 data.dest = dst;
4a1a06bc 408 data.blocks = blkcnt;
272cc70b
AF		 409 data.blocksize = mmc->read_bl_len;
410 data.flags = MMC_DATA_READ;
411
4a1a06bc
AS		 412 if (mmc_send_cmd(mmc, &cmd, &data))
413 return 0;
272cc70b 414
4a1a06bc
AS		 415 if (blkcnt > 1) {
416 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
417 cmd.cmdarg = 0;
418 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 419 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 420#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 421 pr_err("mmc fail to send stop cmd\n");
56196826 422#endif
4a1a06bc
AS		 423 return 0;
424 }
272cc70b
AF		 425 }
426
4a1a06bc 427 return blkcnt;
272cc70b
AF		 428}
429
c4d660d4 430#if CONFIG_IS_ENABLED(BLK)
7dba0b93 431ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 432#else
7dba0b93
SG		 433ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
434 void *dst)
33fb211d 435#endif
272cc70b 436{
c4d660d4 437#if CONFIG_IS_ENABLED(BLK)
33fb211d
SG		 438 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
439#endif
bcce53d0 440 int dev_num = block_dev->devnum;
873cc1d7 441 int err;
4a1a06bc
AS		 442 lbaint_t cur, blocks_todo = blkcnt;
443
444 if (blkcnt == 0)
445 return 0;
272cc70b 446
4a1a06bc 447 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 448 if (!mmc)
449 return 0;
450
b5b838f1
MV		 451 if (CONFIG_IS_ENABLED(MMC_TINY))
452 err = mmc_switch_part(mmc, block_dev->hwpart);
453 else
454 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
455
873cc1d7
SW		 456 if (err < 0)
457 return 0;
458
c40fdca6 459 if ((start + blkcnt) > block_dev->lba) {
56196826 460#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420
JJH		 461 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
462 start + blkcnt, block_dev->lba);
56196826 463#endif
d2bf29e3
LW		 464 return 0;
465 }
272cc70b 466
11692991
SG		 467 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
468 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 469 return 0;
11692991 470 }
272cc70b 471
4a1a06bc 472 do {
93bfd616
PA		 473 cur = (blocks_todo > mmc->cfg->b_max) ?
474 mmc->cfg->b_max : blocks_todo;
11692991
SG		 475 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
476 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 477 return 0;
11692991 478 }
4a1a06bc
AS		 479 blocks_todo -= cur;
480 start += cur;
481 dst += cur * mmc->read_bl_len;
482 } while (blocks_todo > 0);
272cc70b
AF		 483
484 return blkcnt;
485}
486
fdbb873e 487static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 488{
489 struct mmc_cmd cmd;
490 int err;
491
492 udelay(1000);
493
494 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
495 cmd.cmdarg = 0;
496 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 497
498 err = mmc_send_cmd(mmc, &cmd, NULL);
499
500 if (err)
501 return err;
502
503 udelay(2000);
504
505 return 0;
506}
507
f99c2efe 508#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 509static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
510{
511 struct mmc_cmd cmd;
512 int err = 0;
513
514 /*
515 * Send CMD11 only if the request is to switch the card to
516 * 1.8V signalling.
517 */
518 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
519 return mmc_set_signal_voltage(mmc, signal_voltage);
520
521 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
522 cmd.cmdarg = 0;
523 cmd.resp_type = MMC_RSP_R1;
524
525 err = mmc_send_cmd(mmc, &cmd, NULL);
526 if (err)
527 return err;
528
529 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
530 return -EIO;
531
532 /*
533 * The card should drive cmd and dat[0:3] low immediately
534 * after the response of cmd11, but wait 100 us to be sure
535 */
536 err = mmc_wait_dat0(mmc, 0, 100);
537 if (err == -ENOSYS)
538 udelay(100);
539 else if (err)
540 return -ETIMEDOUT;
541
542 /*
543 * During a signal voltage level switch, the clock must be gated
544 * for 5 ms according to the SD spec
545 */
546 mmc_set_clock(mmc, mmc->clock, true);
547
548 err = mmc_set_signal_voltage(mmc, signal_voltage);
549 if (err)
550 return err;
551
552 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
553 mdelay(10);
554 mmc_set_clock(mmc, mmc->clock, false);
555
556 /*
557 * Failure to switch is indicated by the card holding
558 * dat[0:3] low. Wait for at least 1 ms according to spec
559 */
560 err = mmc_wait_dat0(mmc, 1, 1000);
561 if (err == -ENOSYS)
562 udelay(1000);
563 else if (err)
564 return -ETIMEDOUT;
565
566 return 0;
567}
f99c2efe 568#endif
c10b85d6
JJH		 569
570static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 571{
572 int timeout = 1000;
573 int err;
574 struct mmc_cmd cmd;
575
1677eef4 576 while (1) {
272cc70b
AF		 577 cmd.cmdidx = MMC_CMD_APP_CMD;
578 cmd.resp_type = MMC_RSP_R1;
579 cmd.cmdarg = 0;
272cc70b
AF		 580
581 err = mmc_send_cmd(mmc, &cmd, NULL);
582
583 if (err)
584 return err;
585
586 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
587 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 588
589 /*
590 * Most cards do not answer if some reserved bits
591 * in the ocr are set. However, Some controller
592 * can set bit 7 (reserved for low voltages), but
593 * how to manage low voltages SD card is not yet
594 * specified.
595 */
d52ebf10 596 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 597 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 598
599 if (mmc->version == SD_VERSION_2)
600 cmd.cmdarg |= OCR_HCS;
601
c10b85d6
JJH		 602 if (uhs_en)
603 cmd.cmdarg |= OCR_S18R;
604
272cc70b
AF		 605 err = mmc_send_cmd(mmc, &cmd, NULL);
606
607 if (err)
608 return err;
609
1677eef4
AG		 610 if (cmd.response[0] & OCR_BUSY)
611 break;
612
613 if (timeout-- <= 0)
915ffa52 614 return -EOPNOTSUPP;
272cc70b 615
1677eef4
AG		 616 udelay(1000);
617 }
272cc70b
AF		 618
619 if (mmc->version != SD_VERSION_2)
620 mmc->version = SD_VERSION_1_0;
621
d52ebf10
TC		 622 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
623 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
624 cmd.resp_type = MMC_RSP_R3;
625 cmd.cmdarg = 0;
d52ebf10
TC		 626
627 err = mmc_send_cmd(mmc, &cmd, NULL);
628
629 if (err)
630 return err;
631 }
632
998be3dd 633 mmc->ocr = cmd.response[0];
272cc70b 634
f99c2efe 635#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 636 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
637 == 0x41000000) {
638 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
639 if (err)
640 return err;
641 }
f99c2efe 642#endif
c10b85d6 643
272cc70b
AF		 644 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
645 mmc->rca = 0;
646
647 return 0;
648}
649
5289b535 650static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 651{
5289b535 652 struct mmc_cmd cmd;
272cc70b
AF		 653 int err;
654
5289b535
AG		 655 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
656 cmd.resp_type = MMC_RSP_R3;
657 cmd.cmdarg = 0;
5a20397b
RH		 658 if (use_arg && !mmc_host_is_spi(mmc))
659 cmd.cmdarg = OCR_HCS |
93bfd616 660 (mmc->cfg->voltages &
a626c8d4
AG		 661 (mmc->ocr & OCR_VOLTAGE_MASK)) |
662 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 663
5289b535 664 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 665 if (err)
666 return err;
5289b535 667 mmc->ocr = cmd.response[0];
e9550449
CLC		 668 return 0;
669}
670
750121c3 671static int mmc_send_op_cond(struct mmc *mmc)
e9550449 672{
e9550449
CLC		 673 int err, i;
674
272cc70b
AF		 675 /* Some cards seem to need this */
676 mmc_go_idle(mmc);
677
31cacbab 678 /* Asking to the card its capabilities */
e9550449 679 for (i = 0; i < 2; i++) {
5289b535 680 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 681 if (err)
682 return err;
cd6881b5 683
e9550449 684 /* exit if not busy (flag seems to be inverted) */
a626c8d4 685 if (mmc->ocr & OCR_BUSY)
bd47c135 686 break;
e9550449 687 }
bd47c135
AG		 688 mmc->op_cond_pending = 1;
689 return 0;
e9550449 690}
cd6881b5 691
750121c3 692static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 693{
694 struct mmc_cmd cmd;
695 int timeout = 1000;
696 uint start;
697 int err;
cd6881b5 698
e9550449 699 mmc->op_cond_pending = 0;
cc17c01f 700 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 701 /* Some cards seem to need this */
702 mmc_go_idle(mmc);
703
cc17c01f 704 start = get_timer(0);
1677eef4 705 while (1) {
cc17c01f
AG		 706 err = mmc_send_op_cond_iter(mmc, 1);
707 if (err)
708 return err;
1677eef4
AG		 709 if (mmc->ocr & OCR_BUSY)
710 break;
cc17c01f 711 if (get_timer(start) > timeout)
915ffa52 712 return -EOPNOTSUPP;
cc17c01f 713 udelay(100);
1677eef4 714 }
cc17c01f 715 }
272cc70b 716
d52ebf10
TC		 717 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
718 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
719 cmd.resp_type = MMC_RSP_R3;
720 cmd.cmdarg = 0;
d52ebf10
TC		 721
722 err = mmc_send_cmd(mmc, &cmd, NULL);
723
724 if (err)
725 return err;
a626c8d4
AG		 726
727 mmc->ocr = cmd.response[0];
d52ebf10
TC		 728 }
729
272cc70b 730 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 731
732 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 733 mmc->rca = 1;
272cc70b
AF		 734
735 return 0;
736}
737
738
fdbb873e 739static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 740{
741 struct mmc_cmd cmd;
742 struct mmc_data data;
743 int err;
744
745 /* Get the Card Status Register */
746 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
747 cmd.resp_type = MMC_RSP_R1;
748 cmd.cmdarg = 0;
272cc70b 749
cdfd1ac6 750 data.dest = (char *)ext_csd;
272cc70b 751 data.blocks = 1;
8bfa195e 752 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 753 data.flags = MMC_DATA_READ;
754
755 err = mmc_send_cmd(mmc, &cmd, &data);
756
757 return err;
758}
759
c40704f4 760int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 761{
762 struct mmc_cmd cmd;
5d4fc8d9 763 int timeout = 1000;
a9003dc6 764 int retries = 3;
5d4fc8d9 765 int ret;
272cc70b
AF		 766
767 cmd.cmdidx = MMC_CMD_SWITCH;
768 cmd.resp_type = MMC_RSP_R1b;
769 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 770 (index << 16) |
771 (value << 8);
272cc70b 772
a9003dc6
MR		 773 while (retries > 0) {
774 ret = mmc_send_cmd(mmc, &cmd, NULL);
5d4fc8d9 775
a9003dc6
MR		 776 /* Waiting for the ready status */
777 if (!ret) {
778 ret = mmc_send_status(mmc, timeout);
779 return ret;
780 }
781
782 retries--;
783 }
5d4fc8d9
RR		 784
785 return ret;
786
272cc70b
AF		 787}
788
3862b854 789static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
272cc70b 790{
272cc70b 791 int err;
3862b854
JJH		 792 int speed_bits;
793
794 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
795
796 switch (mode) {
797 case MMC_HS:
798 case MMC_HS_52:
799 case MMC_DDR_52:
800 speed_bits = EXT_CSD_TIMING_HS;
634d4849
KVA		 801 break;
802 case MMC_HS_200:
803 speed_bits = EXT_CSD_TIMING_HS200;
804 break;
3862b854
JJH		 805 case MMC_LEGACY:
806 speed_bits = EXT_CSD_TIMING_LEGACY;
807 break;
808 default:
809 return -EINVAL;
810 }
811 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
812 speed_bits);
813 if (err)
814 return err;
815
816 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
817 /* Now check to see that it worked */
818 err = mmc_send_ext_csd(mmc, test_csd);
819 if (err)
820 return err;
821
822 /* No high-speed support */
823 if (!test_csd[EXT_CSD_HS_TIMING])
824 return -ENOTSUPP;
825 }
826
827 return 0;
828}
829
830static int mmc_get_capabilities(struct mmc *mmc)
831{
832 u8 *ext_csd = mmc->ext_csd;
833 char cardtype;
272cc70b 834
00e446fa 835 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 836
d52ebf10
TC		 837 if (mmc_host_is_spi(mmc))
838 return 0;
839
272cc70b
AF		 840 /* Only version 4 supports high-speed */
841 if (mmc->version < MMC_VERSION_4)
842 return 0;
843
3862b854 844 if (!ext_csd) {
d8e3d420 845 pr_err("No ext_csd found!\n"); /* this should enver happen */
3862b854
JJH		 846 return -ENOTSUPP;
847 }
272cc70b 848
3862b854 849 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 850
634d4849 851 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
bc1e3272 852 mmc->cardtype = cardtype;
272cc70b 853
634d4849
KVA		 854 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
855 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
856 mmc->card_caps |= MMC_MODE_HS200;
857 }
d22e3d46 858 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 859 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 860 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 861 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 862 }
3862b854
JJH		 863 if (cardtype & EXT_CSD_CARD_TYPE_26)
864 mmc->card_caps |= MMC_MODE_HS;
272cc70b
AF		 865
866 return 0;
867}
868
f866a46d
SW		 869static int mmc_set_capacity(struct mmc *mmc, int part_num)
870{
871 switch (part_num) {
872 case 0:
873 mmc->capacity = mmc->capacity_user;
874 break;
875 case 1:
876 case 2:
877 mmc->capacity = mmc->capacity_boot;
878 break;
879 case 3:
880 mmc->capacity = mmc->capacity_rpmb;
881 break;
882 case 4:
883 case 5:
884 case 6:
885 case 7:
886 mmc->capacity = mmc->capacity_gp[part_num - 4];
887 break;
888 default:
889 return -1;
890 }
891
c40fdca6 892 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 893
894 return 0;
895}
896
f99c2efe 897#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
01298da3
JJH		 898static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
899{
900 int forbidden = 0;
901 bool change = false;
902
903 if (part_num & PART_ACCESS_MASK)
904 forbidden = MMC_CAP(MMC_HS_200);
905
906 if (MMC_CAP(mmc->selected_mode) & forbidden) {
907 debug("selected mode (%s) is forbidden for part %d\n",
908 mmc_mode_name(mmc->selected_mode), part_num);
909 change = true;
910 } else if (mmc->selected_mode != mmc->best_mode) {
911 debug("selected mode is not optimal\n");
912 change = true;
913 }
914
915 if (change)
916 return mmc_select_mode_and_width(mmc,
917 mmc->card_caps & ~forbidden);
918
919 return 0;
920}
f99c2efe
JJH		 921#else
922static inline int mmc_boot_part_access_chk(struct mmc *mmc,
923 unsigned int part_num)
924{
925 return 0;
926}
927#endif
01298da3 928
7dba0b93 929int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 930{
f866a46d 931 int ret;
bc897b1d 932
01298da3
JJH		 933 ret = mmc_boot_part_access_chk(mmc, part_num);
934 if (ret)
935 return ret;
936
f866a46d
SW		 937 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
938 (mmc->part_config & ~PART_ACCESS_MASK)
939 | (part_num & PART_ACCESS_MASK));
f866a46d 940
6dc93e70
PB		 941 /*
942 * Set the capacity if the switch succeeded or was intended
943 * to return to representing the raw device.
944 */
873cc1d7 945 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 946 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 947 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 948 }
6dc93e70
PB		 949
950 return ret;
bc897b1d
LW		 951}
952
cf17789e 953#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
ac9da0e0
DSC		 954int mmc_hwpart_config(struct mmc *mmc,
955 const struct mmc_hwpart_conf *conf,
956 enum mmc_hwpart_conf_mode mode)
957{
958 u8 part_attrs = 0;
959 u32 enh_size_mult;
960 u32 enh_start_addr;
961 u32 gp_size_mult[4];
962 u32 max_enh_size_mult;
963 u32 tot_enh_size_mult = 0;
8dda5b0e 964 u8 wr_rel_set;
ac9da0e0
DSC		 965 int i, pidx, err;
966 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
967
968 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
969 return -EINVAL;
970
971 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
d8e3d420 972 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
ac9da0e0
DSC		 973 return -EMEDIUMTYPE;
974 }
975
976 if (!(mmc->part_support & PART_SUPPORT)) {
d8e3d420 977 pr_err("Card does not support partitioning\n");
ac9da0e0
DSC		 978 return -EMEDIUMTYPE;
979 }
980
981 if (!mmc->hc_wp_grp_size) {
d8e3d420 982 pr_err("Card does not define HC WP group size\n");
ac9da0e0
DSC		 983 return -EMEDIUMTYPE;
984 }
985
986 /* check partition alignment and total enhanced size */
987 if (conf->user.enh_size) {
988 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
989 conf->user.enh_start % mmc->hc_wp_grp_size) {
d8e3d420 990 pr_err("User data enhanced area not HC WP group "
ac9da0e0
DSC		 991 "size aligned\n");
992 return -EINVAL;
993 }
994 part_attrs |= EXT_CSD_ENH_USR;
995 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
996 if (mmc->high_capacity) {
997 enh_start_addr = conf->user.enh_start;
998 } else {
999 enh_start_addr = (conf->user.enh_start << 9);
1000 }
1001 } else {
1002 enh_size_mult = 0;
1003 enh_start_addr = 0;
1004 }
1005 tot_enh_size_mult += enh_size_mult;
1006
1007 for (pidx = 0; pidx < 4; pidx++) {
1008 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
d8e3d420 1009 pr_err("GP%i partition not HC WP group size "
ac9da0e0
DSC		 1010 "aligned\n", pidx+1);
1011 return -EINVAL;
1012 }
1013 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1014 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1015 part_attrs |= EXT_CSD_ENH_GP(pidx);
1016 tot_enh_size_mult += gp_size_mult[pidx];
1017 }
1018 }
1019
1020 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
d8e3d420 1021 pr_err("Card does not support enhanced attribute\n");
ac9da0e0
DSC		 1022 return -EMEDIUMTYPE;
1023 }
1024
1025 err = mmc_send_ext_csd(mmc, ext_csd);
1026 if (err)
1027 return err;
1028
1029 max_enh_size_mult =
1030 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1031 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1032 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1033 if (tot_enh_size_mult > max_enh_size_mult) {
d8e3d420 1034 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
ac9da0e0
DSC		 1035 tot_enh_size_mult, max_enh_size_mult);
1036 return -EMEDIUMTYPE;
1037 }
1038
8dda5b0e
DSC		 1039 /* The default value of EXT_CSD_WR_REL_SET is device
1040 * dependent, the values can only be changed if the
1041 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1042 * changed only once and before partitioning is completed. */
1043 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1044 if (conf->user.wr_rel_change) {
1045 if (conf->user.wr_rel_set)
1046 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1047 else
1048 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1049 }
1050 for (pidx = 0; pidx < 4; pidx++) {
1051 if (conf->gp_part[pidx].wr_rel_change) {
1052 if (conf->gp_part[pidx].wr_rel_set)
1053 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1054 else
1055 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1056 }
1057 }
1058
1059 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1060 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1061 puts("Card does not support host controlled partition write "
1062 "reliability settings\n");
1063 return -EMEDIUMTYPE;
1064 }
1065
ac9da0e0
DSC		 1066 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1067 EXT_CSD_PARTITION_SETTING_COMPLETED) {
d8e3d420 1068 pr_err("Card already partitioned\n");
ac9da0e0
DSC		 1069 return -EPERM;
1070 }
1071
1072 if (mode == MMC_HWPART_CONF_CHECK)
1073 return 0;
1074
1075 /* Partitioning requires high-capacity size definitions */
1076 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1077 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1078 EXT_CSD_ERASE_GROUP_DEF, 1);
1079
1080 if (err)
1081 return err;
1082
1083 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1084
1085 /* update erase group size to be high-capacity */
1086 mmc->erase_grp_size =
1087 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1088
1089 }
1090
1091 /* all OK, write the configuration */
1092 for (i = 0; i < 4; i++) {
1093 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1094 EXT_CSD_ENH_START_ADDR+i,
1095 (enh_start_addr >> (i*8)) & 0xFF);
1096 if (err)
1097 return err;
1098 }
1099 for (i = 0; i < 3; i++) {
1100 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1101 EXT_CSD_ENH_SIZE_MULT+i,
1102 (enh_size_mult >> (i*8)) & 0xFF);
1103 if (err)
1104 return err;
1105 }
1106 for (pidx = 0; pidx < 4; pidx++) {
1107 for (i = 0; i < 3; i++) {
1108 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1109 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1110 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1111 if (err)
1112 return err;
1113 }
1114 }
1115 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1116 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1117 if (err)
1118 return err;
1119
1120 if (mode == MMC_HWPART_CONF_SET)
1121 return 0;
1122
8dda5b0e
DSC		 1123 /* The WR_REL_SET is a write-once register but shall be
1124 * written before setting PART_SETTING_COMPLETED. As it is
1125 * write-once we can only write it when completing the
1126 * partitioning. */
1127 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1128 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1129 EXT_CSD_WR_REL_SET, wr_rel_set);
1130 if (err)
1131 return err;
1132 }
1133
ac9da0e0
DSC		 1134 /* Setting PART_SETTING_COMPLETED confirms the partition
1135 * configuration but it only becomes effective after power
1136 * cycle, so we do not adjust the partition related settings
1137 * in the mmc struct. */
1138
1139 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1140 EXT_CSD_PARTITION_SETTING,
1141 EXT_CSD_PARTITION_SETTING_COMPLETED);
1142 if (err)
1143 return err;
1144
1145 return 0;
1146}
cf17789e 1147#endif
ac9da0e0 1148
e7881d85 1149#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1150int mmc_getcd(struct mmc *mmc)
1151{
1152 int cd;
1153
1154 cd = board_mmc_getcd(mmc);
1155
d4e1da4e 1156 if (cd < 0) {
93bfd616
PA		 1157 if (mmc->cfg->ops->getcd)
1158 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1159 else
1160 cd = 1;
1161 }
48972d90
TR		 1162
1163 return cd;
1164}
8ca51e51 1165#endif
48972d90 1166
fdbb873e 1167static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1168{
1169 struct mmc_cmd cmd;
1170 struct mmc_data data;
1171
1172 /* Switch the frequency */
1173 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1174 cmd.resp_type = MMC_RSP_R1;
1175 cmd.cmdarg = (mode << 31) | 0xffffff;
1176 cmd.cmdarg &= ~(0xf << (group * 4));
1177 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1178
1179 data.dest = (char *)resp;
1180 data.blocksize = 64;
1181 data.blocks = 1;
1182 data.flags = MMC_DATA_READ;
1183
1184 return mmc_send_cmd(mmc, &cmd, &data);
1185}
1186
1187
d0c221fe 1188static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1189{
1190 int err;
1191 struct mmc_cmd cmd;
18e7c8f6
SM		 1192 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1193 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1194 struct mmc_data data;
1195 int timeout;
f99c2efe 1196#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1197 u32 sd3_bus_mode;
f99c2efe 1198#endif
272cc70b 1199
00e446fa 1200 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
272cc70b 1201
d52ebf10
TC		 1202 if (mmc_host_is_spi(mmc))
1203 return 0;
1204
272cc70b
AF		 1205 /* Read the SCR to find out if this card supports higher speeds */
1206 cmd.cmdidx = MMC_CMD_APP_CMD;
1207 cmd.resp_type = MMC_RSP_R1;
1208 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1209
1210 err = mmc_send_cmd(mmc, &cmd, NULL);
1211
1212 if (err)
1213 return err;
1214
1215 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1216 cmd.resp_type = MMC_RSP_R1;
1217 cmd.cmdarg = 0;
272cc70b
AF		 1218
1219 timeout = 3;
1220
1221retry_scr:
f781dd38 1222 data.dest = (char *)scr;
272cc70b
AF		 1223 data.blocksize = 8;
1224 data.blocks = 1;
1225 data.flags = MMC_DATA_READ;
1226
1227 err = mmc_send_cmd(mmc, &cmd, &data);
1228
1229 if (err) {
1230 if (timeout--)
1231 goto retry_scr;
1232
1233 return err;
1234 }
1235
4e3d89ba
YK		 1236 mmc->scr[0] = __be32_to_cpu(scr[0]);
1237 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1238
1239 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1240 case 0:
1241 mmc->version = SD_VERSION_1_0;
1242 break;
1243 case 1:
1244 mmc->version = SD_VERSION_1_10;
1245 break;
1246 case 2:
1247 mmc->version = SD_VERSION_2;
1248 if ((mmc->scr[0] >> 15) & 0x1)
1249 mmc->version = SD_VERSION_3;
1250 break;
1251 default:
1252 mmc->version = SD_VERSION_1_0;
1253 break;
272cc70b
AF		 1254 }
1255
b44c7083
AS		 1256 if (mmc->scr[0] & SD_DATA_4BIT)
1257 mmc->card_caps |= MMC_MODE_4BIT;
1258
272cc70b
AF		 1259 /* Version 1.0 doesn't support switching */
1260 if (mmc->version == SD_VERSION_1_0)
1261 return 0;
1262
1263 timeout = 4;
1264 while (timeout--) {
1265 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1266 (u8 *)switch_status);
272cc70b
AF		 1267
1268 if (err)
1269 return err;
1270
1271 /* The high-speed function is busy. Try again */
4e3d89ba 1272 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1273 break;
1274 }
1275
272cc70b 1276 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1277 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1278 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1279
f99c2efe 1280#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1281 /* Version before 3.0 don't support UHS modes */
1282 if (mmc->version < SD_VERSION_3)
1283 return 0;
1284
1285 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1286 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1287 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1288 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1289 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1290 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1291 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1292 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1293 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1294 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1295 mmc->card_caps |= MMC_CAP(UHS_DDR50);
f99c2efe 1296#endif
c10b85d6 1297
d0c221fe
JJH		 1298 return 0;
1299}
1300
1301static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1302{
1303 int err;
1304
1305 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1306 int speed;
2c3fbf4c 1307
c10b85d6
JJH		 1308 switch (mode) {
1309 case SD_LEGACY:
1310 case UHS_SDR12:
1311 speed = UHS_SDR12_BUS_SPEED;
1312 break;
1313 case SD_HS:
1314 case UHS_SDR25:
1315 speed = UHS_SDR25_BUS_SPEED;
1316 break;
1317 case UHS_SDR50:
1318 speed = UHS_SDR50_BUS_SPEED;
1319 break;
1320 case UHS_DDR50:
1321 speed = UHS_DDR50_BUS_SPEED;
1322 break;
1323 case UHS_SDR104:
1324 speed = UHS_SDR104_BUS_SPEED;
1325 break;
1326 default:
1327 return -EINVAL;
1328 }
1329
1330 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1331 if (err)
1332 return err;
1333
c10b85d6 1334 if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
d0c221fe 1335 return -ENOTSUPP;
272cc70b 1336
d0c221fe
JJH		 1337 return 0;
1338}
1339
1340int sd_select_bus_width(struct mmc *mmc, int w)
1341{
1342 int err;
1343 struct mmc_cmd cmd;
1344
1345 if ((w != 4) && (w != 1))
1346 return -EINVAL;
1347
1348 cmd.cmdidx = MMC_CMD_APP_CMD;
1349 cmd.resp_type = MMC_RSP_R1;
1350 cmd.cmdarg = mmc->rca << 16;
1351
1352 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1353 if (err)
1354 return err;
1355
d0c221fe
JJH		 1356 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1357 cmd.resp_type = MMC_RSP_R1;
1358 if (w == 4)
1359 cmd.cmdarg = 2;
1360 else if (w == 1)
1361 cmd.cmdarg = 0;
1362 err = mmc_send_cmd(mmc, &cmd, NULL);
1363 if (err)
1364 return err;
272cc70b
AF		 1365
1366 return 0;
1367}
1368
3697e599
PF		 1369static int sd_read_ssr(struct mmc *mmc)
1370{
1371 int err, i;
1372 struct mmc_cmd cmd;
1373 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1374 struct mmc_data data;
1375 int timeout = 3;
1376 unsigned int au, eo, et, es;
1377
1378 cmd.cmdidx = MMC_CMD_APP_CMD;
1379 cmd.resp_type = MMC_RSP_R1;
1380 cmd.cmdarg = mmc->rca << 16;
1381
1382 err = mmc_send_cmd(mmc, &cmd, NULL);
1383 if (err)
1384 return err;
1385
1386 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1387 cmd.resp_type = MMC_RSP_R1;
1388 cmd.cmdarg = 0;
1389
1390retry_ssr:
1391 data.dest = (char *)ssr;
1392 data.blocksize = 64;
1393 data.blocks = 1;
1394 data.flags = MMC_DATA_READ;
1395
1396 err = mmc_send_cmd(mmc, &cmd, &data);
1397 if (err) {
1398 if (timeout--)
1399 goto retry_ssr;
1400
1401 return err;
1402 }
1403
1404 for (i = 0; i < 16; i++)
1405 ssr[i] = be32_to_cpu(ssr[i]);
1406
1407 au = (ssr[2] >> 12) & 0xF;
1408 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1409 mmc->ssr.au = sd_au_size[au];
1410 es = (ssr[3] >> 24) & 0xFF;
1411 es |= (ssr[2] & 0xFF) << 8;
1412 et = (ssr[3] >> 18) & 0x3F;
1413 if (es && et) {
1414 eo = (ssr[3] >> 16) & 0x3;
1415 mmc->ssr.erase_timeout = (et * 1000) / es;
1416 mmc->ssr.erase_offset = eo * 1000;
1417 }
1418 } else {
1419 debug("Invalid Allocation Unit Size.\n");
1420 }
1421
1422 return 0;
1423}
1424
272cc70b
AF		 1425/* frequency bases */
1426/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1427static const int fbase[] = {
272cc70b
AF		 1428 10000,
1429 100000,
1430 1000000,
1431 10000000,
1432};
1433
1434/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1435 * to platforms without floating point.
1436 */
61fe076f 1437static const u8 multipliers[] = {
272cc70b
AF		 1438 0, /* reserved */
1439 10,
1440 12,
1441 13,
1442 15,
1443 20,
1444 25,
1445 30,
1446 35,
1447 40,
1448 45,
1449 50,
1450 55,
1451 60,
1452 70,
1453 80,
1454};
1455
d0c221fe
JJH		 1456static inline int bus_width(uint cap)
1457{
1458 if (cap == MMC_MODE_8BIT)
1459 return 8;
1460 if (cap == MMC_MODE_4BIT)
1461 return 4;
1462 if (cap == MMC_MODE_1BIT)
1463 return 1;
d8e3d420 1464 pr_warn("invalid bus witdh capability 0x%x\n", cap);
d0c221fe
JJH		 1465 return 0;
1466}
1467
e7881d85 1468#if !CONFIG_IS_ENABLED(DM_MMC)
f99c2efe 1469#ifdef MMC_SUPPORTS_TUNING
ec841209
KVA		 1470static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1471{
1472 return -ENOTSUPP;
1473}
f99c2efe 1474#endif
ec841209 1475
318a7a57
JJH		 1476static void mmc_send_init_stream(struct mmc *mmc)
1477{
1478}
1479
2a4d212f 1480static int mmc_set_ios(struct mmc *mmc)
272cc70b 1481{
2a4d212f
KVA		 1482 int ret = 0;
1483
93bfd616 1484 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1485 ret = mmc->cfg->ops->set_ios(mmc);
1486
1487 return ret;
272cc70b 1488}
8ca51e51 1489#endif
272cc70b 1490
35f67820 1491int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1492{
93bfd616
PA		 1493 if (clock > mmc->cfg->f_max)
1494 clock = mmc->cfg->f_max;
272cc70b 1495
93bfd616
PA		 1496 if (clock < mmc->cfg->f_min)
1497 clock = mmc->cfg->f_min;
272cc70b
AF		 1498
1499 mmc->clock = clock;
35f67820 1500 mmc->clk_disable = disable;
272cc70b 1501
2a4d212f 1502 return mmc_set_ios(mmc);
272cc70b
AF		 1503}
1504
2a4d212f 1505static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1506{
1507 mmc->bus_width = width;
1508
2a4d212f 1509 return mmc_set_ios(mmc);
272cc70b
AF		 1510}
1511
4c9d2aaa
JJH		 1512#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1513/*
1514 * helper function to display the capabilities in a human
1515 * friendly manner. The capabilities include bus width and
1516 * supported modes.
1517 */
1518void mmc_dump_capabilities(const char *text, uint caps)
1519{
1520 enum bus_mode mode;
1521
1522 printf("%s: widths [", text);
1523 if (caps & MMC_MODE_8BIT)
1524 printf("8, ");
1525 if (caps & MMC_MODE_4BIT)
1526 printf("4, ");
d0c221fe
JJH		 1527 if (caps & MMC_MODE_1BIT)
1528 printf("1, ");
1529 printf("\b\b] modes [");
4c9d2aaa
JJH		 1530 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1531 if (MMC_CAP(mode) & caps)
1532 printf("%s, ", mmc_mode_name(mode));
1533 printf("\b\b]\n");
1534}
1535#endif
1536
d0c221fe
JJH		 1537struct mode_width_tuning {
1538 enum bus_mode mode;
1539 uint widths;
f99c2efe 1540#ifdef MMC_SUPPORTS_TUNING
634d4849 1541 uint tuning;
f99c2efe 1542#endif
d0c221fe
JJH		 1543};
1544
f99c2efe 1545#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1546int mmc_voltage_to_mv(enum mmc_voltage voltage)
1547{
1548 switch (voltage) {
1549 case MMC_SIGNAL_VOLTAGE_000: return 0;
1550 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1551 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1552 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1553 }
1554 return -EINVAL;
1555}
1556
aff5d3c8
KVA		 1557static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1558{
bc1e3272
JJH		 1559 int err;
1560
1561 if (mmc->signal_voltage == signal_voltage)
1562 return 0;
1563
aff5d3c8 1564 mmc->signal_voltage = signal_voltage;
bc1e3272
JJH		 1565 err = mmc_set_ios(mmc);
1566 if (err)
1567 debug("unable to set voltage (err %d)\n", err);
1568
1569 return err;
aff5d3c8 1570}
f99c2efe
JJH		 1571#else
1572static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1573{
1574 return 0;
1575}
1576#endif
aff5d3c8 1577
d0c221fe 1578static const struct mode_width_tuning sd_modes_by_pref[] = {
f99c2efe
JJH		 1579#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1580#ifdef MMC_SUPPORTS_TUNING
c10b85d6
JJH		 1581 {
1582 .mode = UHS_SDR104,
1583 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1584 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1585 },
f99c2efe 1586#endif
c10b85d6
JJH		 1587 {
1588 .mode = UHS_SDR50,
1589 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1590 },
1591 {
1592 .mode = UHS_DDR50,
1593 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1594 },
1595 {
1596 .mode = UHS_SDR25,
1597 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1598 },
f99c2efe 1599#endif
d0c221fe
JJH		 1600 {
1601 .mode = SD_HS,
1602 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1603 },
f99c2efe 1604#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1605 {
1606 .mode = UHS_SDR12,
1607 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1608 },
f99c2efe 1609#endif
d0c221fe
JJH		 1610 {
1611 .mode = SD_LEGACY,
1612 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1613 }
1614};
1615
1616#define for_each_sd_mode_by_pref(caps, mwt) \
1617 for (mwt = sd_modes_by_pref;\
1618 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1619 mwt++) \
1620 if (caps & MMC_CAP(mwt->mode))
1621
01298da3 1622static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1623{
1624 int err;
d0c221fe
JJH		 1625 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1626 const struct mode_width_tuning *mwt;
f99c2efe 1627#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1628 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
f99c2efe
JJH		 1629#else
1630 bool uhs_en = false;
1631#endif
c10b85d6
JJH		 1632 uint caps;
1633
52d241df
JJH		 1634#ifdef DEBUG
1635 mmc_dump_capabilities("sd card", card_caps);
1da8eb59 1636 mmc_dump_capabilities("host", mmc->host_caps);
52d241df 1637#endif
8ac8a263 1638
8ac8a263 1639 /* Restrict card's capabilities by what the host can do */
1da8eb59 1640 caps = card_caps & mmc->host_caps;
d0c221fe 1641
c10b85d6
JJH		 1642 if (!uhs_en)
1643 caps &= ~UHS_CAPS;
1644
1645 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1646 uint *w;
1647
1648 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1649 if (*w & caps & mwt->widths) {
d0c221fe
JJH		 1650 debug("trying mode %s width %d (at %d MHz)\n",
1651 mmc_mode_name(mwt->mode),
1652 bus_width(*w),
1653 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1654
1655 /* configure the bus width (card + host) */
1656 err = sd_select_bus_width(mmc, bus_width(*w));
1657 if (err)
1658 goto error;
1659 mmc_set_bus_width(mmc, bus_width(*w));
1660
1661 /* configure the bus mode (card) */
1662 err = sd_set_card_speed(mmc, mwt->mode);
1663 if (err)
1664 goto error;
1665
1666 /* configure the bus mode (host) */
1667 mmc_select_mode(mmc, mwt->mode);
35f67820 1668 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe 1669
f99c2efe 1670#ifdef MMC_SUPPORTS_TUNING
c10b85d6
JJH		 1671 /* execute tuning if needed */
1672 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1673 err = mmc_execute_tuning(mmc,
1674 mwt->tuning);
1675 if (err) {
1676 debug("tuning failed\n");
1677 goto error;
1678 }
1679 }
f99c2efe 1680#endif
c10b85d6 1681
d0c221fe
JJH		 1682 err = sd_read_ssr(mmc);
1683 if (!err)
1684 return 0;
1685
d8e3d420 1686 pr_warn("bad ssr\n");
d0c221fe
JJH		 1687
1688error:
1689 /* revert to a safer bus speed */
1690 mmc_select_mode(mmc, SD_LEGACY);
35f67820 1691 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe
JJH		 1692 }
1693 }
8ac8a263
JJH		 1694 }
1695
d0c221fe
JJH		 1696 printf("unable to select a mode\n");
1697 return -ENOTSUPP;
8ac8a263
JJH		 1698}
1699
7382e691
JJH		 1700/*
1701 * read the compare the part of ext csd that is constant.
1702 * This can be used to check that the transfer is working
1703 * as expected.
1704 */
1705static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1706{
7382e691 1707 int err;
dfda9d88 1708 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1709 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1710
1de06b9f
JJH		 1711 if (mmc->version < MMC_VERSION_4)
1712 return 0;
1713
7382e691
JJH		 1714 err = mmc_send_ext_csd(mmc, test_csd);
1715 if (err)
1716 return err;
1717
1718 /* Only compare read only fields */
1719 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1720 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1721 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1722 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1723 ext_csd[EXT_CSD_REV]
1724 == test_csd[EXT_CSD_REV] &&
1725 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1726 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1727 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1728 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1729 return 0;
1730
1731 return -EBADMSG;
1732}
1733
f99c2efe 1734#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1735static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1736 uint32_t allowed_mask)
1737{
1738 u32 card_mask = 0;
1739
1740 switch (mode) {
1741 case MMC_HS_200:
1742 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
1743 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1744 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
1745 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1746 break;
1747 case MMC_DDR_52:
1748 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1749 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1750 MMC_SIGNAL_VOLTAGE_180;
1751 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1752 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1753 break;
1754 default:
1755 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1756 break;
1757 }
1758
1759 while (card_mask & allowed_mask) {
1760 enum mmc_voltage best_match;
1761
1762 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1763 if (!mmc_set_signal_voltage(mmc, best_match))
1764 return 0;
1765
1766 allowed_mask &= ~best_match;
1767 }
1768
1769 return -ENOTSUPP;
1770}
f99c2efe
JJH		 1771#else
1772static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1773 uint32_t allowed_mask)
1774{
1775 return 0;
1776}
1777#endif
bc1e3272 1778
3862b854 1779static const struct mode_width_tuning mmc_modes_by_pref[] = {
f99c2efe 1780#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
3862b854
JJH		 1781 {
1782 .mode = MMC_HS_200,
1783 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1784 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854 1785 },
f99c2efe 1786#endif
3862b854
JJH		 1787 {
1788 .mode = MMC_DDR_52,
1789 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1790 },
1791 {
1792 .mode = MMC_HS_52,
1793 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1794 },
1795 {
1796 .mode = MMC_HS,
1797 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1798 },
1799 {
1800 .mode = MMC_LEGACY,
1801 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1802 }
1803};
1804
1805#define for_each_mmc_mode_by_pref(caps, mwt) \
1806 for (mwt = mmc_modes_by_pref;\
1807 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1808 mwt++) \
1809 if (caps & MMC_CAP(mwt->mode))
1810
1811static const struct ext_csd_bus_width {
1812 uint cap;
1813 bool is_ddr;
1814 uint ext_csd_bits;
1815} ext_csd_bus_width[] = {
1816 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1817 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1818 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1819 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1820 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1821};
1822
1823#define for_each_supported_width(caps, ddr, ecbv) \
1824 for (ecbv = ext_csd_bus_width;\
1825 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1826 ecbv++) \
1827 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1828
01298da3 1829static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 1830{
8ac8a263 1831 int err;
3862b854
JJH		 1832 const struct mode_width_tuning *mwt;
1833 const struct ext_csd_bus_width *ecbw;
8ac8a263 1834
52d241df
JJH		 1835#ifdef DEBUG
1836 mmc_dump_capabilities("mmc", card_caps);
1da8eb59 1837 mmc_dump_capabilities("host", mmc->host_caps);
52d241df
JJH		 1838#endif
1839
8ac8a263 1840 /* Restrict card's capabilities by what the host can do */
1da8eb59 1841 card_caps &= mmc->host_caps;
8ac8a263
JJH		 1842
1843 /* Only version 4 of MMC supports wider bus widths */
1844 if (mmc->version < MMC_VERSION_4)
1845 return 0;
1846
dfda9d88
JJH		 1847 if (!mmc->ext_csd) {
1848 debug("No ext_csd found!\n"); /* this should enver happen */
1849 return -ENOTSUPP;
1850 }
1851
01298da3
JJH		 1852 mmc_set_clock(mmc, mmc->legacy_speed, false);
1853
1854 for_each_mmc_mode_by_pref(card_caps, mwt) {
1855 for_each_supported_width(card_caps & mwt->widths,
3862b854 1856 mmc_is_mode_ddr(mwt->mode), ecbw) {
bc1e3272 1857 enum mmc_voltage old_voltage;
3862b854
JJH		 1858 debug("trying mode %s width %d (at %d MHz)\n",
1859 mmc_mode_name(mwt->mode),
1860 bus_width(ecbw->cap),
1861 mmc_mode2freq(mmc, mwt->mode) / 1000000);
bc1e3272
JJH		 1862 old_voltage = mmc->signal_voltage;
1863 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1864 MMC_ALL_SIGNAL_VOLTAGE);
1865 if (err)
1866 continue;
1867
3862b854
JJH		 1868 /* configure the bus width (card + host) */
1869 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1870 EXT_CSD_BUS_WIDTH,
1871 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1872 if (err)
1873 goto error;
1874 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 1875
3862b854
JJH		 1876 /* configure the bus speed (card) */
1877 err = mmc_set_card_speed(mmc, mwt->mode);
1878 if (err)
1879 goto error;
1880
1881 /*
1882 * configure the bus width AND the ddr mode (card)
1883 * The host side will be taken care of in the next step
1884 */
1885 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1886 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1887 EXT_CSD_BUS_WIDTH,
1888 ecbw->ext_csd_bits);
1889 if (err)
1890 goto error;
1891 }
8ac8a263 1892
3862b854
JJH		 1893 /* configure the bus mode (host) */
1894 mmc_select_mode(mmc, mwt->mode);
35f67820 1895 mmc_set_clock(mmc, mmc->tran_speed, false);
f99c2efe 1896#ifdef MMC_SUPPORTS_TUNING
8ac8a263 1897
634d4849
KVA		 1898 /* execute tuning if needed */
1899 if (mwt->tuning) {
1900 err = mmc_execute_tuning(mmc, mwt->tuning);
1901 if (err) {
1902 debug("tuning failed\n");
1903 goto error;
1904 }
1905 }
f99c2efe 1906#endif
634d4849 1907
3862b854
JJH		 1908 /* do a transfer to check the configuration */
1909 err = mmc_read_and_compare_ext_csd(mmc);
1910 if (!err)
1911 return 0;
1912error:
bc1e3272 1913 mmc_set_signal_voltage(mmc, old_voltage);
3862b854
JJH		 1914 /* if an error occured, revert to a safer bus mode */
1915 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1916 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1917 mmc_select_mode(mmc, MMC_LEGACY);
1918 mmc_set_bus_width(mmc, 1);
1919 }
8ac8a263
JJH		 1920 }
1921
d8e3d420 1922 pr_err("unable to select a mode\n");
8ac8a263 1923
3862b854 1924 return -ENOTSUPP;
8ac8a263
JJH		 1925}
1926
dfda9d88 1927static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 1928{
1929 int err, i;
1930 u64 capacity;
1931 bool has_parts = false;
1932 bool part_completed;
f7d5dffc 1933 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
c744b6f6
JJH		 1934
1935 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1936 return 0;
1937
1938 /* check ext_csd version and capacity */
1939 err = mmc_send_ext_csd(mmc, ext_csd);
1940 if (err)
f7d5dffc
JJH		 1941 goto error;
1942
1943 /* store the ext csd for future reference */
1944 if (!mmc->ext_csd)
1945 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
1946 if (!mmc->ext_csd)
1947 return -ENOMEM;
1948 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
1949
c744b6f6
JJH		 1950 if (ext_csd[EXT_CSD_REV] >= 2) {
1951 /*
1952 * According to the JEDEC Standard, the value of
1953 * ext_csd's capacity is valid if the value is more
1954 * than 2GB
1955 */
1956 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1957 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1958 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1959 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1960 capacity *= MMC_MAX_BLOCK_LEN;
1961 if ((capacity >> 20) > 2 * 1024)
1962 mmc->capacity_user = capacity;
1963 }
1964
1965 switch (ext_csd[EXT_CSD_REV]) {
1966 case 1:
1967 mmc->version = MMC_VERSION_4_1;
1968 break;
1969 case 2:
1970 mmc->version = MMC_VERSION_4_2;
1971 break;
1972 case 3:
1973 mmc->version = MMC_VERSION_4_3;
1974 break;
1975 case 5:
1976 mmc->version = MMC_VERSION_4_41;
1977 break;
1978 case 6:
1979 mmc->version = MMC_VERSION_4_5;
1980 break;
1981 case 7:
1982 mmc->version = MMC_VERSION_5_0;
1983 break;
1984 case 8:
1985 mmc->version = MMC_VERSION_5_1;
1986 break;
1987 }
1988
1989 /* The partition data may be non-zero but it is only
1990 * effective if PARTITION_SETTING_COMPLETED is set in
1991 * EXT_CSD, so ignore any data if this bit is not set,
1992 * except for enabling the high-capacity group size
1993 * definition (see below).
1994 */
1995 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1996 EXT_CSD_PARTITION_SETTING_COMPLETED);
1997
1998 /* store the partition info of emmc */
1999 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2000 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2001 ext_csd[EXT_CSD_BOOT_MULT])
2002 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2003 if (part_completed &&
2004 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2005 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2006
2007 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2008
2009 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2010
2011 for (i = 0; i < 4; i++) {
2012 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2013 uint mult = (ext_csd[idx + 2] << 16) +
2014 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2015 if (mult)
2016 has_parts = true;
2017 if (!part_completed)
2018 continue;
2019 mmc->capacity_gp[i] = mult;
2020 mmc->capacity_gp[i] *=
2021 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2022 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2023 mmc->capacity_gp[i] <<= 19;
2024 }
2025
2026 if (part_completed) {
2027 mmc->enh_user_size =
2028 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2029 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2030 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2031 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2032 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2033 mmc->enh_user_size <<= 19;
2034 mmc->enh_user_start =
2035 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2036 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2037 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2038 ext_csd[EXT_CSD_ENH_START_ADDR];
2039 if (mmc->high_capacity)
2040 mmc->enh_user_start <<= 9;
2041 }
2042
2043 /*
2044 * Host needs to enable ERASE_GRP_DEF bit if device is
2045 * partitioned. This bit will be lost every time after a reset
2046 * or power off. This will affect erase size.
2047 */
2048 if (part_completed)
2049 has_parts = true;
2050 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2051 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2052 has_parts = true;
2053 if (has_parts) {
2054 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2055 EXT_CSD_ERASE_GROUP_DEF, 1);
2056
2057 if (err)
f7d5dffc 2058 goto error;
c744b6f6
JJH		 2059
2060 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2061 }
2062
2063 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2064 /* Read out group size from ext_csd */
2065 mmc->erase_grp_size =
2066 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2067 /*
2068 * if high capacity and partition setting completed
2069 * SEC_COUNT is valid even if it is smaller than 2 GiB
2070 * JEDEC Standard JESD84-B45, 6.2.4
2071 */
2072 if (mmc->high_capacity && part_completed) {
2073 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2074 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2075 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2076 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2077 capacity *= MMC_MAX_BLOCK_LEN;
2078 mmc->capacity_user = capacity;
2079 }
2080 } else {
2081 /* Calculate the group size from the csd value. */
2082 int erase_gsz, erase_gmul;
2083
2084 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2085 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2086 mmc->erase_grp_size = (erase_gsz + 1)
2087 * (erase_gmul + 1);
2088 }
2089
2090 mmc->hc_wp_grp_size = 1024
2091 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2092 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2093
2094 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2095
2096 return 0;
f7d5dffc
JJH		 2097error:
2098 if (mmc->ext_csd) {
2099 free(mmc->ext_csd);
2100 mmc->ext_csd = NULL;
2101 }
2102 return err;
c744b6f6
JJH		 2103}
2104
fdbb873e 2105static int mmc_startup(struct mmc *mmc)
272cc70b 2106{
f866a46d 2107 int err, i;
272cc70b 2108 uint mult, freq;
c744b6f6 2109 u64 cmult, csize;
272cc70b 2110 struct mmc_cmd cmd;
c40fdca6 2111 struct blk_desc *bdesc;
272cc70b 2112
d52ebf10
TC		 2113#ifdef CONFIG_MMC_SPI_CRC_ON
2114 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2115 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2116 cmd.resp_type = MMC_RSP_R1;
2117 cmd.cmdarg = 1;
d52ebf10 2118 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 2119 if (err)
2120 return err;
2121 }
2122#endif
2123
272cc70b 2124 /* Put the Card in Identify Mode */
d52ebf10
TC		 2125 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2126 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 2127 cmd.resp_type = MMC_RSP_R2;
2128 cmd.cmdarg = 0;
272cc70b
AF		 2129
2130 err = mmc_send_cmd(mmc, &cmd, NULL);
2131
83dc4227
KVA		 2132#ifdef CONFIG_MMC_QUIRKS
2133 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2134 int retries = 4;
2135 /*
2136 * It has been seen that SEND_CID may fail on the first
2137 * attempt, let's try a few more time
2138 */
2139 do {
2140 err = mmc_send_cmd(mmc, &cmd, NULL);
2141 if (!err)
2142 break;
2143 } while (retries--);
2144 }
2145#endif
2146
272cc70b
AF		 2147 if (err)
2148 return err;
2149
2150 memcpy(mmc->cid, cmd.response, 16);
2151
2152 /*
2153 * For MMC cards, set the Relative Address.
2154 * For SD cards, get the Relatvie Address.
2155 * This also puts the cards into Standby State
2156 */
d52ebf10
TC		 2157 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2158 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2159 cmd.cmdarg = mmc->rca << 16;
2160 cmd.resp_type = MMC_RSP_R6;
272cc70b 2161
d52ebf10 2162 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2163
d52ebf10
TC		 2164 if (err)
2165 return err;
272cc70b 2166
d52ebf10
TC		 2167 if (IS_SD(mmc))
2168 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2169 }
272cc70b
AF		 2170
2171 /* Get the Card-Specific Data */
2172 cmd.cmdidx = MMC_CMD_SEND_CSD;
2173 cmd.resp_type = MMC_RSP_R2;
2174 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 2175
2176 err = mmc_send_cmd(mmc, &cmd, NULL);
2177
2178 if (err)
2179 return err;
2180
998be3dd
RV		 2181 mmc->csd[0] = cmd.response[0];
2182 mmc->csd[1] = cmd.response[1];
2183 mmc->csd[2] = cmd.response[2];
2184 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 2185
2186 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 2187 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 2188
2189 switch (version) {
53e8e40b
BM		 2190 case 0:
2191 mmc->version = MMC_VERSION_1_2;
2192 break;
2193 case 1:
2194 mmc->version = MMC_VERSION_1_4;
2195 break;
2196 case 2:
2197 mmc->version = MMC_VERSION_2_2;
2198 break;
2199 case 3:
2200 mmc->version = MMC_VERSION_3;
2201 break;
2202 case 4:
2203 mmc->version = MMC_VERSION_4;
2204 break;
2205 default:
2206 mmc->version = MMC_VERSION_1_2;
2207 break;
272cc70b
AF		 2208 }
2209 }
2210
2211 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 2212 freq = fbase[(cmd.response[0] & 0x7)];
2213 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 2214
35f9e196 2215 mmc->legacy_speed = freq * mult;
35f9e196 2216 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2217
ab71188c 2218 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2219 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 2220
2221 if (IS_SD(mmc))
2222 mmc->write_bl_len = mmc->read_bl_len;
2223 else
998be3dd 2224 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 2225
2226 if (mmc->high_capacity) {
2227 csize = (mmc->csd[1] & 0x3f) << 16
2228 | (mmc->csd[2] & 0xffff0000) >> 16;
2229 cmult = 8;
2230 } else {
2231 csize = (mmc->csd[1] & 0x3ff) << 2
2232 | (mmc->csd[2] & 0xc0000000) >> 30;
2233 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2234 }
2235
f866a46d
SW		 2236 mmc->capacity_user = (csize + 1) << (cmult + 2);
2237 mmc->capacity_user *= mmc->read_bl_len;
2238 mmc->capacity_boot = 0;
2239 mmc->capacity_rpmb = 0;
2240 for (i = 0; i < 4; i++)
2241 mmc->capacity_gp[i] = 0;
272cc70b 2242
8bfa195e
SG		 2243 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2244 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2245
8bfa195e
SG		 2246 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2247 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2248
ab71188c
MN		 2249 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2250 cmd.cmdidx = MMC_CMD_SET_DSR;
2251 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2252 cmd.resp_type = MMC_RSP_NONE;
2253 if (mmc_send_cmd(mmc, &cmd, NULL))
d8e3d420 2254 pr_warn("MMC: SET_DSR failed\n");
ab71188c
MN		 2255 }
2256
272cc70b 2257 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2258 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2259 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2260 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2261 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2262 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2263
d52ebf10
TC		 2264 if (err)
2265 return err;
2266 }
272cc70b 2267
e6f99a56
LW		 2268 /*
2269 * For SD, its erase group is always one sector
2270 */
2271 mmc->erase_grp_size = 1;
bc897b1d 2272 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2273
dfda9d88 2274 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2275 if (err)
2276 return err;
d23e2c09 2277
c40fdca6 2278 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2279 if (err)
2280 return err;
2281
01298da3
JJH		 2282 if (IS_SD(mmc)) {
2283 err = sd_get_capabilities(mmc);
2284 if (err)
2285 return err;
2286 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2287 } else {
2288 err = mmc_get_capabilities(mmc);
2289 if (err)
2290 return err;
2291 mmc_select_mode_and_width(mmc, mmc->card_caps);
2292 }
272cc70b
AF		 2293
2294 if (err)
2295 return err;
2296
01298da3 2297 mmc->best_mode = mmc->selected_mode;
ad5fd922 2298
5af8f45c
AG		 2299 /* Fix the block length for DDR mode */
2300 if (mmc->ddr_mode) {
2301 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2302 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2303 }
2304
272cc70b 2305 /* fill in device description */
c40fdca6
SG		 2306 bdesc = mmc_get_blk_desc(mmc);
2307 bdesc->lun = 0;
2308 bdesc->hwpart = 0;
2309 bdesc->type = 0;
2310 bdesc->blksz = mmc->read_bl_len;
2311 bdesc->log2blksz = LOG2(bdesc->blksz);
2312 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2313#if !defined(CONFIG_SPL_BUILD) || \
2314 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2315 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 2316 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2317 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2318 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2319 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2320 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2321 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2322 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2323 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2324 (mmc->cid[2] >> 16) & 0xf);
56196826 2325#else
c40fdca6
SG		 2326 bdesc->vendor[0] = 0;
2327 bdesc->product[0] = 0;
2328 bdesc->revision[0] = 0;
56196826 2329#endif
122efd43 2330#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
c40fdca6 2331 part_init(bdesc);
122efd43 2332#endif
272cc70b
AF		 2333
2334 return 0;
2335}
2336
fdbb873e 2337static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2338{
2339 struct mmc_cmd cmd;
2340 int err;
2341
2342 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2343 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2344 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2345 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2346
2347 err = mmc_send_cmd(mmc, &cmd, NULL);
2348
2349 if (err)
2350 return err;
2351
998be3dd 2352 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2353 return -EOPNOTSUPP;
272cc70b
AF		 2354 else
2355 mmc->version = SD_VERSION_2;
2356
2357 return 0;
2358}
2359
c4d660d4 2360#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2361/* board-specific MMC power initializations. */
2362__weak void board_mmc_power_init(void)
2363{
2364}
05cbeb7c 2365#endif
95de9ab2 2366
2051aefe
PF		 2367static int mmc_power_init(struct mmc *mmc)
2368{
c4d660d4 2369#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2370#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2371 int ret;
2372
2373 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2374 &mmc->vmmc_supply);
2375 if (ret)
288db7c7 2376 debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2377
06ec045f
JJH		 2378 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2379 &mmc->vqmmc_supply);
2380 if (ret)
2381 debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2382#endif
2383#else /* !CONFIG_DM_MMC */
2384 /*
2385 * Driver model should use a regulator, as above, rather than calling
2386 * out to board code.
2387 */
2388 board_mmc_power_init();
2389#endif
2390 return 0;
2391}
2392
2393/*
2394 * put the host in the initial state:
2395 * - turn on Vdd (card power supply)
2396 * - configure the bus width and clock to minimal values
2397 */
2398static void mmc_set_initial_state(struct mmc *mmc)
2399{
2400 int err;
2401
2402 /* First try to set 3.3V. If it fails set to 1.8V */
2403 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2404 if (err != 0)
2405 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2406 if (err != 0)
d8e3d420 2407 pr_warn("mmc: failed to set signal voltage\n");
fb7c3beb
KVA		 2408
2409 mmc_select_mode(mmc, MMC_LEGACY);
2410 mmc_set_bus_width(mmc, 1);
35f67820 2411 mmc_set_clock(mmc, 0, false);
fb7c3beb 2412}
06ec045f 2413
fb7c3beb
KVA		 2414static int mmc_power_on(struct mmc *mmc)
2415{
2416#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2417 if (mmc->vmmc_supply) {
fb7c3beb
KVA		 2418 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2419
06ec045f
JJH		 2420 if (ret) {
2421 puts("Error enabling VMMC supply\n");
2422 return ret;
2423 }
2051aefe 2424 }
05cbeb7c 2425#endif
fb7c3beb
KVA		 2426 return 0;
2427}
2428
2429static int mmc_power_off(struct mmc *mmc)
2430{
2e7410d7 2431 mmc_set_clock(mmc, 1, true);
fb7c3beb
KVA		 2432#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2433 if (mmc->vmmc_supply) {
2434 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2435
2436 if (ret) {
c10b85d6 2437 debug("Error disabling VMMC supply\n");
fb7c3beb
KVA		 2438 return ret;
2439 }
2440 }
2051aefe
PF		 2441#endif
2442 return 0;
2443}
2444
fb7c3beb
KVA		 2445static int mmc_power_cycle(struct mmc *mmc)
2446{
2447 int ret;
2448
2449 ret = mmc_power_off(mmc);
2450 if (ret)
2451 return ret;
2452 /*
2453 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2454 * to be on the safer side.
2455 */
2456 udelay(2000);
2457 return mmc_power_on(mmc);
2458}
2459
e9550449 2460int mmc_start_init(struct mmc *mmc)
272cc70b 2461{
8ca51e51 2462 bool no_card;
c10b85d6 2463 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2464 int err;
272cc70b 2465
1da8eb59
JJH		 2466 /*
2467 * all hosts are capable of 1 bit bus-width and able to use the legacy
2468 * timings.
2469 */
2470 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2471 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
04a2ea24 2472
ab769f22 2473 /* we pretend there's no card when init is NULL */
8ca51e51 2474 no_card = mmc_getcd(mmc) == 0;
e7881d85 2475#if !CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2476 no_card = no_card || (mmc->cfg->ops->init == NULL);
2477#endif
2478 if (no_card) {
48972d90 2479 mmc->has_init = 0;
56196826 2480#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 2481 printf("MMC: no card present\n");
56196826 2482#endif
915ffa52 2483 return -ENOMEDIUM;
48972d90
TR		 2484 }
2485
bc897b1d
LW		 2486 if (mmc->has_init)
2487 return 0;
2488
5a8dbdc6
YL		 2489#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2490 mmc_adapter_card_type_ident();
2491#endif
2051aefe
PF		 2492 err = mmc_power_init(mmc);
2493 if (err)
2494 return err;
95de9ab2 2495
83dc4227
KVA		 2496#ifdef CONFIG_MMC_QUIRKS
2497 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2498 MMC_QUIRK_RETRY_SEND_CID;
2499#endif
2500
04a2ea24
JJH		 2501 err = mmc_power_cycle(mmc);
2502 if (err) {
2503 /*
2504 * if power cycling is not supported, we should not try
2505 * to use the UHS modes, because we wouldn't be able to
2506 * recover from an error during the UHS initialization.
2507 */
2508 debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2509 uhs_en = false;
2510 mmc->host_caps &= ~UHS_CAPS;
2511 err = mmc_power_on(mmc);
2512 }
fb7c3beb
KVA		 2513 if (err)
2514 return err;
2515
e7881d85 2516#if CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2517 /* The device has already been probed ready for use */
2518#else
ab769f22 2519 /* made sure it's not NULL earlier */
93bfd616 2520 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 2521 if (err)
2522 return err;
8ca51e51 2523#endif
786e8f81 2524 mmc->ddr_mode = 0;
aff5d3c8 2525
c10b85d6 2526retry:
fb7c3beb 2527 mmc_set_initial_state(mmc);
318a7a57
JJH		 2528 mmc_send_init_stream(mmc);
2529
272cc70b
AF		 2530 /* Reset the Card */
2531 err = mmc_go_idle(mmc);
2532
2533 if (err)
2534 return err;
2535
bc897b1d 2536 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 2537 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2538
272cc70b 2539 /* Test for SD version 2 */
afd5932b 2540 err = mmc_send_if_cond(mmc);
272cc70b 2541
272cc70b 2542 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2543 err = sd_send_op_cond(mmc, uhs_en);
2544 if (err && uhs_en) {
2545 uhs_en = false;
2546 mmc_power_cycle(mmc);
2547 goto retry;
2548 }
272cc70b
AF		 2549
2550 /* If the command timed out, we check for an MMC card */
915ffa52 2551 if (err == -ETIMEDOUT) {
272cc70b
AF		 2552 err = mmc_send_op_cond(mmc);
2553
bd47c135 2554 if (err) {
56196826 2555#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 2556 pr_err("Card did not respond to voltage select!\n");
56196826 2557#endif
915ffa52 2558 return -EOPNOTSUPP;
272cc70b
AF		 2559 }
2560 }
2561
bd47c135 2562 if (!err)
e9550449
CLC		 2563 mmc->init_in_progress = 1;
2564
2565 return err;
2566}
2567
2568static int mmc_complete_init(struct mmc *mmc)
2569{
2570 int err = 0;
2571
bd47c135 2572 mmc->init_in_progress = 0;
e9550449
CLC		 2573 if (mmc->op_cond_pending)
2574 err = mmc_complete_op_cond(mmc);
2575
2576 if (!err)
2577 err = mmc_startup(mmc);
bc897b1d
LW		 2578 if (err)
2579 mmc->has_init = 0;
2580 else
2581 mmc->has_init = 1;
e9550449
CLC		 2582 return err;
2583}
2584
2585int mmc_init(struct mmc *mmc)
2586{
bd47c135 2587 int err = 0;
ce9eca94 2588 __maybe_unused unsigned start;
c4d660d4 2589#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 2590 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 2591
33fb211d
SG		 2592 upriv->mmc = mmc;
2593#endif
e9550449
CLC		 2594 if (mmc->has_init)
2595 return 0;
d803fea5
MZ		 2596
2597 start = get_timer(0);
2598
e9550449
CLC		 2599 if (!mmc->init_in_progress)
2600 err = mmc_start_init(mmc);
2601
bd47c135 2602 if (!err)
e9550449 2603 err = mmc_complete_init(mmc);
919b4858
JT		 2604 if (err)
2605 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2606
bc897b1d 2607 return err;
272cc70b
AF		 2608}
2609
ab71188c
MN		 2610int mmc_set_dsr(struct mmc *mmc, u16 val)
2611{
2612 mmc->dsr = val;
2613 return 0;
2614}
2615
cee9ab7c
JH		 2616/* CPU-specific MMC initializations */
2617__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 2618{
2619 return -1;
2620}
2621
cee9ab7c
JH		 2622/* board-specific MMC initializations. */
2623__weak int board_mmc_init(bd_t *bis)
2624{
2625 return -1;
2626}
272cc70b 2627
e9550449
CLC		 2628void mmc_set_preinit(struct mmc *mmc, int preinit)
2629{
2630 mmc->preinit = preinit;
2631}
2632
c4d660d4 2633#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
8e3332e2
SS		 2634static int mmc_probe(bd_t *bis)
2635{
2636 return 0;
2637}
c4d660d4 2638#elif CONFIG_IS_ENABLED(DM_MMC)
8e3332e2
SS		 2639static int mmc_probe(bd_t *bis)
2640{
4a1db6d8 2641 int ret, i;
8e3332e2 2642 struct uclass *uc;
4a1db6d8 2643 struct udevice *dev;
8e3332e2
SS		 2644
2645 ret = uclass_get(UCLASS_MMC, &uc);
2646 if (ret)
2647 return ret;
2648
4a1db6d8
SG		 2649 /*
2650 * Try to add them in sequence order. Really with driver model we
2651 * should allow holes, but the current MMC list does not allow that.
2652 * So if we request 0, 1, 3 we will get 0, 1, 2.
2653 */
2654 for (i = 0; ; i++) {
2655 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2656 if (ret == -ENODEV)
2657 break;
2658 }
2659 uclass_foreach_dev(dev, uc) {
2660 ret = device_probe(dev);
8e3332e2 2661 if (ret)
d8e3d420 2662 pr_err("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 2663 }
2664
2665 return 0;
2666}
2667#else
2668static int mmc_probe(bd_t *bis)
2669{
2670 if (board_mmc_init(bis) < 0)
2671 cpu_mmc_init(bis);
2672
2673 return 0;
2674}
2675#endif
e9550449 2676
272cc70b
AF		 2677int mmc_initialize(bd_t *bis)
2678{
1b26bab1 2679 static int initialized = 0;
8e3332e2 2680 int ret;
1b26bab1
DK		 2681 if (initialized) /* Avoid initializing mmc multiple times */
2682 return 0;
2683 initialized = 1;
2684
c4d660d4 2685#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 2686#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 2687 mmc_list_init();
b5b838f1 2688#endif
c40fdca6 2689#endif
8e3332e2
SS		 2690 ret = mmc_probe(bis);
2691 if (ret)
2692 return ret;
272cc70b 2693
bb0dc108 2694#ifndef CONFIG_SPL_BUILD
272cc70b 2695 print_mmc_devices(',');
bb0dc108 2696#endif
272cc70b 2697
c40fdca6 2698 mmc_do_preinit();
272cc70b
AF		 2699 return 0;
2700}
cd3d4880
TM		 2701
2702#ifdef CONFIG_CMD_BKOPS_ENABLE
2703int mmc_set_bkops_enable(struct mmc *mmc)
2704{
2705 int err;
2706 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2707
2708 err = mmc_send_ext_csd(mmc, ext_csd);
2709 if (err) {
2710 puts("Could not get ext_csd register values\n");
2711 return err;
2712 }
2713
2714 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2715 puts("Background operations not supported on device\n");
2716 return -EMEDIUMTYPE;
2717 }
2718
2719 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2720 puts("Background operations already enabled\n");
2721 return 0;
2722 }
2723
2724 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2725 if (err) {
2726 puts("Failed to enable manual background operations\n");
2727 return err;
2728 }
2729
2730 puts("Enabled manual background operations\n");
2731
2732 return 0;
2733}
2734#endif
"Das U-Boot" Source Tree