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Commit | Line | Data |
---|---|---|
272cc70b AF |
1 | /* |
2 | * Copyright 2008, Freescale Semiconductor, Inc | |
3 | * Andy Fleming | |
4 | * | |
5 | * Based vaguely on the Linux code | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
272cc70b AF |
8 | */ |
9 | ||
10 | #include <config.h> | |
11 | #include <common.h> | |
12 | #include <command.h> | |
d4622df3 | 13 | #include <errno.h> |
272cc70b AF |
14 | #include <mmc.h> |
15 | #include <part.h> | |
16 | #include <malloc.h> | |
17 | #include <linux/list.h> | |
9b1f942c | 18 | #include <div64.h> |
da61fa5f | 19 | #include "mmc_private.h" |
272cc70b AF |
20 | |
21 | static struct list_head mmc_devices; | |
22 | static int cur_dev_num = -1; | |
23 | ||
750121c3 | 24 | __weak int board_mmc_getwp(struct mmc *mmc) |
d23d8d7e NK |
25 | { |
26 | return -1; | |
27 | } | |
28 | ||
29 | int mmc_getwp(struct mmc *mmc) | |
30 | { | |
31 | int wp; | |
32 | ||
33 | wp = board_mmc_getwp(mmc); | |
34 | ||
d4e1da4e | 35 | if (wp < 0) { |
93bfd616 PA |
36 | if (mmc->cfg->ops->getwp) |
37 | wp = mmc->cfg->ops->getwp(mmc); | |
d4e1da4e PK |
38 | else |
39 | wp = 0; | |
40 | } | |
d23d8d7e NK |
41 | |
42 | return wp; | |
43 | } | |
44 | ||
cee9ab7c JH |
45 | __weak int board_mmc_getcd(struct mmc *mmc) |
46 | { | |
11fdade2 SB |
47 | return -1; |
48 | } | |
49 | ||
da61fa5f | 50 | int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
272cc70b | 51 | { |
5db2fe3a | 52 | int ret; |
8635ff9e | 53 | |
8635ff9e | 54 | #ifdef CONFIG_MMC_TRACE |
5db2fe3a RR |
55 | int i; |
56 | u8 *ptr; | |
57 | ||
58 | printf("CMD_SEND:%d\n", cmd->cmdidx); | |
59 | printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); | |
93bfd616 | 60 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a RR |
61 | switch (cmd->resp_type) { |
62 | case MMC_RSP_NONE: | |
63 | printf("\t\tMMC_RSP_NONE\n"); | |
64 | break; | |
65 | case MMC_RSP_R1: | |
66 | printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", | |
67 | cmd->response[0]); | |
68 | break; | |
69 | case MMC_RSP_R1b: | |
70 | printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", | |
71 | cmd->response[0]); | |
72 | break; | |
73 | case MMC_RSP_R2: | |
74 | printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", | |
75 | cmd->response[0]); | |
76 | printf("\t\t \t\t 0x%08X \n", | |
77 | cmd->response[1]); | |
78 | printf("\t\t \t\t 0x%08X \n", | |
79 | cmd->response[2]); | |
80 | printf("\t\t \t\t 0x%08X \n", | |
81 | cmd->response[3]); | |
82 | printf("\n"); | |
83 | printf("\t\t\t\t\tDUMPING DATA\n"); | |
84 | for (i = 0; i < 4; i++) { | |
85 | int j; | |
86 | printf("\t\t\t\t\t%03d - ", i*4); | |
146bec79 | 87 | ptr = (u8 *)&cmd->response[i]; |
5db2fe3a RR |
88 | ptr += 3; |
89 | for (j = 0; j < 4; j++) | |
90 | printf("%02X ", *ptr--); | |
91 | printf("\n"); | |
92 | } | |
93 | break; | |
94 | case MMC_RSP_R3: | |
95 | printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", | |
96 | cmd->response[0]); | |
97 | break; | |
98 | default: | |
99 | printf("\t\tERROR MMC rsp not supported\n"); | |
100 | break; | |
101 | } | |
5db2fe3a | 102 | #else |
93bfd616 | 103 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a | 104 | #endif |
8635ff9e | 105 | return ret; |
272cc70b AF |
106 | } |
107 | ||
da61fa5f | 108 | int mmc_send_status(struct mmc *mmc, int timeout) |
5d4fc8d9 RR |
109 | { |
110 | struct mmc_cmd cmd; | |
d617c426 | 111 | int err, retries = 5; |
5d4fc8d9 RR |
112 | #ifdef CONFIG_MMC_TRACE |
113 | int status; | |
114 | #endif | |
115 | ||
116 | cmd.cmdidx = MMC_CMD_SEND_STATUS; | |
117 | cmd.resp_type = MMC_RSP_R1; | |
aaf3d41a MV |
118 | if (!mmc_host_is_spi(mmc)) |
119 | cmd.cmdarg = mmc->rca << 16; | |
5d4fc8d9 RR |
120 | |
121 | do { | |
122 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
d617c426 JK |
123 | if (!err) { |
124 | if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && | |
125 | (cmd.response[0] & MMC_STATUS_CURR_STATE) != | |
126 | MMC_STATE_PRG) | |
127 | break; | |
128 | else if (cmd.response[0] & MMC_STATUS_MASK) { | |
56196826 | 129 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
d617c426 JK |
130 | printf("Status Error: 0x%08X\n", |
131 | cmd.response[0]); | |
56196826 | 132 | #endif |
d617c426 JK |
133 | return COMM_ERR; |
134 | } | |
135 | } else if (--retries < 0) | |
5d4fc8d9 | 136 | return err; |
5d4fc8d9 RR |
137 | |
138 | udelay(1000); | |
139 | ||
5d4fc8d9 RR |
140 | } while (timeout--); |
141 | ||
5db2fe3a RR |
142 | #ifdef CONFIG_MMC_TRACE |
143 | status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; | |
144 | printf("CURR STATE:%d\n", status); | |
145 | #endif | |
5b0c942f | 146 | if (timeout <= 0) { |
56196826 | 147 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
5d4fc8d9 | 148 | printf("Timeout waiting card ready\n"); |
56196826 | 149 | #endif |
5d4fc8d9 RR |
150 | return TIMEOUT; |
151 | } | |
6b2221b0 AG |
152 | if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) |
153 | return SWITCH_ERR; | |
5d4fc8d9 RR |
154 | |
155 | return 0; | |
156 | } | |
157 | ||
da61fa5f | 158 | int mmc_set_blocklen(struct mmc *mmc, int len) |
272cc70b AF |
159 | { |
160 | struct mmc_cmd cmd; | |
161 | ||
786e8f81 | 162 | if (mmc->ddr_mode) |
d22e3d46 JC |
163 | return 0; |
164 | ||
272cc70b AF |
165 | cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; |
166 | cmd.resp_type = MMC_RSP_R1; | |
167 | cmd.cmdarg = len; | |
272cc70b AF |
168 | |
169 | return mmc_send_cmd(mmc, &cmd, NULL); | |
170 | } | |
171 | ||
172 | struct mmc *find_mmc_device(int dev_num) | |
173 | { | |
174 | struct mmc *m; | |
175 | struct list_head *entry; | |
176 | ||
177 | list_for_each(entry, &mmc_devices) { | |
178 | m = list_entry(entry, struct mmc, link); | |
179 | ||
180 | if (m->block_dev.dev == dev_num) | |
181 | return m; | |
182 | } | |
183 | ||
56196826 | 184 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 185 | printf("MMC Device %d not found\n", dev_num); |
56196826 | 186 | #endif |
272cc70b AF |
187 | |
188 | return NULL; | |
189 | } | |
190 | ||
ff8fef56 | 191 | static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, |
fdbb873e | 192 | lbaint_t blkcnt) |
272cc70b AF |
193 | { |
194 | struct mmc_cmd cmd; | |
195 | struct mmc_data data; | |
196 | ||
4a1a06bc AS |
197 | if (blkcnt > 1) |
198 | cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; | |
199 | else | |
200 | cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; | |
272cc70b AF |
201 | |
202 | if (mmc->high_capacity) | |
4a1a06bc | 203 | cmd.cmdarg = start; |
272cc70b | 204 | else |
4a1a06bc | 205 | cmd.cmdarg = start * mmc->read_bl_len; |
272cc70b AF |
206 | |
207 | cmd.resp_type = MMC_RSP_R1; | |
272cc70b AF |
208 | |
209 | data.dest = dst; | |
4a1a06bc | 210 | data.blocks = blkcnt; |
272cc70b AF |
211 | data.blocksize = mmc->read_bl_len; |
212 | data.flags = MMC_DATA_READ; | |
213 | ||
4a1a06bc AS |
214 | if (mmc_send_cmd(mmc, &cmd, &data)) |
215 | return 0; | |
272cc70b | 216 | |
4a1a06bc AS |
217 | if (blkcnt > 1) { |
218 | cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; | |
219 | cmd.cmdarg = 0; | |
220 | cmd.resp_type = MMC_RSP_R1b; | |
4a1a06bc | 221 | if (mmc_send_cmd(mmc, &cmd, NULL)) { |
56196826 | 222 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
4a1a06bc | 223 | printf("mmc fail to send stop cmd\n"); |
56196826 | 224 | #endif |
4a1a06bc AS |
225 | return 0; |
226 | } | |
272cc70b AF |
227 | } |
228 | ||
4a1a06bc | 229 | return blkcnt; |
272cc70b AF |
230 | } |
231 | ||
ff8fef56 | 232 | static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) |
272cc70b | 233 | { |
4a1a06bc AS |
234 | lbaint_t cur, blocks_todo = blkcnt; |
235 | ||
236 | if (blkcnt == 0) | |
237 | return 0; | |
272cc70b | 238 | |
4a1a06bc | 239 | struct mmc *mmc = find_mmc_device(dev_num); |
272cc70b AF |
240 | if (!mmc) |
241 | return 0; | |
242 | ||
d2bf29e3 | 243 | if ((start + blkcnt) > mmc->block_dev.lba) { |
56196826 | 244 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
ff8fef56 | 245 | printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", |
d2bf29e3 | 246 | start + blkcnt, mmc->block_dev.lba); |
56196826 | 247 | #endif |
d2bf29e3 LW |
248 | return 0; |
249 | } | |
272cc70b | 250 | |
4a1a06bc | 251 | if (mmc_set_blocklen(mmc, mmc->read_bl_len)) |
272cc70b | 252 | return 0; |
272cc70b | 253 | |
4a1a06bc | 254 | do { |
93bfd616 PA |
255 | cur = (blocks_todo > mmc->cfg->b_max) ? |
256 | mmc->cfg->b_max : blocks_todo; | |
4a1a06bc AS |
257 | if(mmc_read_blocks(mmc, dst, start, cur) != cur) |
258 | return 0; | |
259 | blocks_todo -= cur; | |
260 | start += cur; | |
261 | dst += cur * mmc->read_bl_len; | |
262 | } while (blocks_todo > 0); | |
272cc70b AF |
263 | |
264 | return blkcnt; | |
265 | } | |
266 | ||
fdbb873e | 267 | static int mmc_go_idle(struct mmc *mmc) |
272cc70b AF |
268 | { |
269 | struct mmc_cmd cmd; | |
270 | int err; | |
271 | ||
272 | udelay(1000); | |
273 | ||
274 | cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; | |
275 | cmd.cmdarg = 0; | |
276 | cmd.resp_type = MMC_RSP_NONE; | |
272cc70b AF |
277 | |
278 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
279 | ||
280 | if (err) | |
281 | return err; | |
282 | ||
283 | udelay(2000); | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
fdbb873e | 288 | static int sd_send_op_cond(struct mmc *mmc) |
272cc70b AF |
289 | { |
290 | int timeout = 1000; | |
291 | int err; | |
292 | struct mmc_cmd cmd; | |
293 | ||
294 | do { | |
295 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
296 | cmd.resp_type = MMC_RSP_R1; | |
297 | cmd.cmdarg = 0; | |
272cc70b AF |
298 | |
299 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
300 | ||
301 | if (err) | |
302 | return err; | |
303 | ||
304 | cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; | |
305 | cmd.resp_type = MMC_RSP_R3; | |
250de12b SB |
306 | |
307 | /* | |
308 | * Most cards do not answer if some reserved bits | |
309 | * in the ocr are set. However, Some controller | |
310 | * can set bit 7 (reserved for low voltages), but | |
311 | * how to manage low voltages SD card is not yet | |
312 | * specified. | |
313 | */ | |
d52ebf10 | 314 | cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : |
93bfd616 | 315 | (mmc->cfg->voltages & 0xff8000); |
272cc70b AF |
316 | |
317 | if (mmc->version == SD_VERSION_2) | |
318 | cmd.cmdarg |= OCR_HCS; | |
319 | ||
320 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
321 | ||
322 | if (err) | |
323 | return err; | |
324 | ||
325 | udelay(1000); | |
326 | } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--); | |
327 | ||
328 | if (timeout <= 0) | |
329 | return UNUSABLE_ERR; | |
330 | ||
331 | if (mmc->version != SD_VERSION_2) | |
332 | mmc->version = SD_VERSION_1_0; | |
333 | ||
d52ebf10 TC |
334 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
335 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
336 | cmd.resp_type = MMC_RSP_R3; | |
337 | cmd.cmdarg = 0; | |
d52ebf10 TC |
338 | |
339 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
340 | ||
341 | if (err) | |
342 | return err; | |
343 | } | |
344 | ||
998be3dd | 345 | mmc->ocr = cmd.response[0]; |
272cc70b AF |
346 | |
347 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
348 | mmc->rca = 0; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
e9550449 CLC |
353 | /* We pass in the cmd since otherwise the init seems to fail */ |
354 | static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd, | |
355 | int use_arg) | |
272cc70b | 356 | { |
272cc70b AF |
357 | int err; |
358 | ||
e9550449 CLC |
359 | cmd->cmdidx = MMC_CMD_SEND_OP_COND; |
360 | cmd->resp_type = MMC_RSP_R3; | |
361 | cmd->cmdarg = 0; | |
362 | if (use_arg && !mmc_host_is_spi(mmc)) { | |
363 | cmd->cmdarg = | |
93bfd616 | 364 | (mmc->cfg->voltages & |
a626c8d4 AG |
365 | (mmc->ocr & OCR_VOLTAGE_MASK)) | |
366 | (mmc->ocr & OCR_ACCESS_MODE); | |
e9550449 | 367 | |
93bfd616 | 368 | if (mmc->cfg->host_caps & MMC_MODE_HC) |
e9550449 CLC |
369 | cmd->cmdarg |= OCR_HCS; |
370 | } | |
371 | err = mmc_send_cmd(mmc, cmd, NULL); | |
372 | if (err) | |
373 | return err; | |
a626c8d4 | 374 | mmc->ocr = cmd->response[0]; |
e9550449 CLC |
375 | return 0; |
376 | } | |
377 | ||
750121c3 | 378 | static int mmc_send_op_cond(struct mmc *mmc) |
e9550449 CLC |
379 | { |
380 | struct mmc_cmd cmd; | |
381 | int err, i; | |
382 | ||
272cc70b AF |
383 | /* Some cards seem to need this */ |
384 | mmc_go_idle(mmc); | |
385 | ||
31cacbab | 386 | /* Asking to the card its capabilities */ |
e9550449 CLC |
387 | mmc->op_cond_pending = 1; |
388 | for (i = 0; i < 2; i++) { | |
389 | err = mmc_send_op_cond_iter(mmc, &cmd, i != 0); | |
390 | if (err) | |
391 | return err; | |
cd6881b5 | 392 | |
e9550449 | 393 | /* exit if not busy (flag seems to be inverted) */ |
a626c8d4 | 394 | if (mmc->ocr & OCR_BUSY) |
e9550449 CLC |
395 | return 0; |
396 | } | |
397 | return IN_PROGRESS; | |
398 | } | |
cd6881b5 | 399 | |
750121c3 | 400 | static int mmc_complete_op_cond(struct mmc *mmc) |
e9550449 CLC |
401 | { |
402 | struct mmc_cmd cmd; | |
403 | int timeout = 1000; | |
404 | uint start; | |
405 | int err; | |
cd6881b5 | 406 | |
e9550449 CLC |
407 | mmc->op_cond_pending = 0; |
408 | start = get_timer(0); | |
272cc70b | 409 | do { |
e9550449 | 410 | err = mmc_send_op_cond_iter(mmc, &cmd, 1); |
272cc70b AF |
411 | if (err) |
412 | return err; | |
e9550449 CLC |
413 | if (get_timer(start) > timeout) |
414 | return UNUSABLE_ERR; | |
415 | udelay(100); | |
a626c8d4 | 416 | } while (!(mmc->ocr & OCR_BUSY)); |
272cc70b | 417 | |
d52ebf10 TC |
418 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
419 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
420 | cmd.resp_type = MMC_RSP_R3; | |
421 | cmd.cmdarg = 0; | |
d52ebf10 TC |
422 | |
423 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
424 | ||
425 | if (err) | |
426 | return err; | |
a626c8d4 AG |
427 | |
428 | mmc->ocr = cmd.response[0]; | |
d52ebf10 TC |
429 | } |
430 | ||
272cc70b | 431 | mmc->version = MMC_VERSION_UNKNOWN; |
272cc70b AF |
432 | |
433 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
def816a2 | 434 | mmc->rca = 1; |
272cc70b AF |
435 | |
436 | return 0; | |
437 | } | |
438 | ||
439 | ||
fdbb873e | 440 | static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) |
272cc70b AF |
441 | { |
442 | struct mmc_cmd cmd; | |
443 | struct mmc_data data; | |
444 | int err; | |
445 | ||
446 | /* Get the Card Status Register */ | |
447 | cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; | |
448 | cmd.resp_type = MMC_RSP_R1; | |
449 | cmd.cmdarg = 0; | |
272cc70b | 450 | |
cdfd1ac6 | 451 | data.dest = (char *)ext_csd; |
272cc70b | 452 | data.blocks = 1; |
8bfa195e | 453 | data.blocksize = MMC_MAX_BLOCK_LEN; |
272cc70b AF |
454 | data.flags = MMC_DATA_READ; |
455 | ||
456 | err = mmc_send_cmd(mmc, &cmd, &data); | |
457 | ||
458 | return err; | |
459 | } | |
460 | ||
461 | ||
fdbb873e | 462 | static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) |
272cc70b AF |
463 | { |
464 | struct mmc_cmd cmd; | |
5d4fc8d9 RR |
465 | int timeout = 1000; |
466 | int ret; | |
272cc70b AF |
467 | |
468 | cmd.cmdidx = MMC_CMD_SWITCH; | |
469 | cmd.resp_type = MMC_RSP_R1b; | |
470 | cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | | |
5d4fc8d9 RR |
471 | (index << 16) | |
472 | (value << 8); | |
272cc70b | 473 | |
5d4fc8d9 RR |
474 | ret = mmc_send_cmd(mmc, &cmd, NULL); |
475 | ||
476 | /* Waiting for the ready status */ | |
93ad0d18 JK |
477 | if (!ret) |
478 | ret = mmc_send_status(mmc, timeout); | |
5d4fc8d9 RR |
479 | |
480 | return ret; | |
481 | ||
272cc70b AF |
482 | } |
483 | ||
fdbb873e | 484 | static int mmc_change_freq(struct mmc *mmc) |
272cc70b | 485 | { |
8bfa195e | 486 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
272cc70b AF |
487 | char cardtype; |
488 | int err; | |
489 | ||
fc5b32fb | 490 | mmc->card_caps = 0; |
272cc70b | 491 | |
d52ebf10 TC |
492 | if (mmc_host_is_spi(mmc)) |
493 | return 0; | |
494 | ||
272cc70b AF |
495 | /* Only version 4 supports high-speed */ |
496 | if (mmc->version < MMC_VERSION_4) | |
497 | return 0; | |
498 | ||
fc5b32fb AG |
499 | mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; |
500 | ||
272cc70b AF |
501 | err = mmc_send_ext_csd(mmc, ext_csd); |
502 | ||
503 | if (err) | |
504 | return err; | |
505 | ||
0560db18 | 506 | cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; |
272cc70b AF |
507 | |
508 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); | |
509 | ||
510 | if (err) | |
6b2221b0 | 511 | return err == SWITCH_ERR ? 0 : err; |
272cc70b AF |
512 | |
513 | /* Now check to see that it worked */ | |
514 | err = mmc_send_ext_csd(mmc, ext_csd); | |
515 | ||
516 | if (err) | |
517 | return err; | |
518 | ||
519 | /* No high-speed support */ | |
0560db18 | 520 | if (!ext_csd[EXT_CSD_HS_TIMING]) |
272cc70b AF |
521 | return 0; |
522 | ||
523 | /* High Speed is set, there are two types: 52MHz and 26MHz */ | |
d22e3d46 | 524 | if (cardtype & EXT_CSD_CARD_TYPE_52) { |
201d5ac4 | 525 | if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) |
d22e3d46 | 526 | mmc->card_caps |= MMC_MODE_DDR_52MHz; |
272cc70b | 527 | mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
d22e3d46 | 528 | } else { |
272cc70b | 529 | mmc->card_caps |= MMC_MODE_HS; |
d22e3d46 | 530 | } |
272cc70b AF |
531 | |
532 | return 0; | |
533 | } | |
534 | ||
f866a46d SW |
535 | static int mmc_set_capacity(struct mmc *mmc, int part_num) |
536 | { | |
537 | switch (part_num) { | |
538 | case 0: | |
539 | mmc->capacity = mmc->capacity_user; | |
540 | break; | |
541 | case 1: | |
542 | case 2: | |
543 | mmc->capacity = mmc->capacity_boot; | |
544 | break; | |
545 | case 3: | |
546 | mmc->capacity = mmc->capacity_rpmb; | |
547 | break; | |
548 | case 4: | |
549 | case 5: | |
550 | case 6: | |
551 | case 7: | |
552 | mmc->capacity = mmc->capacity_gp[part_num - 4]; | |
553 | break; | |
554 | default: | |
555 | return -1; | |
556 | } | |
557 | ||
558 | mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
d2356284 SW |
563 | int mmc_select_hwpart(int dev_num, int hwpart) |
564 | { | |
565 | struct mmc *mmc = find_mmc_device(dev_num); | |
566 | int ret; | |
567 | ||
568 | if (!mmc) | |
d4622df3 | 569 | return -ENODEV; |
d2356284 SW |
570 | |
571 | if (mmc->part_num == hwpart) | |
572 | return 0; | |
573 | ||
574 | if (mmc->part_config == MMCPART_NOAVAILABLE) { | |
575 | printf("Card doesn't support part_switch\n"); | |
d4622df3 | 576 | return -EMEDIUMTYPE; |
d2356284 SW |
577 | } |
578 | ||
579 | ret = mmc_switch_part(dev_num, hwpart); | |
580 | if (ret) | |
d4622df3 | 581 | return ret; |
d2356284 SW |
582 | |
583 | mmc->part_num = hwpart; | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | ||
bc897b1d LW |
589 | int mmc_switch_part(int dev_num, unsigned int part_num) |
590 | { | |
591 | struct mmc *mmc = find_mmc_device(dev_num); | |
f866a46d | 592 | int ret; |
bc897b1d LW |
593 | |
594 | if (!mmc) | |
595 | return -1; | |
596 | ||
f866a46d SW |
597 | ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, |
598 | (mmc->part_config & ~PART_ACCESS_MASK) | |
599 | | (part_num & PART_ACCESS_MASK)); | |
f866a46d | 600 | |
6dc93e70 PB |
601 | /* |
602 | * Set the capacity if the switch succeeded or was intended | |
603 | * to return to representing the raw device. | |
604 | */ | |
605 | if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) | |
606 | ret = mmc_set_capacity(mmc, part_num); | |
607 | ||
608 | return ret; | |
bc897b1d LW |
609 | } |
610 | ||
ac9da0e0 DSC |
611 | int mmc_hwpart_config(struct mmc *mmc, |
612 | const struct mmc_hwpart_conf *conf, | |
613 | enum mmc_hwpart_conf_mode mode) | |
614 | { | |
615 | u8 part_attrs = 0; | |
616 | u32 enh_size_mult; | |
617 | u32 enh_start_addr; | |
618 | u32 gp_size_mult[4]; | |
619 | u32 max_enh_size_mult; | |
620 | u32 tot_enh_size_mult = 0; | |
8dda5b0e | 621 | u8 wr_rel_set; |
ac9da0e0 DSC |
622 | int i, pidx, err; |
623 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); | |
624 | ||
625 | if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) | |
626 | return -EINVAL; | |
627 | ||
628 | if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { | |
629 | printf("eMMC >= 4.4 required for enhanced user data area\n"); | |
630 | return -EMEDIUMTYPE; | |
631 | } | |
632 | ||
633 | if (!(mmc->part_support & PART_SUPPORT)) { | |
634 | printf("Card does not support partitioning\n"); | |
635 | return -EMEDIUMTYPE; | |
636 | } | |
637 | ||
638 | if (!mmc->hc_wp_grp_size) { | |
639 | printf("Card does not define HC WP group size\n"); | |
640 | return -EMEDIUMTYPE; | |
641 | } | |
642 | ||
643 | /* check partition alignment and total enhanced size */ | |
644 | if (conf->user.enh_size) { | |
645 | if (conf->user.enh_size % mmc->hc_wp_grp_size || | |
646 | conf->user.enh_start % mmc->hc_wp_grp_size) { | |
647 | printf("User data enhanced area not HC WP group " | |
648 | "size aligned\n"); | |
649 | return -EINVAL; | |
650 | } | |
651 | part_attrs |= EXT_CSD_ENH_USR; | |
652 | enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; | |
653 | if (mmc->high_capacity) { | |
654 | enh_start_addr = conf->user.enh_start; | |
655 | } else { | |
656 | enh_start_addr = (conf->user.enh_start << 9); | |
657 | } | |
658 | } else { | |
659 | enh_size_mult = 0; | |
660 | enh_start_addr = 0; | |
661 | } | |
662 | tot_enh_size_mult += enh_size_mult; | |
663 | ||
664 | for (pidx = 0; pidx < 4; pidx++) { | |
665 | if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { | |
666 | printf("GP%i partition not HC WP group size " | |
667 | "aligned\n", pidx+1); | |
668 | return -EINVAL; | |
669 | } | |
670 | gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; | |
671 | if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { | |
672 | part_attrs |= EXT_CSD_ENH_GP(pidx); | |
673 | tot_enh_size_mult += gp_size_mult[pidx]; | |
674 | } | |
675 | } | |
676 | ||
677 | if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { | |
678 | printf("Card does not support enhanced attribute\n"); | |
679 | return -EMEDIUMTYPE; | |
680 | } | |
681 | ||
682 | err = mmc_send_ext_csd(mmc, ext_csd); | |
683 | if (err) | |
684 | return err; | |
685 | ||
686 | max_enh_size_mult = | |
687 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + | |
688 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + | |
689 | ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; | |
690 | if (tot_enh_size_mult > max_enh_size_mult) { | |
691 | printf("Total enhanced size exceeds maximum (%u > %u)\n", | |
692 | tot_enh_size_mult, max_enh_size_mult); | |
693 | return -EMEDIUMTYPE; | |
694 | } | |
695 | ||
8dda5b0e DSC |
696 | /* The default value of EXT_CSD_WR_REL_SET is device |
697 | * dependent, the values can only be changed if the | |
698 | * EXT_CSD_HS_CTRL_REL bit is set. The values can be | |
699 | * changed only once and before partitioning is completed. */ | |
700 | wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
701 | if (conf->user.wr_rel_change) { | |
702 | if (conf->user.wr_rel_set) | |
703 | wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; | |
704 | else | |
705 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; | |
706 | } | |
707 | for (pidx = 0; pidx < 4; pidx++) { | |
708 | if (conf->gp_part[pidx].wr_rel_change) { | |
709 | if (conf->gp_part[pidx].wr_rel_set) | |
710 | wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); | |
711 | else | |
712 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); | |
713 | } | |
714 | } | |
715 | ||
716 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && | |
717 | !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { | |
718 | puts("Card does not support host controlled partition write " | |
719 | "reliability settings\n"); | |
720 | return -EMEDIUMTYPE; | |
721 | } | |
722 | ||
ac9da0e0 DSC |
723 | if (ext_csd[EXT_CSD_PARTITION_SETTING] & |
724 | EXT_CSD_PARTITION_SETTING_COMPLETED) { | |
725 | printf("Card already partitioned\n"); | |
726 | return -EPERM; | |
727 | } | |
728 | ||
729 | if (mode == MMC_HWPART_CONF_CHECK) | |
730 | return 0; | |
731 | ||
732 | /* Partitioning requires high-capacity size definitions */ | |
733 | if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { | |
734 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
735 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
736 | ||
737 | if (err) | |
738 | return err; | |
739 | ||
740 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
741 | ||
742 | /* update erase group size to be high-capacity */ | |
743 | mmc->erase_grp_size = | |
744 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; | |
745 | ||
746 | } | |
747 | ||
748 | /* all OK, write the configuration */ | |
749 | for (i = 0; i < 4; i++) { | |
750 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
751 | EXT_CSD_ENH_START_ADDR+i, | |
752 | (enh_start_addr >> (i*8)) & 0xFF); | |
753 | if (err) | |
754 | return err; | |
755 | } | |
756 | for (i = 0; i < 3; i++) { | |
757 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
758 | EXT_CSD_ENH_SIZE_MULT+i, | |
759 | (enh_size_mult >> (i*8)) & 0xFF); | |
760 | if (err) | |
761 | return err; | |
762 | } | |
763 | for (pidx = 0; pidx < 4; pidx++) { | |
764 | for (i = 0; i < 3; i++) { | |
765 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
766 | EXT_CSD_GP_SIZE_MULT+pidx*3+i, | |
767 | (gp_size_mult[pidx] >> (i*8)) & 0xFF); | |
768 | if (err) | |
769 | return err; | |
770 | } | |
771 | } | |
772 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
773 | EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); | |
774 | if (err) | |
775 | return err; | |
776 | ||
777 | if (mode == MMC_HWPART_CONF_SET) | |
778 | return 0; | |
779 | ||
8dda5b0e DSC |
780 | /* The WR_REL_SET is a write-once register but shall be |
781 | * written before setting PART_SETTING_COMPLETED. As it is | |
782 | * write-once we can only write it when completing the | |
783 | * partitioning. */ | |
784 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { | |
785 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
786 | EXT_CSD_WR_REL_SET, wr_rel_set); | |
787 | if (err) | |
788 | return err; | |
789 | } | |
790 | ||
ac9da0e0 DSC |
791 | /* Setting PART_SETTING_COMPLETED confirms the partition |
792 | * configuration but it only becomes effective after power | |
793 | * cycle, so we do not adjust the partition related settings | |
794 | * in the mmc struct. */ | |
795 | ||
796 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
797 | EXT_CSD_PARTITION_SETTING, | |
798 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
799 | if (err) | |
800 | return err; | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
48972d90 TR |
805 | int mmc_getcd(struct mmc *mmc) |
806 | { | |
807 | int cd; | |
808 | ||
809 | cd = board_mmc_getcd(mmc); | |
810 | ||
d4e1da4e | 811 | if (cd < 0) { |
93bfd616 PA |
812 | if (mmc->cfg->ops->getcd) |
813 | cd = mmc->cfg->ops->getcd(mmc); | |
d4e1da4e PK |
814 | else |
815 | cd = 1; | |
816 | } | |
48972d90 TR |
817 | |
818 | return cd; | |
819 | } | |
820 | ||
fdbb873e | 821 | static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) |
272cc70b AF |
822 | { |
823 | struct mmc_cmd cmd; | |
824 | struct mmc_data data; | |
825 | ||
826 | /* Switch the frequency */ | |
827 | cmd.cmdidx = SD_CMD_SWITCH_FUNC; | |
828 | cmd.resp_type = MMC_RSP_R1; | |
829 | cmd.cmdarg = (mode << 31) | 0xffffff; | |
830 | cmd.cmdarg &= ~(0xf << (group * 4)); | |
831 | cmd.cmdarg |= value << (group * 4); | |
272cc70b AF |
832 | |
833 | data.dest = (char *)resp; | |
834 | data.blocksize = 64; | |
835 | data.blocks = 1; | |
836 | data.flags = MMC_DATA_READ; | |
837 | ||
838 | return mmc_send_cmd(mmc, &cmd, &data); | |
839 | } | |
840 | ||
841 | ||
fdbb873e | 842 | static int sd_change_freq(struct mmc *mmc) |
272cc70b AF |
843 | { |
844 | int err; | |
845 | struct mmc_cmd cmd; | |
f781dd38 A |
846 | ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); |
847 | ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); | |
272cc70b AF |
848 | struct mmc_data data; |
849 | int timeout; | |
850 | ||
851 | mmc->card_caps = 0; | |
852 | ||
d52ebf10 TC |
853 | if (mmc_host_is_spi(mmc)) |
854 | return 0; | |
855 | ||
272cc70b AF |
856 | /* Read the SCR to find out if this card supports higher speeds */ |
857 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
858 | cmd.resp_type = MMC_RSP_R1; | |
859 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
860 | |
861 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
862 | ||
863 | if (err) | |
864 | return err; | |
865 | ||
866 | cmd.cmdidx = SD_CMD_APP_SEND_SCR; | |
867 | cmd.resp_type = MMC_RSP_R1; | |
868 | cmd.cmdarg = 0; | |
272cc70b AF |
869 | |
870 | timeout = 3; | |
871 | ||
872 | retry_scr: | |
f781dd38 | 873 | data.dest = (char *)scr; |
272cc70b AF |
874 | data.blocksize = 8; |
875 | data.blocks = 1; | |
876 | data.flags = MMC_DATA_READ; | |
877 | ||
878 | err = mmc_send_cmd(mmc, &cmd, &data); | |
879 | ||
880 | if (err) { | |
881 | if (timeout--) | |
882 | goto retry_scr; | |
883 | ||
884 | return err; | |
885 | } | |
886 | ||
4e3d89ba YK |
887 | mmc->scr[0] = __be32_to_cpu(scr[0]); |
888 | mmc->scr[1] = __be32_to_cpu(scr[1]); | |
272cc70b AF |
889 | |
890 | switch ((mmc->scr[0] >> 24) & 0xf) { | |
891 | case 0: | |
892 | mmc->version = SD_VERSION_1_0; | |
893 | break; | |
894 | case 1: | |
895 | mmc->version = SD_VERSION_1_10; | |
896 | break; | |
897 | case 2: | |
898 | mmc->version = SD_VERSION_2; | |
1741c64d JC |
899 | if ((mmc->scr[0] >> 15) & 0x1) |
900 | mmc->version = SD_VERSION_3; | |
272cc70b AF |
901 | break; |
902 | default: | |
903 | mmc->version = SD_VERSION_1_0; | |
904 | break; | |
905 | } | |
906 | ||
b44c7083 AS |
907 | if (mmc->scr[0] & SD_DATA_4BIT) |
908 | mmc->card_caps |= MMC_MODE_4BIT; | |
909 | ||
272cc70b AF |
910 | /* Version 1.0 doesn't support switching */ |
911 | if (mmc->version == SD_VERSION_1_0) | |
912 | return 0; | |
913 | ||
914 | timeout = 4; | |
915 | while (timeout--) { | |
916 | err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, | |
f781dd38 | 917 | (u8 *)switch_status); |
272cc70b AF |
918 | |
919 | if (err) | |
920 | return err; | |
921 | ||
922 | /* The high-speed function is busy. Try again */ | |
4e3d89ba | 923 | if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) |
272cc70b AF |
924 | break; |
925 | } | |
926 | ||
272cc70b | 927 | /* If high-speed isn't supported, we return */ |
4e3d89ba | 928 | if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) |
272cc70b AF |
929 | return 0; |
930 | ||
2c3fbf4c ML |
931 | /* |
932 | * If the host doesn't support SD_HIGHSPEED, do not switch card to | |
933 | * HIGHSPEED mode even if the card support SD_HIGHSPPED. | |
934 | * This can avoid furthur problem when the card runs in different | |
935 | * mode between the host. | |
936 | */ | |
93bfd616 PA |
937 | if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && |
938 | (mmc->cfg->host_caps & MMC_MODE_HS))) | |
2c3fbf4c ML |
939 | return 0; |
940 | ||
f781dd38 | 941 | err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); |
272cc70b AF |
942 | |
943 | if (err) | |
944 | return err; | |
945 | ||
4e3d89ba | 946 | if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) |
272cc70b AF |
947 | mmc->card_caps |= MMC_MODE_HS; |
948 | ||
949 | return 0; | |
950 | } | |
951 | ||
952 | /* frequency bases */ | |
953 | /* divided by 10 to be nice to platforms without floating point */ | |
5f837c2c | 954 | static const int fbase[] = { |
272cc70b AF |
955 | 10000, |
956 | 100000, | |
957 | 1000000, | |
958 | 10000000, | |
959 | }; | |
960 | ||
961 | /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice | |
962 | * to platforms without floating point. | |
963 | */ | |
5f837c2c | 964 | static const int multipliers[] = { |
272cc70b AF |
965 | 0, /* reserved */ |
966 | 10, | |
967 | 12, | |
968 | 13, | |
969 | 15, | |
970 | 20, | |
971 | 25, | |
972 | 30, | |
973 | 35, | |
974 | 40, | |
975 | 45, | |
976 | 50, | |
977 | 55, | |
978 | 60, | |
979 | 70, | |
980 | 80, | |
981 | }; | |
982 | ||
fdbb873e | 983 | static void mmc_set_ios(struct mmc *mmc) |
272cc70b | 984 | { |
93bfd616 PA |
985 | if (mmc->cfg->ops->set_ios) |
986 | mmc->cfg->ops->set_ios(mmc); | |
272cc70b AF |
987 | } |
988 | ||
989 | void mmc_set_clock(struct mmc *mmc, uint clock) | |
990 | { | |
93bfd616 PA |
991 | if (clock > mmc->cfg->f_max) |
992 | clock = mmc->cfg->f_max; | |
272cc70b | 993 | |
93bfd616 PA |
994 | if (clock < mmc->cfg->f_min) |
995 | clock = mmc->cfg->f_min; | |
272cc70b AF |
996 | |
997 | mmc->clock = clock; | |
998 | ||
999 | mmc_set_ios(mmc); | |
1000 | } | |
1001 | ||
fdbb873e | 1002 | static void mmc_set_bus_width(struct mmc *mmc, uint width) |
272cc70b AF |
1003 | { |
1004 | mmc->bus_width = width; | |
1005 | ||
1006 | mmc_set_ios(mmc); | |
1007 | } | |
1008 | ||
fdbb873e | 1009 | static int mmc_startup(struct mmc *mmc) |
272cc70b | 1010 | { |
f866a46d | 1011 | int err, i; |
272cc70b | 1012 | uint mult, freq; |
639b7827 | 1013 | u64 cmult, csize, capacity; |
272cc70b | 1014 | struct mmc_cmd cmd; |
8bfa195e SG |
1015 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
1016 | ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); | |
5d4fc8d9 | 1017 | int timeout = 1000; |
0c453bb7 | 1018 | bool has_parts = false; |
8a0cf490 | 1019 | bool part_completed; |
272cc70b | 1020 | |
d52ebf10 TC |
1021 | #ifdef CONFIG_MMC_SPI_CRC_ON |
1022 | if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ | |
1023 | cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; | |
1024 | cmd.resp_type = MMC_RSP_R1; | |
1025 | cmd.cmdarg = 1; | |
d52ebf10 TC |
1026 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1027 | ||
1028 | if (err) | |
1029 | return err; | |
1030 | } | |
1031 | #endif | |
1032 | ||
272cc70b | 1033 | /* Put the Card in Identify Mode */ |
d52ebf10 TC |
1034 | cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : |
1035 | MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ | |
272cc70b AF |
1036 | cmd.resp_type = MMC_RSP_R2; |
1037 | cmd.cmdarg = 0; | |
272cc70b AF |
1038 | |
1039 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1040 | ||
1041 | if (err) | |
1042 | return err; | |
1043 | ||
1044 | memcpy(mmc->cid, cmd.response, 16); | |
1045 | ||
1046 | /* | |
1047 | * For MMC cards, set the Relative Address. | |
1048 | * For SD cards, get the Relatvie Address. | |
1049 | * This also puts the cards into Standby State | |
1050 | */ | |
d52ebf10 TC |
1051 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1052 | cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; | |
1053 | cmd.cmdarg = mmc->rca << 16; | |
1054 | cmd.resp_type = MMC_RSP_R6; | |
272cc70b | 1055 | |
d52ebf10 | 1056 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1057 | |
d52ebf10 TC |
1058 | if (err) |
1059 | return err; | |
272cc70b | 1060 | |
d52ebf10 TC |
1061 | if (IS_SD(mmc)) |
1062 | mmc->rca = (cmd.response[0] >> 16) & 0xffff; | |
1063 | } | |
272cc70b AF |
1064 | |
1065 | /* Get the Card-Specific Data */ | |
1066 | cmd.cmdidx = MMC_CMD_SEND_CSD; | |
1067 | cmd.resp_type = MMC_RSP_R2; | |
1068 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1069 | |
1070 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1071 | ||
5d4fc8d9 RR |
1072 | /* Waiting for the ready status */ |
1073 | mmc_send_status(mmc, timeout); | |
1074 | ||
272cc70b AF |
1075 | if (err) |
1076 | return err; | |
1077 | ||
998be3dd RV |
1078 | mmc->csd[0] = cmd.response[0]; |
1079 | mmc->csd[1] = cmd.response[1]; | |
1080 | mmc->csd[2] = cmd.response[2]; | |
1081 | mmc->csd[3] = cmd.response[3]; | |
272cc70b AF |
1082 | |
1083 | if (mmc->version == MMC_VERSION_UNKNOWN) { | |
0b453ffe | 1084 | int version = (cmd.response[0] >> 26) & 0xf; |
272cc70b AF |
1085 | |
1086 | switch (version) { | |
1087 | case 0: | |
1088 | mmc->version = MMC_VERSION_1_2; | |
1089 | break; | |
1090 | case 1: | |
1091 | mmc->version = MMC_VERSION_1_4; | |
1092 | break; | |
1093 | case 2: | |
1094 | mmc->version = MMC_VERSION_2_2; | |
1095 | break; | |
1096 | case 3: | |
1097 | mmc->version = MMC_VERSION_3; | |
1098 | break; | |
1099 | case 4: | |
1100 | mmc->version = MMC_VERSION_4; | |
1101 | break; | |
1102 | default: | |
1103 | mmc->version = MMC_VERSION_1_2; | |
1104 | break; | |
1105 | } | |
1106 | } | |
1107 | ||
1108 | /* divide frequency by 10, since the mults are 10x bigger */ | |
0b453ffe RV |
1109 | freq = fbase[(cmd.response[0] & 0x7)]; |
1110 | mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; | |
272cc70b AF |
1111 | |
1112 | mmc->tran_speed = freq * mult; | |
1113 | ||
ab71188c | 1114 | mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); |
998be3dd | 1115 | mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); |
272cc70b AF |
1116 | |
1117 | if (IS_SD(mmc)) | |
1118 | mmc->write_bl_len = mmc->read_bl_len; | |
1119 | else | |
998be3dd | 1120 | mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); |
272cc70b AF |
1121 | |
1122 | if (mmc->high_capacity) { | |
1123 | csize = (mmc->csd[1] & 0x3f) << 16 | |
1124 | | (mmc->csd[2] & 0xffff0000) >> 16; | |
1125 | cmult = 8; | |
1126 | } else { | |
1127 | csize = (mmc->csd[1] & 0x3ff) << 2 | |
1128 | | (mmc->csd[2] & 0xc0000000) >> 30; | |
1129 | cmult = (mmc->csd[2] & 0x00038000) >> 15; | |
1130 | } | |
1131 | ||
f866a46d SW |
1132 | mmc->capacity_user = (csize + 1) << (cmult + 2); |
1133 | mmc->capacity_user *= mmc->read_bl_len; | |
1134 | mmc->capacity_boot = 0; | |
1135 | mmc->capacity_rpmb = 0; | |
1136 | for (i = 0; i < 4; i++) | |
1137 | mmc->capacity_gp[i] = 0; | |
272cc70b | 1138 | |
8bfa195e SG |
1139 | if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) |
1140 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1141 | |
8bfa195e SG |
1142 | if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) |
1143 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1144 | |
ab71188c MN |
1145 | if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { |
1146 | cmd.cmdidx = MMC_CMD_SET_DSR; | |
1147 | cmd.cmdarg = (mmc->dsr & 0xffff) << 16; | |
1148 | cmd.resp_type = MMC_RSP_NONE; | |
1149 | if (mmc_send_cmd(mmc, &cmd, NULL)) | |
1150 | printf("MMC: SET_DSR failed\n"); | |
1151 | } | |
1152 | ||
272cc70b | 1153 | /* Select the card, and put it into Transfer Mode */ |
d52ebf10 TC |
1154 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1155 | cmd.cmdidx = MMC_CMD_SELECT_CARD; | |
fe8f7066 | 1156 | cmd.resp_type = MMC_RSP_R1; |
d52ebf10 | 1157 | cmd.cmdarg = mmc->rca << 16; |
d52ebf10 | 1158 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1159 | |
d52ebf10 TC |
1160 | if (err) |
1161 | return err; | |
1162 | } | |
272cc70b | 1163 | |
e6f99a56 LW |
1164 | /* |
1165 | * For SD, its erase group is always one sector | |
1166 | */ | |
1167 | mmc->erase_grp_size = 1; | |
bc897b1d | 1168 | mmc->part_config = MMCPART_NOAVAILABLE; |
d23e2c09 SG |
1169 | if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { |
1170 | /* check ext_csd version and capacity */ | |
1171 | err = mmc_send_ext_csd(mmc, ext_csd); | |
9cf199eb DSC |
1172 | if (err) |
1173 | return err; | |
1174 | if (ext_csd[EXT_CSD_REV] >= 2) { | |
639b7827 YS |
1175 | /* |
1176 | * According to the JEDEC Standard, the value of | |
1177 | * ext_csd's capacity is valid if the value is more | |
1178 | * than 2GB | |
1179 | */ | |
0560db18 LW |
1180 | capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 |
1181 | | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | |
1182 | | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | |
1183 | | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; | |
8bfa195e | 1184 | capacity *= MMC_MAX_BLOCK_LEN; |
b1f1e821 | 1185 | if ((capacity >> 20) > 2 * 1024) |
f866a46d | 1186 | mmc->capacity_user = capacity; |
d23e2c09 | 1187 | } |
bc897b1d | 1188 | |
64f4a619 JC |
1189 | switch (ext_csd[EXT_CSD_REV]) { |
1190 | case 1: | |
1191 | mmc->version = MMC_VERSION_4_1; | |
1192 | break; | |
1193 | case 2: | |
1194 | mmc->version = MMC_VERSION_4_2; | |
1195 | break; | |
1196 | case 3: | |
1197 | mmc->version = MMC_VERSION_4_3; | |
1198 | break; | |
1199 | case 5: | |
1200 | mmc->version = MMC_VERSION_4_41; | |
1201 | break; | |
1202 | case 6: | |
1203 | mmc->version = MMC_VERSION_4_5; | |
1204 | break; | |
edab723b MN |
1205 | case 7: |
1206 | mmc->version = MMC_VERSION_5_0; | |
1207 | break; | |
64f4a619 JC |
1208 | } |
1209 | ||
8a0cf490 DSC |
1210 | /* The partition data may be non-zero but it is only |
1211 | * effective if PARTITION_SETTING_COMPLETED is set in | |
1212 | * EXT_CSD, so ignore any data if this bit is not set, | |
1213 | * except for enabling the high-capacity group size | |
1214 | * definition (see below). */ | |
1215 | part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & | |
1216 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
1217 | ||
0c453bb7 DSC |
1218 | /* store the partition info of emmc */ |
1219 | mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; | |
1220 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || | |
1221 | ext_csd[EXT_CSD_BOOT_MULT]) | |
1222 | mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; | |
8a0cf490 DSC |
1223 | if (part_completed && |
1224 | (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) | |
0c453bb7 DSC |
1225 | mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; |
1226 | ||
1227 | mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; | |
1228 | ||
1229 | mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; | |
1230 | ||
1231 | for (i = 0; i < 4; i++) { | |
1232 | int idx = EXT_CSD_GP_SIZE_MULT + i * 3; | |
8a0cf490 | 1233 | uint mult = (ext_csd[idx + 2] << 16) + |
0c453bb7 | 1234 | (ext_csd[idx + 1] << 8) + ext_csd[idx]; |
8a0cf490 DSC |
1235 | if (mult) |
1236 | has_parts = true; | |
1237 | if (!part_completed) | |
1238 | continue; | |
1239 | mmc->capacity_gp[i] = mult; | |
0c453bb7 DSC |
1240 | mmc->capacity_gp[i] *= |
1241 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1242 | mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
f8e89d67 | 1243 | mmc->capacity_gp[i] <<= 19; |
0c453bb7 DSC |
1244 | } |
1245 | ||
8a0cf490 DSC |
1246 | if (part_completed) { |
1247 | mmc->enh_user_size = | |
1248 | (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + | |
1249 | (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + | |
1250 | ext_csd[EXT_CSD_ENH_SIZE_MULT]; | |
1251 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1252 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
1253 | mmc->enh_user_size <<= 19; | |
1254 | mmc->enh_user_start = | |
1255 | (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + | |
1256 | (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + | |
1257 | (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + | |
1258 | ext_csd[EXT_CSD_ENH_START_ADDR]; | |
1259 | if (mmc->high_capacity) | |
1260 | mmc->enh_user_start <<= 9; | |
1261 | } | |
a7f852b6 | 1262 | |
e6f99a56 | 1263 | /* |
1937e5aa OM |
1264 | * Host needs to enable ERASE_GRP_DEF bit if device is |
1265 | * partitioned. This bit will be lost every time after a reset | |
1266 | * or power off. This will affect erase size. | |
e6f99a56 | 1267 | */ |
8a0cf490 | 1268 | if (part_completed) |
0c453bb7 | 1269 | has_parts = true; |
1937e5aa | 1270 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && |
0c453bb7 DSC |
1271 | (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) |
1272 | has_parts = true; | |
1273 | if (has_parts) { | |
1937e5aa OM |
1274 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
1275 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
1276 | ||
1277 | if (err) | |
1278 | return err; | |
021a8055 HP |
1279 | else |
1280 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
037dc0ab | 1281 | } |
1937e5aa | 1282 | |
037dc0ab | 1283 | if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { |
1937e5aa | 1284 | /* Read out group size from ext_csd */ |
0560db18 | 1285 | mmc->erase_grp_size = |
a4ff9f83 | 1286 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; |
d7b29129 MN |
1287 | /* |
1288 | * if high capacity and partition setting completed | |
1289 | * SEC_COUNT is valid even if it is smaller than 2 GiB | |
1290 | * JEDEC Standard JESD84-B45, 6.2.4 | |
1291 | */ | |
8a0cf490 | 1292 | if (mmc->high_capacity && part_completed) { |
d7b29129 MN |
1293 | capacity = (ext_csd[EXT_CSD_SEC_CNT]) | |
1294 | (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | | |
1295 | (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | | |
1296 | (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); | |
1297 | capacity *= MMC_MAX_BLOCK_LEN; | |
1298 | mmc->capacity_user = capacity; | |
1299 | } | |
8bfa195e | 1300 | } else { |
1937e5aa | 1301 | /* Calculate the group size from the csd value. */ |
e6f99a56 LW |
1302 | int erase_gsz, erase_gmul; |
1303 | erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; | |
1304 | erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; | |
1305 | mmc->erase_grp_size = (erase_gsz + 1) | |
1306 | * (erase_gmul + 1); | |
1307 | } | |
037dc0ab DSC |
1308 | |
1309 | mmc->hc_wp_grp_size = 1024 | |
1310 | * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1311 | * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
9e41a00b DSC |
1312 | |
1313 | mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
d23e2c09 SG |
1314 | } |
1315 | ||
f866a46d SW |
1316 | err = mmc_set_capacity(mmc, mmc->part_num); |
1317 | if (err) | |
1318 | return err; | |
1319 | ||
272cc70b AF |
1320 | if (IS_SD(mmc)) |
1321 | err = sd_change_freq(mmc); | |
1322 | else | |
1323 | err = mmc_change_freq(mmc); | |
1324 | ||
1325 | if (err) | |
1326 | return err; | |
1327 | ||
1328 | /* Restrict card's capabilities by what the host can do */ | |
93bfd616 | 1329 | mmc->card_caps &= mmc->cfg->host_caps; |
272cc70b AF |
1330 | |
1331 | if (IS_SD(mmc)) { | |
1332 | if (mmc->card_caps & MMC_MODE_4BIT) { | |
1333 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
1334 | cmd.resp_type = MMC_RSP_R1; | |
1335 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1336 | |
1337 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1338 | if (err) | |
1339 | return err; | |
1340 | ||
1341 | cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; | |
1342 | cmd.resp_type = MMC_RSP_R1; | |
1343 | cmd.cmdarg = 2; | |
272cc70b AF |
1344 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1345 | if (err) | |
1346 | return err; | |
1347 | ||
1348 | mmc_set_bus_width(mmc, 4); | |
1349 | } | |
1350 | ||
1351 | if (mmc->card_caps & MMC_MODE_HS) | |
ad5fd922 | 1352 | mmc->tran_speed = 50000000; |
272cc70b | 1353 | else |
ad5fd922 | 1354 | mmc->tran_speed = 25000000; |
fc5b32fb AG |
1355 | } else if (mmc->version >= MMC_VERSION_4) { |
1356 | /* Only version 4 of MMC supports wider bus widths */ | |
7798f6db AF |
1357 | int idx; |
1358 | ||
1359 | /* An array of possible bus widths in order of preference */ | |
1360 | static unsigned ext_csd_bits[] = { | |
d22e3d46 JC |
1361 | EXT_CSD_DDR_BUS_WIDTH_8, |
1362 | EXT_CSD_DDR_BUS_WIDTH_4, | |
7798f6db AF |
1363 | EXT_CSD_BUS_WIDTH_8, |
1364 | EXT_CSD_BUS_WIDTH_4, | |
1365 | EXT_CSD_BUS_WIDTH_1, | |
1366 | }; | |
1367 | ||
1368 | /* An array to map CSD bus widths to host cap bits */ | |
1369 | static unsigned ext_to_hostcaps[] = { | |
786e8f81 AG |
1370 | [EXT_CSD_DDR_BUS_WIDTH_4] = |
1371 | MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, | |
1372 | [EXT_CSD_DDR_BUS_WIDTH_8] = | |
1373 | MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, | |
7798f6db AF |
1374 | [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, |
1375 | [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, | |
1376 | }; | |
1377 | ||
1378 | /* An array to map chosen bus width to an integer */ | |
1379 | static unsigned widths[] = { | |
d22e3d46 | 1380 | 8, 4, 8, 4, 1, |
7798f6db AF |
1381 | }; |
1382 | ||
1383 | for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { | |
1384 | unsigned int extw = ext_csd_bits[idx]; | |
786e8f81 | 1385 | unsigned int caps = ext_to_hostcaps[extw]; |
7798f6db | 1386 | |
bf477073 AG |
1387 | /* |
1388 | * If the bus width is still not changed, | |
1389 | * don't try to set the default again. | |
1390 | * Otherwise, recover from switch attempts | |
1391 | * by switching to 1-bit bus width. | |
1392 | */ | |
1393 | if (extw == EXT_CSD_BUS_WIDTH_1 && | |
1394 | mmc->bus_width == 1) { | |
1395 | err = 0; | |
1396 | break; | |
1397 | } | |
1398 | ||
7798f6db | 1399 | /* |
786e8f81 AG |
1400 | * Check to make sure the card and controller support |
1401 | * these capabilities | |
7798f6db | 1402 | */ |
786e8f81 | 1403 | if ((mmc->card_caps & caps) != caps) |
7798f6db AF |
1404 | continue; |
1405 | ||
272cc70b | 1406 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
7798f6db | 1407 | EXT_CSD_BUS_WIDTH, extw); |
272cc70b AF |
1408 | |
1409 | if (err) | |
4137894e | 1410 | continue; |
272cc70b | 1411 | |
786e8f81 | 1412 | mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; |
7798f6db | 1413 | mmc_set_bus_width(mmc, widths[idx]); |
4137894e LW |
1414 | |
1415 | err = mmc_send_ext_csd(mmc, test_csd); | |
786e8f81 AG |
1416 | |
1417 | if (err) | |
1418 | continue; | |
1419 | ||
786a27b7 | 1420 | /* Only compare read only fields */ |
786e8f81 AG |
1421 | if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] |
1422 | == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && | |
1423 | ext_csd[EXT_CSD_HC_WP_GRP_SIZE] | |
1424 | == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && | |
1425 | ext_csd[EXT_CSD_REV] | |
1426 | == test_csd[EXT_CSD_REV] && | |
1427 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1428 | == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && | |
1429 | memcmp(&ext_csd[EXT_CSD_SEC_CNT], | |
1430 | &test_csd[EXT_CSD_SEC_CNT], 4) == 0) | |
4137894e | 1431 | break; |
786e8f81 AG |
1432 | else |
1433 | err = SWITCH_ERR; | |
272cc70b AF |
1434 | } |
1435 | ||
786e8f81 AG |
1436 | if (err) |
1437 | return err; | |
1438 | ||
272cc70b AF |
1439 | if (mmc->card_caps & MMC_MODE_HS) { |
1440 | if (mmc->card_caps & MMC_MODE_HS_52MHz) | |
ad5fd922 | 1441 | mmc->tran_speed = 52000000; |
272cc70b | 1442 | else |
ad5fd922 JC |
1443 | mmc->tran_speed = 26000000; |
1444 | } | |
272cc70b AF |
1445 | } |
1446 | ||
ad5fd922 JC |
1447 | mmc_set_clock(mmc, mmc->tran_speed); |
1448 | ||
5af8f45c AG |
1449 | /* Fix the block length for DDR mode */ |
1450 | if (mmc->ddr_mode) { | |
1451 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
1452 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
1453 | } | |
1454 | ||
272cc70b AF |
1455 | /* fill in device description */ |
1456 | mmc->block_dev.lun = 0; | |
1457 | mmc->block_dev.type = 0; | |
1458 | mmc->block_dev.blksz = mmc->read_bl_len; | |
0472fbfd | 1459 | mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); |
9b1f942c | 1460 | mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); |
56196826 | 1461 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
babce5f6 TH |
1462 | sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", |
1463 | mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), | |
1464 | (mmc->cid[3] >> 16) & 0xffff); | |
1465 | sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, | |
1466 | (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, | |
1467 | (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, | |
1468 | (mmc->cid[2] >> 24) & 0xff); | |
1469 | sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, | |
1470 | (mmc->cid[2] >> 16) & 0xf); | |
56196826 PB |
1471 | #else |
1472 | mmc->block_dev.vendor[0] = 0; | |
1473 | mmc->block_dev.product[0] = 0; | |
1474 | mmc->block_dev.revision[0] = 0; | |
1475 | #endif | |
122efd43 | 1476 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) |
272cc70b | 1477 | init_part(&mmc->block_dev); |
122efd43 | 1478 | #endif |
272cc70b AF |
1479 | |
1480 | return 0; | |
1481 | } | |
1482 | ||
fdbb873e | 1483 | static int mmc_send_if_cond(struct mmc *mmc) |
272cc70b AF |
1484 | { |
1485 | struct mmc_cmd cmd; | |
1486 | int err; | |
1487 | ||
1488 | cmd.cmdidx = SD_CMD_SEND_IF_COND; | |
1489 | /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ | |
93bfd616 | 1490 | cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; |
272cc70b | 1491 | cmd.resp_type = MMC_RSP_R7; |
272cc70b AF |
1492 | |
1493 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1494 | ||
1495 | if (err) | |
1496 | return err; | |
1497 | ||
998be3dd | 1498 | if ((cmd.response[0] & 0xff) != 0xaa) |
272cc70b AF |
1499 | return UNUSABLE_ERR; |
1500 | else | |
1501 | mmc->version = SD_VERSION_2; | |
1502 | ||
1503 | return 0; | |
1504 | } | |
1505 | ||
93bfd616 PA |
1506 | /* not used any more */ |
1507 | int __deprecated mmc_register(struct mmc *mmc) | |
1508 | { | |
1509 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) | |
1510 | printf("%s is deprecated! use mmc_create() instead.\n", __func__); | |
1511 | #endif | |
1512 | return -1; | |
1513 | } | |
1514 | ||
1515 | struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) | |
272cc70b | 1516 | { |
93bfd616 PA |
1517 | struct mmc *mmc; |
1518 | ||
1519 | /* quick validation */ | |
1520 | if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || | |
1521 | cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) | |
1522 | return NULL; | |
1523 | ||
1524 | mmc = calloc(1, sizeof(*mmc)); | |
1525 | if (mmc == NULL) | |
1526 | return NULL; | |
1527 | ||
1528 | mmc->cfg = cfg; | |
1529 | mmc->priv = priv; | |
1530 | ||
1531 | /* the following chunk was mmc_register() */ | |
1532 | ||
ab71188c MN |
1533 | /* Setup dsr related values */ |
1534 | mmc->dsr_imp = 0; | |
1535 | mmc->dsr = 0xffffffff; | |
272cc70b AF |
1536 | /* Setup the universal parts of the block interface just once */ |
1537 | mmc->block_dev.if_type = IF_TYPE_MMC; | |
1538 | mmc->block_dev.dev = cur_dev_num++; | |
1539 | mmc->block_dev.removable = 1; | |
1540 | mmc->block_dev.block_read = mmc_bread; | |
1541 | mmc->block_dev.block_write = mmc_bwrite; | |
e6f99a56 | 1542 | mmc->block_dev.block_erase = mmc_berase; |
272cc70b | 1543 | |
93bfd616 PA |
1544 | /* setup initial part type */ |
1545 | mmc->block_dev.part_type = mmc->cfg->part_type; | |
272cc70b | 1546 | |
93bfd616 | 1547 | INIT_LIST_HEAD(&mmc->link); |
272cc70b | 1548 | |
93bfd616 PA |
1549 | list_add_tail(&mmc->link, &mmc_devices); |
1550 | ||
1551 | return mmc; | |
1552 | } | |
1553 | ||
1554 | void mmc_destroy(struct mmc *mmc) | |
1555 | { | |
1556 | /* only freeing memory for now */ | |
1557 | free(mmc); | |
272cc70b AF |
1558 | } |
1559 | ||
df3fc526 | 1560 | #ifdef CONFIG_PARTITIONS |
272cc70b AF |
1561 | block_dev_desc_t *mmc_get_dev(int dev) |
1562 | { | |
1563 | struct mmc *mmc = find_mmc_device(dev); | |
6bb4b4bc | 1564 | if (!mmc || mmc_init(mmc)) |
40242bc3 | 1565 | return NULL; |
272cc70b | 1566 | |
40242bc3 | 1567 | return &mmc->block_dev; |
272cc70b | 1568 | } |
df3fc526 | 1569 | #endif |
272cc70b | 1570 | |
95de9ab2 PK |
1571 | /* board-specific MMC power initializations. */ |
1572 | __weak void board_mmc_power_init(void) | |
1573 | { | |
1574 | } | |
1575 | ||
e9550449 | 1576 | int mmc_start_init(struct mmc *mmc) |
272cc70b | 1577 | { |
afd5932b | 1578 | int err; |
272cc70b | 1579 | |
ab769f22 | 1580 | /* we pretend there's no card when init is NULL */ |
93bfd616 | 1581 | if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { |
48972d90 | 1582 | mmc->has_init = 0; |
56196826 | 1583 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
48972d90 | 1584 | printf("MMC: no card present\n"); |
56196826 | 1585 | #endif |
48972d90 TR |
1586 | return NO_CARD_ERR; |
1587 | } | |
1588 | ||
bc897b1d LW |
1589 | if (mmc->has_init) |
1590 | return 0; | |
1591 | ||
95de9ab2 PK |
1592 | board_mmc_power_init(); |
1593 | ||
ab769f22 | 1594 | /* made sure it's not NULL earlier */ |
93bfd616 | 1595 | err = mmc->cfg->ops->init(mmc); |
272cc70b AF |
1596 | |
1597 | if (err) | |
1598 | return err; | |
1599 | ||
786e8f81 | 1600 | mmc->ddr_mode = 0; |
b86b85e2 IY |
1601 | mmc_set_bus_width(mmc, 1); |
1602 | mmc_set_clock(mmc, 1); | |
1603 | ||
272cc70b AF |
1604 | /* Reset the Card */ |
1605 | err = mmc_go_idle(mmc); | |
1606 | ||
1607 | if (err) | |
1608 | return err; | |
1609 | ||
bc897b1d LW |
1610 | /* The internal partition reset to user partition(0) at every CMD0*/ |
1611 | mmc->part_num = 0; | |
1612 | ||
272cc70b | 1613 | /* Test for SD version 2 */ |
afd5932b | 1614 | err = mmc_send_if_cond(mmc); |
272cc70b | 1615 | |
272cc70b AF |
1616 | /* Now try to get the SD card's operating condition */ |
1617 | err = sd_send_op_cond(mmc); | |
1618 | ||
1619 | /* If the command timed out, we check for an MMC card */ | |
1620 | if (err == TIMEOUT) { | |
1621 | err = mmc_send_op_cond(mmc); | |
1622 | ||
e9550449 | 1623 | if (err && err != IN_PROGRESS) { |
56196826 | 1624 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 1625 | printf("Card did not respond to voltage select!\n"); |
56196826 | 1626 | #endif |
272cc70b AF |
1627 | return UNUSABLE_ERR; |
1628 | } | |
1629 | } | |
1630 | ||
e9550449 CLC |
1631 | if (err == IN_PROGRESS) |
1632 | mmc->init_in_progress = 1; | |
1633 | ||
1634 | return err; | |
1635 | } | |
1636 | ||
1637 | static int mmc_complete_init(struct mmc *mmc) | |
1638 | { | |
1639 | int err = 0; | |
1640 | ||
1641 | if (mmc->op_cond_pending) | |
1642 | err = mmc_complete_op_cond(mmc); | |
1643 | ||
1644 | if (!err) | |
1645 | err = mmc_startup(mmc); | |
bc897b1d LW |
1646 | if (err) |
1647 | mmc->has_init = 0; | |
1648 | else | |
1649 | mmc->has_init = 1; | |
e9550449 CLC |
1650 | mmc->init_in_progress = 0; |
1651 | return err; | |
1652 | } | |
1653 | ||
1654 | int mmc_init(struct mmc *mmc) | |
1655 | { | |
1656 | int err = IN_PROGRESS; | |
d803fea5 | 1657 | unsigned start; |
e9550449 CLC |
1658 | |
1659 | if (mmc->has_init) | |
1660 | return 0; | |
d803fea5 MZ |
1661 | |
1662 | start = get_timer(0); | |
1663 | ||
e9550449 CLC |
1664 | if (!mmc->init_in_progress) |
1665 | err = mmc_start_init(mmc); | |
1666 | ||
1667 | if (!err || err == IN_PROGRESS) | |
1668 | err = mmc_complete_init(mmc); | |
1669 | debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); | |
bc897b1d | 1670 | return err; |
272cc70b AF |
1671 | } |
1672 | ||
ab71188c MN |
1673 | int mmc_set_dsr(struct mmc *mmc, u16 val) |
1674 | { | |
1675 | mmc->dsr = val; | |
1676 | return 0; | |
1677 | } | |
1678 | ||
cee9ab7c JH |
1679 | /* CPU-specific MMC initializations */ |
1680 | __weak int cpu_mmc_init(bd_t *bis) | |
272cc70b AF |
1681 | { |
1682 | return -1; | |
1683 | } | |
1684 | ||
cee9ab7c JH |
1685 | /* board-specific MMC initializations. */ |
1686 | __weak int board_mmc_init(bd_t *bis) | |
1687 | { | |
1688 | return -1; | |
1689 | } | |
272cc70b | 1690 | |
56196826 PB |
1691 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
1692 | ||
272cc70b AF |
1693 | void print_mmc_devices(char separator) |
1694 | { | |
1695 | struct mmc *m; | |
1696 | struct list_head *entry; | |
34dd9284 | 1697 | char *mmc_type; |
272cc70b AF |
1698 | |
1699 | list_for_each(entry, &mmc_devices) { | |
1700 | m = list_entry(entry, struct mmc, link); | |
1701 | ||
34dd9284 PM |
1702 | if (m->has_init) |
1703 | mmc_type = IS_SD(m) ? "SD" : "eMMC"; | |
1704 | else | |
1705 | mmc_type = NULL; | |
1706 | ||
93bfd616 | 1707 | printf("%s: %d", m->cfg->name, m->block_dev.dev); |
34dd9284 PM |
1708 | if (mmc_type) |
1709 | printf(" (%s)", mmc_type); | |
272cc70b | 1710 | |
e75eaf10 LP |
1711 | if (entry->next != &mmc_devices) { |
1712 | printf("%c", separator); | |
1713 | if (separator != '\n') | |
1714 | puts (" "); | |
1715 | } | |
272cc70b AF |
1716 | } |
1717 | ||
1718 | printf("\n"); | |
1719 | } | |
1720 | ||
56196826 PB |
1721 | #else |
1722 | void print_mmc_devices(char separator) { } | |
1723 | #endif | |
1724 | ||
ea6ebe21 LW |
1725 | int get_mmc_num(void) |
1726 | { | |
1727 | return cur_dev_num; | |
1728 | } | |
1729 | ||
e9550449 CLC |
1730 | void mmc_set_preinit(struct mmc *mmc, int preinit) |
1731 | { | |
1732 | mmc->preinit = preinit; | |
1733 | } | |
1734 | ||
1735 | static void do_preinit(void) | |
1736 | { | |
1737 | struct mmc *m; | |
1738 | struct list_head *entry; | |
1739 | ||
1740 | list_for_each(entry, &mmc_devices) { | |
1741 | m = list_entry(entry, struct mmc, link); | |
1742 | ||
1743 | if (m->preinit) | |
1744 | mmc_start_init(m); | |
1745 | } | |
1746 | } | |
1747 | ||
1748 | ||
272cc70b AF |
1749 | int mmc_initialize(bd_t *bis) |
1750 | { | |
1751 | INIT_LIST_HEAD (&mmc_devices); | |
1752 | cur_dev_num = 0; | |
1753 | ||
1754 | if (board_mmc_init(bis) < 0) | |
1755 | cpu_mmc_init(bis); | |
1756 | ||
bb0dc108 | 1757 | #ifndef CONFIG_SPL_BUILD |
272cc70b | 1758 | print_mmc_devices(','); |
bb0dc108 | 1759 | #endif |
272cc70b | 1760 | |
e9550449 | 1761 | do_preinit(); |
272cc70b AF |
1762 | return 0; |
1763 | } | |
3690d6d6 A |
1764 | |
1765 | #ifdef CONFIG_SUPPORT_EMMC_BOOT | |
1766 | /* | |
1767 | * This function changes the size of boot partition and the size of rpmb | |
1768 | * partition present on EMMC devices. | |
1769 | * | |
1770 | * Input Parameters: | |
1771 | * struct *mmc: pointer for the mmc device strcuture | |
1772 | * bootsize: size of boot partition | |
1773 | * rpmbsize: size of rpmb partition | |
1774 | * | |
1775 | * Returns 0 on success. | |
1776 | */ | |
1777 | ||
1778 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
1779 | unsigned long rpmbsize) | |
1780 | { | |
1781 | int err; | |
1782 | struct mmc_cmd cmd; | |
1783 | ||
1784 | /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ | |
1785 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1786 | cmd.resp_type = MMC_RSP_R1b; | |
1787 | cmd.cmdarg = MMC_CMD62_ARG1; | |
1788 | ||
1789 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1790 | if (err) { | |
1791 | debug("mmc_boot_partition_size_change: Error1 = %d\n", err); | |
1792 | return err; | |
1793 | } | |
1794 | ||
1795 | /* Boot partition changing mode */ | |
1796 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1797 | cmd.resp_type = MMC_RSP_R1b; | |
1798 | cmd.cmdarg = MMC_CMD62_ARG2; | |
1799 | ||
1800 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1801 | if (err) { | |
1802 | debug("mmc_boot_partition_size_change: Error2 = %d\n", err); | |
1803 | return err; | |
1804 | } | |
1805 | /* boot partition size is multiple of 128KB */ | |
1806 | bootsize = (bootsize * 1024) / 128; | |
1807 | ||
1808 | /* Arg: boot partition size */ | |
1809 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1810 | cmd.resp_type = MMC_RSP_R1b; | |
1811 | cmd.cmdarg = bootsize; | |
1812 | ||
1813 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1814 | if (err) { | |
1815 | debug("mmc_boot_partition_size_change: Error3 = %d\n", err); | |
1816 | return err; | |
1817 | } | |
1818 | /* RPMB partition size is multiple of 128KB */ | |
1819 | rpmbsize = (rpmbsize * 1024) / 128; | |
1820 | /* Arg: RPMB partition size */ | |
1821 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1822 | cmd.resp_type = MMC_RSP_R1b; | |
1823 | cmd.cmdarg = rpmbsize; | |
1824 | ||
1825 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1826 | if (err) { | |
1827 | debug("mmc_boot_partition_size_change: Error4 = %d\n", err); | |
1828 | return err; | |
1829 | } | |
1830 | return 0; | |
1831 | } | |
1832 | ||
5a99b9de TR |
1833 | /* |
1834 | * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH | |
1835 | * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH | |
1836 | * and BOOT_MODE. | |
1837 | * | |
1838 | * Returns 0 on success. | |
1839 | */ | |
1840 | int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) | |
1841 | { | |
1842 | int err; | |
1843 | ||
1844 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, | |
1845 | EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | | |
1846 | EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | | |
1847 | EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); | |
1848 | ||
1849 | if (err) | |
1850 | return err; | |
1851 | return 0; | |
1852 | } | |
1853 | ||
792970b0 TR |
1854 | /* |
1855 | * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) | |
1856 | * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and | |
1857 | * PARTITION_ACCESS. | |
1858 | * | |
1859 | * Returns 0 on success. | |
1860 | */ | |
1861 | int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) | |
1862 | { | |
1863 | int err; | |
1864 | ||
1865 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, | |
1866 | EXT_CSD_BOOT_ACK(ack) | | |
1867 | EXT_CSD_BOOT_PART_NUM(part_num) | | |
1868 | EXT_CSD_PARTITION_ACCESS(access)); | |
1869 | ||
1870 | if (err) | |
1871 | return err; | |
1872 | return 0; | |
1873 | } | |
33ace362 TR |
1874 | |
1875 | /* | |
1876 | * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value | |
1877 | * for enable. Note that this is a write-once field for non-zero values. | |
1878 | * | |
1879 | * Returns 0 on success. | |
1880 | */ | |
1881 | int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) | |
1882 | { | |
1883 | return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, | |
1884 | enable); | |
1885 | } | |
3690d6d6 | 1886 | #endif |