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i2c: designware: Avoid overwriting the cmd_data register
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
18#include <malloc.h>
cf92e05c 19#include <memalign.h>
272cc70b 20#include <linux/list.h>
9b1f942c 21#include <div64.h>
da61fa5f 22#include "mmc_private.h"
272cc70b 23
3697e599
PF		 24static const unsigned int sd_au_size[] = {
25 0, SZ_16K / 512, SZ_32K / 512,
26 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
27 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
28 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
29 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
30};
31
8ca51e51 32#ifndef CONFIG_DM_MMC_OPS
750121c3 33__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 34{
35 return -1;
36}
37
38int mmc_getwp(struct mmc *mmc)
39{
40 int wp;
41
42 wp = board_mmc_getwp(mmc);
43
d4e1da4e 44 if (wp < 0) {
93bfd616
PA		 45 if (mmc->cfg->ops->getwp)
46 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 47 else
48 wp = 0;
49 }
d23d8d7e
NK		 50
51 return wp;
52}
53
cee9ab7c
JH		 54__weak int board_mmc_getcd(struct mmc *mmc)
55{
11fdade2
SB		 56 return -1;
57}
8ca51e51 58#endif
11fdade2 59
c0c76eba
SG		 60#ifdef CONFIG_MMC_TRACE
61void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 62{
c0c76eba
SG		 63 printf("CMD_SEND:%d\n", cmd->cmdidx);
64 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
65}
8635ff9e 66
c0c76eba
SG		 67void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
68{
5db2fe3a
RR		 69 int i;
70 u8 *ptr;
71
7863ce58
BM		 72 if (ret) {
73 printf("\t\tRET\t\t\t %d\n", ret);
74 } else {
75 switch (cmd->resp_type) {
76 case MMC_RSP_NONE:
77 printf("\t\tMMC_RSP_NONE\n");
78 break;
79 case MMC_RSP_R1:
80 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
81 cmd->response[0]);
82 break;
83 case MMC_RSP_R1b:
84 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
85 cmd->response[0]);
86 break;
87 case MMC_RSP_R2:
88 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
89 cmd->response[0]);
90 printf("\t\t \t\t 0x%08X \n",
91 cmd->response[1]);
92 printf("\t\t \t\t 0x%08X \n",
93 cmd->response[2]);
94 printf("\t\t \t\t 0x%08X \n",
95 cmd->response[3]);
5db2fe3a 96 printf("\n");
7863ce58
BM		 97 printf("\t\t\t\t\tDUMPING DATA\n");
98 for (i = 0; i < 4; i++) {
99 int j;
100 printf("\t\t\t\t\t%03d - ", i*4);
101 ptr = (u8 *)&cmd->response[i];
102 ptr += 3;
103 for (j = 0; j < 4; j++)
104 printf("%02X ", *ptr--);
105 printf("\n");
106 }
107 break;
108 case MMC_RSP_R3:
109 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
110 cmd->response[0]);
111 break;
112 default:
113 printf("\t\tERROR MMC rsp not supported\n");
114 break;
53e8e40b 115 }
5db2fe3a 116 }
c0c76eba
SG		 117}
118
119void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
120{
121 int status;
122
123 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
124 printf("CURR STATE:%d\n", status);
125}
5db2fe3a 126#endif
c0c76eba 127
8ca51e51 128#ifndef CONFIG_DM_MMC_OPS
c0c76eba
SG		 129int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
130{
131 int ret;
132
133 mmmc_trace_before_send(mmc, cmd);
134 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
135 mmmc_trace_after_send(mmc, cmd, ret);
136
8635ff9e 137 return ret;
272cc70b 138}
8ca51e51 139#endif
272cc70b 140
da61fa5f 141int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 142{
143 struct mmc_cmd cmd;
d617c426 144 int err, retries = 5;
5d4fc8d9
RR		 145
146 cmd.cmdidx = MMC_CMD_SEND_STATUS;
147 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 148 if (!mmc_host_is_spi(mmc))
149 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 150
1677eef4 151 while (1) {
5d4fc8d9 152 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 153 if (!err) {
154 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
155 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
156 MMC_STATE_PRG)
157 break;
158 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 159#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 160 printf("Status Error: 0x%08X\n",
161 cmd.response[0]);
56196826 162#endif
915ffa52 163 return -ECOMM;
d617c426
JK		 164 }
165 } else if (--retries < 0)
5d4fc8d9 166 return err;
5d4fc8d9 167
1677eef4
AG		 168 if (timeout-- <= 0)
169 break;
5d4fc8d9 170
1677eef4
AG		 171 udelay(1000);
172 }
5d4fc8d9 173
c0c76eba 174 mmc_trace_state(mmc, &cmd);
5b0c942f 175 if (timeout <= 0) {
56196826 176#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 177 printf("Timeout waiting card ready\n");
56196826 178#endif
915ffa52 179 return -ETIMEDOUT;
5d4fc8d9
RR		 180 }
181
182 return 0;
183}
184
da61fa5f 185int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 186{
187 struct mmc_cmd cmd;
188
786e8f81 189 if (mmc->ddr_mode)
d22e3d46
JC		 190 return 0;
191
272cc70b
AF		 192 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
193 cmd.resp_type = MMC_RSP_R1;
194 cmd.cmdarg = len;
272cc70b
AF		 195
196 return mmc_send_cmd(mmc, &cmd, NULL);
197}
198
ff8fef56 199static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 200 lbaint_t blkcnt)
272cc70b
AF		 201{
202 struct mmc_cmd cmd;
203 struct mmc_data data;
204
4a1a06bc
AS		 205 if (blkcnt > 1)
206 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
207 else
208 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 209
210 if (mmc->high_capacity)
4a1a06bc 211 cmd.cmdarg = start;
272cc70b 212 else
4a1a06bc 213 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 214
215 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 216
217 data.dest = dst;
4a1a06bc 218 data.blocks = blkcnt;
272cc70b
AF		 219 data.blocksize = mmc->read_bl_len;
220 data.flags = MMC_DATA_READ;
221
4a1a06bc
AS		 222 if (mmc_send_cmd(mmc, &cmd, &data))
223 return 0;
272cc70b 224
4a1a06bc
AS		 225 if (blkcnt > 1) {
226 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
227 cmd.cmdarg = 0;
228 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 229 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 230#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 231 printf("mmc fail to send stop cmd\n");
56196826 232#endif
4a1a06bc
AS		 233 return 0;
234 }
272cc70b
AF		 235 }
236
4a1a06bc 237 return blkcnt;
272cc70b
AF		 238}
239
33fb211d 240#ifdef CONFIG_BLK
7dba0b93 241ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 242#else
7dba0b93
SG		 243ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
244 void *dst)
33fb211d 245#endif
272cc70b 246{
33fb211d
SG		 247#ifdef CONFIG_BLK
248 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
249#endif
bcce53d0 250 int dev_num = block_dev->devnum;
873cc1d7 251 int err;
4a1a06bc
AS		 252 lbaint_t cur, blocks_todo = blkcnt;
253
254 if (blkcnt == 0)
255 return 0;
272cc70b 256
4a1a06bc 257 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 258 if (!mmc)
259 return 0;
260
69f45cd5 261 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
873cc1d7
SW		 262 if (err < 0)
263 return 0;
264
c40fdca6 265 if ((start + blkcnt) > block_dev->lba) {
56196826 266#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 267 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
c40fdca6 268 start + blkcnt, block_dev->lba);
56196826 269#endif
d2bf29e3
LW		 270 return 0;
271 }
272cc70b 272
11692991
SG		 273 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
274 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 275 return 0;
11692991 276 }
272cc70b 277
4a1a06bc 278 do {
93bfd616
PA		 279 cur = (blocks_todo > mmc->cfg->b_max) ?
280 mmc->cfg->b_max : blocks_todo;
11692991
SG		 281 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
282 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 283 return 0;
11692991 284 }
4a1a06bc
AS		 285 blocks_todo -= cur;
286 start += cur;
287 dst += cur * mmc->read_bl_len;
288 } while (blocks_todo > 0);
272cc70b
AF		 289
290 return blkcnt;
291}
292
fdbb873e 293static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 294{
295 struct mmc_cmd cmd;
296 int err;
297
298 udelay(1000);
299
300 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
301 cmd.cmdarg = 0;
302 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 303
304 err = mmc_send_cmd(mmc, &cmd, NULL);
305
306 if (err)
307 return err;
308
309 udelay(2000);
310
311 return 0;
312}
313
fdbb873e 314static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF		 315{
316 int timeout = 1000;
317 int err;
318 struct mmc_cmd cmd;
319
1677eef4 320 while (1) {
272cc70b
AF		 321 cmd.cmdidx = MMC_CMD_APP_CMD;
322 cmd.resp_type = MMC_RSP_R1;
323 cmd.cmdarg = 0;
272cc70b
AF		 324
325 err = mmc_send_cmd(mmc, &cmd, NULL);
326
327 if (err)
328 return err;
329
330 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
331 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 332
333 /*
334 * Most cards do not answer if some reserved bits
335 * in the ocr are set. However, Some controller
336 * can set bit 7 (reserved for low voltages), but
337 * how to manage low voltages SD card is not yet
338 * specified.
339 */
d52ebf10 340 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 341 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 342
343 if (mmc->version == SD_VERSION_2)
344 cmd.cmdarg |= OCR_HCS;
345
346 err = mmc_send_cmd(mmc, &cmd, NULL);
347
348 if (err)
349 return err;
350
1677eef4
AG		 351 if (cmd.response[0] & OCR_BUSY)
352 break;
353
354 if (timeout-- <= 0)
915ffa52 355 return -EOPNOTSUPP;
272cc70b 356
1677eef4
AG		 357 udelay(1000);
358 }
272cc70b
AF		 359
360 if (mmc->version != SD_VERSION_2)
361 mmc->version = SD_VERSION_1_0;
362
d52ebf10
TC		 363 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
364 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
365 cmd.resp_type = MMC_RSP_R3;
366 cmd.cmdarg = 0;
d52ebf10
TC		 367
368 err = mmc_send_cmd(mmc, &cmd, NULL);
369
370 if (err)
371 return err;
372 }
373
998be3dd 374 mmc->ocr = cmd.response[0];
272cc70b
AF		 375
376 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
377 mmc->rca = 0;
378
379 return 0;
380}
381
5289b535 382static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 383{
5289b535 384 struct mmc_cmd cmd;
272cc70b
AF		 385 int err;
386
5289b535
AG		 387 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
388 cmd.resp_type = MMC_RSP_R3;
389 cmd.cmdarg = 0;
5a20397b
RH		 390 if (use_arg && !mmc_host_is_spi(mmc))
391 cmd.cmdarg = OCR_HCS |
93bfd616 392 (mmc->cfg->voltages &
a626c8d4
AG		 393 (mmc->ocr & OCR_VOLTAGE_MASK)) |
394 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 395
5289b535 396 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 397 if (err)
398 return err;
5289b535 399 mmc->ocr = cmd.response[0];
e9550449
CLC		 400 return 0;
401}
402
750121c3 403static int mmc_send_op_cond(struct mmc *mmc)
e9550449 404{
e9550449
CLC		 405 int err, i;
406
272cc70b
AF		 407 /* Some cards seem to need this */
408 mmc_go_idle(mmc);
409
31cacbab 410 /* Asking to the card its capabilities */
e9550449 411 for (i = 0; i < 2; i++) {
5289b535 412 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 413 if (err)
414 return err;
cd6881b5 415
e9550449 416 /* exit if not busy (flag seems to be inverted) */
a626c8d4 417 if (mmc->ocr & OCR_BUSY)
bd47c135 418 break;
e9550449 419 }
bd47c135
AG		 420 mmc->op_cond_pending = 1;
421 return 0;
e9550449 422}
cd6881b5 423
750121c3 424static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 425{
426 struct mmc_cmd cmd;
427 int timeout = 1000;
428 uint start;
429 int err;
cd6881b5 430
e9550449 431 mmc->op_cond_pending = 0;
cc17c01f 432 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 433 /* Some cards seem to need this */
434 mmc_go_idle(mmc);
435
cc17c01f 436 start = get_timer(0);
1677eef4 437 while (1) {
cc17c01f
AG		 438 err = mmc_send_op_cond_iter(mmc, 1);
439 if (err)
440 return err;
1677eef4
AG		 441 if (mmc->ocr & OCR_BUSY)
442 break;
cc17c01f 443 if (get_timer(start) > timeout)
915ffa52 444 return -EOPNOTSUPP;
cc17c01f 445 udelay(100);
1677eef4 446 }
cc17c01f 447 }
272cc70b 448
d52ebf10
TC		 449 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
450 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
451 cmd.resp_type = MMC_RSP_R3;
452 cmd.cmdarg = 0;
d52ebf10
TC		 453
454 err = mmc_send_cmd(mmc, &cmd, NULL);
455
456 if (err)
457 return err;
a626c8d4
AG		 458
459 mmc->ocr = cmd.response[0];
d52ebf10
TC		 460 }
461
272cc70b 462 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 463
464 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 465 mmc->rca = 1;
272cc70b
AF		 466
467 return 0;
468}
469
470
fdbb873e 471static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 472{
473 struct mmc_cmd cmd;
474 struct mmc_data data;
475 int err;
476
477 /* Get the Card Status Register */
478 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
479 cmd.resp_type = MMC_RSP_R1;
480 cmd.cmdarg = 0;
272cc70b 481
cdfd1ac6 482 data.dest = (char *)ext_csd;
272cc70b 483 data.blocks = 1;
8bfa195e 484 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 485 data.flags = MMC_DATA_READ;
486
487 err = mmc_send_cmd(mmc, &cmd, &data);
488
489 return err;
490}
491
c40704f4 492int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 493{
494 struct mmc_cmd cmd;
5d4fc8d9
RR		 495 int timeout = 1000;
496 int ret;
272cc70b
AF		 497
498 cmd.cmdidx = MMC_CMD_SWITCH;
499 cmd.resp_type = MMC_RSP_R1b;
500 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 501 (index << 16) |
502 (value << 8);
272cc70b 503
5d4fc8d9
RR		 504 ret = mmc_send_cmd(mmc, &cmd, NULL);
505
506 /* Waiting for the ready status */
93ad0d18
JK		 507 if (!ret)
508 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR		 509
510 return ret;
511
272cc70b
AF		 512}
513
fdbb873e 514static int mmc_change_freq(struct mmc *mmc)
272cc70b 515{
8bfa195e 516 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF		 517 char cardtype;
518 int err;
519
fc5b32fb 520 mmc->card_caps = 0;
272cc70b 521
d52ebf10
TC		 522 if (mmc_host_is_spi(mmc))
523 return 0;
524
272cc70b
AF		 525 /* Only version 4 supports high-speed */
526 if (mmc->version < MMC_VERSION_4)
527 return 0;
528
fc5b32fb
AG		 529 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
530
272cc70b
AF		 531 err = mmc_send_ext_csd(mmc, ext_csd);
532
533 if (err)
534 return err;
535
0560db18 536 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF		 537
538 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
539
540 if (err)
a5e27b41 541 return err;
272cc70b
AF		 542
543 /* Now check to see that it worked */
544 err = mmc_send_ext_csd(mmc, ext_csd);
545
546 if (err)
547 return err;
548
549 /* No high-speed support */
0560db18 550 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF		 551 return 0;
552
553 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 554 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 555 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 556 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 557 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 558 } else {
272cc70b 559 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 560 }
272cc70b
AF		 561
562 return 0;
563}
564
f866a46d
SW		 565static int mmc_set_capacity(struct mmc *mmc, int part_num)
566{
567 switch (part_num) {
568 case 0:
569 mmc->capacity = mmc->capacity_user;
570 break;
571 case 1:
572 case 2:
573 mmc->capacity = mmc->capacity_boot;
574 break;
575 case 3:
576 mmc->capacity = mmc->capacity_rpmb;
577 break;
578 case 4:
579 case 5:
580 case 6:
581 case 7:
582 mmc->capacity = mmc->capacity_gp[part_num - 4];
583 break;
584 default:
585 return -1;
586 }
587
c40fdca6 588 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 589
590 return 0;
591}
592
7dba0b93 593int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 594{
f866a46d 595 int ret;
bc897b1d 596
f866a46d
SW		 597 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
598 (mmc->part_config & ~PART_ACCESS_MASK)
599 | (part_num & PART_ACCESS_MASK));
f866a46d 600
6dc93e70
PB		 601 /*
602 * Set the capacity if the switch succeeded or was intended
603 * to return to representing the raw device.
604 */
873cc1d7 605 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 606 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 607 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 608 }
6dc93e70
PB		 609
610 return ret;
bc897b1d
LW		 611}
612
ac9da0e0
DSC		 613int mmc_hwpart_config(struct mmc *mmc,
614 const struct mmc_hwpart_conf *conf,
615 enum mmc_hwpart_conf_mode mode)
616{
617 u8 part_attrs = 0;
618 u32 enh_size_mult;
619 u32 enh_start_addr;
620 u32 gp_size_mult[4];
621 u32 max_enh_size_mult;
622 u32 tot_enh_size_mult = 0;
8dda5b0e 623 u8 wr_rel_set;
ac9da0e0
DSC		 624 int i, pidx, err;
625 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
626
627 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
628 return -EINVAL;
629
630 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
631 printf("eMMC >= 4.4 required for enhanced user data area\n");
632 return -EMEDIUMTYPE;
633 }
634
635 if (!(mmc->part_support & PART_SUPPORT)) {
636 printf("Card does not support partitioning\n");
637 return -EMEDIUMTYPE;
638 }
639
640 if (!mmc->hc_wp_grp_size) {
641 printf("Card does not define HC WP group size\n");
642 return -EMEDIUMTYPE;
643 }
644
645 /* check partition alignment and total enhanced size */
646 if (conf->user.enh_size) {
647 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
648 conf->user.enh_start % mmc->hc_wp_grp_size) {
649 printf("User data enhanced area not HC WP group "
650 "size aligned\n");
651 return -EINVAL;
652 }
653 part_attrs |= EXT_CSD_ENH_USR;
654 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
655 if (mmc->high_capacity) {
656 enh_start_addr = conf->user.enh_start;
657 } else {
658 enh_start_addr = (conf->user.enh_start << 9);
659 }
660 } else {
661 enh_size_mult = 0;
662 enh_start_addr = 0;
663 }
664 tot_enh_size_mult += enh_size_mult;
665
666 for (pidx = 0; pidx < 4; pidx++) {
667 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
668 printf("GP%i partition not HC WP group size "
669 "aligned\n", pidx+1);
670 return -EINVAL;
671 }
672 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
673 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
674 part_attrs |= EXT_CSD_ENH_GP(pidx);
675 tot_enh_size_mult += gp_size_mult[pidx];
676 }
677 }
678
679 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
680 printf("Card does not support enhanced attribute\n");
681 return -EMEDIUMTYPE;
682 }
683
684 err = mmc_send_ext_csd(mmc, ext_csd);
685 if (err)
686 return err;
687
688 max_enh_size_mult =
689 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
690 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
691 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
692 if (tot_enh_size_mult > max_enh_size_mult) {
693 printf("Total enhanced size exceeds maximum (%u > %u)\n",
694 tot_enh_size_mult, max_enh_size_mult);
695 return -EMEDIUMTYPE;
696 }
697
8dda5b0e
DSC		 698 /* The default value of EXT_CSD_WR_REL_SET is device
699 * dependent, the values can only be changed if the
700 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
701 * changed only once and before partitioning is completed. */
702 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
703 if (conf->user.wr_rel_change) {
704 if (conf->user.wr_rel_set)
705 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
706 else
707 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
708 }
709 for (pidx = 0; pidx < 4; pidx++) {
710 if (conf->gp_part[pidx].wr_rel_change) {
711 if (conf->gp_part[pidx].wr_rel_set)
712 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
713 else
714 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
715 }
716 }
717
718 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
719 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
720 puts("Card does not support host controlled partition write "
721 "reliability settings\n");
722 return -EMEDIUMTYPE;
723 }
724
ac9da0e0
DSC		 725 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
726 EXT_CSD_PARTITION_SETTING_COMPLETED) {
727 printf("Card already partitioned\n");
728 return -EPERM;
729 }
730
731 if (mode == MMC_HWPART_CONF_CHECK)
732 return 0;
733
734 /* Partitioning requires high-capacity size definitions */
735 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
736 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
737 EXT_CSD_ERASE_GROUP_DEF, 1);
738
739 if (err)
740 return err;
741
742 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
743
744 /* update erase group size to be high-capacity */
745 mmc->erase_grp_size =
746 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
747
748 }
749
750 /* all OK, write the configuration */
751 for (i = 0; i < 4; i++) {
752 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
753 EXT_CSD_ENH_START_ADDR+i,
754 (enh_start_addr >> (i*8)) & 0xFF);
755 if (err)
756 return err;
757 }
758 for (i = 0; i < 3; i++) {
759 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
760 EXT_CSD_ENH_SIZE_MULT+i,
761 (enh_size_mult >> (i*8)) & 0xFF);
762 if (err)
763 return err;
764 }
765 for (pidx = 0; pidx < 4; pidx++) {
766 for (i = 0; i < 3; i++) {
767 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
768 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
769 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
770 if (err)
771 return err;
772 }
773 }
774 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
775 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
776 if (err)
777 return err;
778
779 if (mode == MMC_HWPART_CONF_SET)
780 return 0;
781
8dda5b0e
DSC		 782 /* The WR_REL_SET is a write-once register but shall be
783 * written before setting PART_SETTING_COMPLETED. As it is
784 * write-once we can only write it when completing the
785 * partitioning. */
786 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
787 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
788 EXT_CSD_WR_REL_SET, wr_rel_set);
789 if (err)
790 return err;
791 }
792
ac9da0e0
DSC		 793 /* Setting PART_SETTING_COMPLETED confirms the partition
794 * configuration but it only becomes effective after power
795 * cycle, so we do not adjust the partition related settings
796 * in the mmc struct. */
797
798 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
799 EXT_CSD_PARTITION_SETTING,
800 EXT_CSD_PARTITION_SETTING_COMPLETED);
801 if (err)
802 return err;
803
804 return 0;
805}
806
8ca51e51 807#ifndef CONFIG_DM_MMC_OPS
48972d90
TR		 808int mmc_getcd(struct mmc *mmc)
809{
810 int cd;
811
812 cd = board_mmc_getcd(mmc);
813
d4e1da4e 814 if (cd < 0) {
93bfd616
PA		 815 if (mmc->cfg->ops->getcd)
816 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 817 else
818 cd = 1;
819 }
48972d90
TR		 820
821 return cd;
822}
8ca51e51 823#endif
48972d90 824
fdbb873e 825static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 826{
827 struct mmc_cmd cmd;
828 struct mmc_data data;
829
830 /* Switch the frequency */
831 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
832 cmd.resp_type = MMC_RSP_R1;
833 cmd.cmdarg = (mode << 31) | 0xffffff;
834 cmd.cmdarg &= ~(0xf << (group * 4));
835 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 836
837 data.dest = (char *)resp;
838 data.blocksize = 64;
839 data.blocks = 1;
840 data.flags = MMC_DATA_READ;
841
842 return mmc_send_cmd(mmc, &cmd, &data);
843}
844
845
fdbb873e 846static int sd_change_freq(struct mmc *mmc)
272cc70b
AF		 847{
848 int err;
849 struct mmc_cmd cmd;
f781dd38
A		 850 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
851 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF		 852 struct mmc_data data;
853 int timeout;
854
855 mmc->card_caps = 0;
856
d52ebf10
TC		 857 if (mmc_host_is_spi(mmc))
858 return 0;
859
272cc70b
AF		 860 /* Read the SCR to find out if this card supports higher speeds */
861 cmd.cmdidx = MMC_CMD_APP_CMD;
862 cmd.resp_type = MMC_RSP_R1;
863 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 864
865 err = mmc_send_cmd(mmc, &cmd, NULL);
866
867 if (err)
868 return err;
869
870 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
871 cmd.resp_type = MMC_RSP_R1;
872 cmd.cmdarg = 0;
272cc70b
AF		 873
874 timeout = 3;
875
876retry_scr:
f781dd38 877 data.dest = (char *)scr;
272cc70b
AF		 878 data.blocksize = 8;
879 data.blocks = 1;
880 data.flags = MMC_DATA_READ;
881
882 err = mmc_send_cmd(mmc, &cmd, &data);
883
884 if (err) {
885 if (timeout--)
886 goto retry_scr;
887
888 return err;
889 }
890
4e3d89ba
YK		 891 mmc->scr[0] = __be32_to_cpu(scr[0]);
892 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 893
894 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 895 case 0:
896 mmc->version = SD_VERSION_1_0;
897 break;
898 case 1:
899 mmc->version = SD_VERSION_1_10;
900 break;
901 case 2:
902 mmc->version = SD_VERSION_2;
903 if ((mmc->scr[0] >> 15) & 0x1)
904 mmc->version = SD_VERSION_3;
905 break;
906 default:
907 mmc->version = SD_VERSION_1_0;
908 break;
272cc70b
AF		 909 }
910
b44c7083
AS		 911 if (mmc->scr[0] & SD_DATA_4BIT)
912 mmc->card_caps |= MMC_MODE_4BIT;
913
272cc70b
AF		 914 /* Version 1.0 doesn't support switching */
915 if (mmc->version == SD_VERSION_1_0)
916 return 0;
917
918 timeout = 4;
919 while (timeout--) {
920 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 921 (u8 *)switch_status);
272cc70b
AF		 922
923 if (err)
924 return err;
925
926 /* The high-speed function is busy. Try again */
4e3d89ba 927 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 928 break;
929 }
930
272cc70b 931 /* If high-speed isn't supported, we return */
4e3d89ba 932 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF		 933 return 0;
934
2c3fbf4c
ML		 935 /*
936 * If the host doesn't support SD_HIGHSPEED, do not switch card to
937 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
938 * This can avoid furthur problem when the card runs in different
939 * mode between the host.
940 */
93bfd616
PA		 941 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
942 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML		 943 return 0;
944
f781dd38 945 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF		 946
947 if (err)
948 return err;
949
4e3d89ba 950 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF		 951 mmc->card_caps |= MMC_MODE_HS;
952
953 return 0;
954}
955
3697e599
PF		 956static int sd_read_ssr(struct mmc *mmc)
957{
958 int err, i;
959 struct mmc_cmd cmd;
960 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
961 struct mmc_data data;
962 int timeout = 3;
963 unsigned int au, eo, et, es;
964
965 cmd.cmdidx = MMC_CMD_APP_CMD;
966 cmd.resp_type = MMC_RSP_R1;
967 cmd.cmdarg = mmc->rca << 16;
968
969 err = mmc_send_cmd(mmc, &cmd, NULL);
970 if (err)
971 return err;
972
973 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
974 cmd.resp_type = MMC_RSP_R1;
975 cmd.cmdarg = 0;
976
977retry_ssr:
978 data.dest = (char *)ssr;
979 data.blocksize = 64;
980 data.blocks = 1;
981 data.flags = MMC_DATA_READ;
982
983 err = mmc_send_cmd(mmc, &cmd, &data);
984 if (err) {
985 if (timeout--)
986 goto retry_ssr;
987
988 return err;
989 }
990
991 for (i = 0; i < 16; i++)
992 ssr[i] = be32_to_cpu(ssr[i]);
993
994 au = (ssr[2] >> 12) & 0xF;
995 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
996 mmc->ssr.au = sd_au_size[au];
997 es = (ssr[3] >> 24) & 0xFF;
998 es |= (ssr[2] & 0xFF) << 8;
999 et = (ssr[3] >> 18) & 0x3F;
1000 if (es && et) {
1001 eo = (ssr[3] >> 16) & 0x3;
1002 mmc->ssr.erase_timeout = (et * 1000) / es;
1003 mmc->ssr.erase_offset = eo * 1000;
1004 }
1005 } else {
1006 debug("Invalid Allocation Unit Size.\n");
1007 }
1008
1009 return 0;
1010}
1011
272cc70b
AF		 1012/* frequency bases */
1013/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1014static const int fbase[] = {
272cc70b
AF		 1015 10000,
1016 100000,
1017 1000000,
1018 10000000,
1019};
1020
1021/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1022 * to platforms without floating point.
1023 */
61fe076f 1024static const u8 multipliers[] = {
272cc70b
AF		 1025 0, /* reserved */
1026 10,
1027 12,
1028 13,
1029 15,
1030 20,
1031 25,
1032 30,
1033 35,
1034 40,
1035 45,
1036 50,
1037 55,
1038 60,
1039 70,
1040 80,
1041};
1042
8ca51e51 1043#ifndef CONFIG_DM_MMC_OPS
fdbb873e 1044static void mmc_set_ios(struct mmc *mmc)
272cc70b 1045{
93bfd616
PA		 1046 if (mmc->cfg->ops->set_ios)
1047 mmc->cfg->ops->set_ios(mmc);
272cc70b 1048}
8ca51e51 1049#endif
272cc70b
AF		 1050
1051void mmc_set_clock(struct mmc *mmc, uint clock)
1052{
93bfd616
PA		 1053 if (clock > mmc->cfg->f_max)
1054 clock = mmc->cfg->f_max;
272cc70b 1055
93bfd616
PA		 1056 if (clock < mmc->cfg->f_min)
1057 clock = mmc->cfg->f_min;
272cc70b
AF		 1058
1059 mmc->clock = clock;
1060
1061 mmc_set_ios(mmc);
1062}
1063
fdbb873e 1064static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1065{
1066 mmc->bus_width = width;
1067
1068 mmc_set_ios(mmc);
1069}
1070
fdbb873e 1071static int mmc_startup(struct mmc *mmc)
272cc70b 1072{
f866a46d 1073 int err, i;
272cc70b 1074 uint mult, freq;
639b7827 1075 u64 cmult, csize, capacity;
272cc70b 1076 struct mmc_cmd cmd;
8bfa195e
SG		 1077 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1078 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 1079 int timeout = 1000;
0c453bb7 1080 bool has_parts = false;
8a0cf490 1081 bool part_completed;
c40fdca6 1082 struct blk_desc *bdesc;
272cc70b 1083
d52ebf10
TC		 1084#ifdef CONFIG_MMC_SPI_CRC_ON
1085 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1086 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1087 cmd.resp_type = MMC_RSP_R1;
1088 cmd.cmdarg = 1;
d52ebf10
TC		 1089 err = mmc_send_cmd(mmc, &cmd, NULL);
1090
1091 if (err)
1092 return err;
1093 }
1094#endif
1095
272cc70b 1096 /* Put the Card in Identify Mode */
d52ebf10
TC		 1097 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1098 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1099 cmd.resp_type = MMC_RSP_R2;
1100 cmd.cmdarg = 0;
272cc70b
AF		 1101
1102 err = mmc_send_cmd(mmc, &cmd, NULL);
1103
1104 if (err)
1105 return err;
1106
1107 memcpy(mmc->cid, cmd.response, 16);
1108
1109 /*
1110 * For MMC cards, set the Relative Address.
1111 * For SD cards, get the Relatvie Address.
1112 * This also puts the cards into Standby State
1113 */
d52ebf10
TC		 1114 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1115 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1116 cmd.cmdarg = mmc->rca << 16;
1117 cmd.resp_type = MMC_RSP_R6;
272cc70b 1118
d52ebf10 1119 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1120
d52ebf10
TC		 1121 if (err)
1122 return err;
272cc70b 1123
d52ebf10
TC		 1124 if (IS_SD(mmc))
1125 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1126 }
272cc70b
AF		 1127
1128 /* Get the Card-Specific Data */
1129 cmd.cmdidx = MMC_CMD_SEND_CSD;
1130 cmd.resp_type = MMC_RSP_R2;
1131 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1132
1133 err = mmc_send_cmd(mmc, &cmd, NULL);
1134
5d4fc8d9
RR		 1135 /* Waiting for the ready status */
1136 mmc_send_status(mmc, timeout);
1137
272cc70b
AF		 1138 if (err)
1139 return err;
1140
998be3dd
RV		 1141 mmc->csd[0] = cmd.response[0];
1142 mmc->csd[1] = cmd.response[1];
1143 mmc->csd[2] = cmd.response[2];
1144 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1145
1146 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1147 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1148
1149 switch (version) {
53e8e40b
BM		 1150 case 0:
1151 mmc->version = MMC_VERSION_1_2;
1152 break;
1153 case 1:
1154 mmc->version = MMC_VERSION_1_4;
1155 break;
1156 case 2:
1157 mmc->version = MMC_VERSION_2_2;
1158 break;
1159 case 3:
1160 mmc->version = MMC_VERSION_3;
1161 break;
1162 case 4:
1163 mmc->version = MMC_VERSION_4;
1164 break;
1165 default:
1166 mmc->version = MMC_VERSION_1_2;
1167 break;
272cc70b
AF		 1168 }
1169 }
1170
1171 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1172 freq = fbase[(cmd.response[0] & 0x7)];
1173 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF		 1174
1175 mmc->tran_speed = freq * mult;
1176
ab71188c 1177 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1178 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 1179
1180 if (IS_SD(mmc))
1181 mmc->write_bl_len = mmc->read_bl_len;
1182 else
998be3dd 1183 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 1184
1185 if (mmc->high_capacity) {
1186 csize = (mmc->csd[1] & 0x3f) << 16
1187 | (mmc->csd[2] & 0xffff0000) >> 16;
1188 cmult = 8;
1189 } else {
1190 csize = (mmc->csd[1] & 0x3ff) << 2
1191 | (mmc->csd[2] & 0xc0000000) >> 30;
1192 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1193 }
1194
f866a46d
SW		 1195 mmc->capacity_user = (csize + 1) << (cmult + 2);
1196 mmc->capacity_user *= mmc->read_bl_len;
1197 mmc->capacity_boot = 0;
1198 mmc->capacity_rpmb = 0;
1199 for (i = 0; i < 4; i++)
1200 mmc->capacity_gp[i] = 0;
272cc70b 1201
8bfa195e
SG		 1202 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1203 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1204
8bfa195e
SG		 1205 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1206 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1207
ab71188c
MN		 1208 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1209 cmd.cmdidx = MMC_CMD_SET_DSR;
1210 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1211 cmd.resp_type = MMC_RSP_NONE;
1212 if (mmc_send_cmd(mmc, &cmd, NULL))
1213 printf("MMC: SET_DSR failed\n");
1214 }
1215
272cc70b 1216 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 1217 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1218 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1219 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1220 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1221 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1222
d52ebf10
TC		 1223 if (err)
1224 return err;
1225 }
272cc70b 1226
e6f99a56
LW		 1227 /*
1228 * For SD, its erase group is always one sector
1229 */
1230 mmc->erase_grp_size = 1;
bc897b1d 1231 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG		 1232 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1233 /* check ext_csd version and capacity */
1234 err = mmc_send_ext_csd(mmc, ext_csd);
9cf199eb
DSC		 1235 if (err)
1236 return err;
1237 if (ext_csd[EXT_CSD_REV] >= 2) {
639b7827
YS		 1238 /*
1239 * According to the JEDEC Standard, the value of
1240 * ext_csd's capacity is valid if the value is more
1241 * than 2GB
1242 */
0560db18
LW		 1243 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1244 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1245 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1246 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 1247 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 1248 if ((capacity >> 20) > 2 * 1024)
f866a46d 1249 mmc->capacity_user = capacity;
d23e2c09 1250 }
bc897b1d 1251
64f4a619
JC		 1252 switch (ext_csd[EXT_CSD_REV]) {
1253 case 1:
1254 mmc->version = MMC_VERSION_4_1;
1255 break;
1256 case 2:
1257 mmc->version = MMC_VERSION_4_2;
1258 break;
1259 case 3:
1260 mmc->version = MMC_VERSION_4_3;
1261 break;
1262 case 5:
1263 mmc->version = MMC_VERSION_4_41;
1264 break;
1265 case 6:
1266 mmc->version = MMC_VERSION_4_5;
1267 break;
edab723b
MN		 1268 case 7:
1269 mmc->version = MMC_VERSION_5_0;
1270 break;
1a3619cf
SW		 1271 case 8:
1272 mmc->version = MMC_VERSION_5_1;
1273 break;
64f4a619
JC		 1274 }
1275
8a0cf490
DSC		 1276 /* The partition data may be non-zero but it is only
1277 * effective if PARTITION_SETTING_COMPLETED is set in
1278 * EXT_CSD, so ignore any data if this bit is not set,
1279 * except for enabling the high-capacity group size
1280 * definition (see below). */
1281 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1282 EXT_CSD_PARTITION_SETTING_COMPLETED);
1283
0c453bb7
DSC		 1284 /* store the partition info of emmc */
1285 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1286 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1287 ext_csd[EXT_CSD_BOOT_MULT])
1288 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
8a0cf490
DSC		 1289 if (part_completed &&
1290 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
0c453bb7
DSC		 1291 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1292
1293 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1294
1295 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1296
1297 for (i = 0; i < 4; i++) {
1298 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
8a0cf490 1299 uint mult = (ext_csd[idx + 2] << 16) +
0c453bb7 1300 (ext_csd[idx + 1] << 8) + ext_csd[idx];
8a0cf490
DSC		 1301 if (mult)
1302 has_parts = true;
1303 if (!part_completed)
1304 continue;
1305 mmc->capacity_gp[i] = mult;
0c453bb7
DSC		 1306 mmc->capacity_gp[i] *=
1307 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1308 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
f8e89d67 1309 mmc->capacity_gp[i] <<= 19;
0c453bb7
DSC		 1310 }
1311
8a0cf490
DSC		 1312 if (part_completed) {
1313 mmc->enh_user_size =
1314 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1315 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1316 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1317 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1318 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1319 mmc->enh_user_size <<= 19;
1320 mmc->enh_user_start =
1321 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1322 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1323 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1324 ext_csd[EXT_CSD_ENH_START_ADDR];
1325 if (mmc->high_capacity)
1326 mmc->enh_user_start <<= 9;
1327 }
a7f852b6 1328
e6f99a56 1329 /*
1937e5aa
OM		 1330 * Host needs to enable ERASE_GRP_DEF bit if device is
1331 * partitioned. This bit will be lost every time after a reset
1332 * or power off. This will affect erase size.
e6f99a56 1333 */
8a0cf490 1334 if (part_completed)
0c453bb7 1335 has_parts = true;
1937e5aa 1336 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC		 1337 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1338 has_parts = true;
1339 if (has_parts) {
1937e5aa
OM		 1340 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1341 EXT_CSD_ERASE_GROUP_DEF, 1);
1342
1343 if (err)
1344 return err;
021a8055
HP		 1345 else
1346 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
037dc0ab 1347 }
1937e5aa 1348
037dc0ab 1349 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1937e5aa 1350 /* Read out group size from ext_csd */
0560db18 1351 mmc->erase_grp_size =
a4ff9f83 1352 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
d7b29129
MN		 1353 /*
1354 * if high capacity and partition setting completed
1355 * SEC_COUNT is valid even if it is smaller than 2 GiB
1356 * JEDEC Standard JESD84-B45, 6.2.4
1357 */
8a0cf490 1358 if (mmc->high_capacity && part_completed) {
d7b29129
MN		 1359 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1360 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1361 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1362 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1363 capacity *= MMC_MAX_BLOCK_LEN;
1364 mmc->capacity_user = capacity;
1365 }
8bfa195e 1366 } else {
1937e5aa 1367 /* Calculate the group size from the csd value. */
e6f99a56
LW		 1368 int erase_gsz, erase_gmul;
1369 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1370 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1371 mmc->erase_grp_size = (erase_gsz + 1)
1372 * (erase_gmul + 1);
1373 }
037dc0ab
DSC		 1374
1375 mmc->hc_wp_grp_size = 1024
1376 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1377 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
9e41a00b
DSC		 1378
1379 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
d23e2c09
SG		 1380 }
1381
c40fdca6 1382 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 1383 if (err)
1384 return err;
1385
272cc70b
AF		 1386 if (IS_SD(mmc))
1387 err = sd_change_freq(mmc);
1388 else
1389 err = mmc_change_freq(mmc);
1390
1391 if (err)
1392 return err;
1393
1394 /* Restrict card's capabilities by what the host can do */
93bfd616 1395 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF		 1396
1397 if (IS_SD(mmc)) {
1398 if (mmc->card_caps & MMC_MODE_4BIT) {
1399 cmd.cmdidx = MMC_CMD_APP_CMD;
1400 cmd.resp_type = MMC_RSP_R1;
1401 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1402
1403 err = mmc_send_cmd(mmc, &cmd, NULL);
1404 if (err)
1405 return err;
1406
1407 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1408 cmd.resp_type = MMC_RSP_R1;
1409 cmd.cmdarg = 2;
272cc70b
AF		 1410 err = mmc_send_cmd(mmc, &cmd, NULL);
1411 if (err)
1412 return err;
1413
1414 mmc_set_bus_width(mmc, 4);
1415 }
1416
3697e599
PF		 1417 err = sd_read_ssr(mmc);
1418 if (err)
1419 return err;
1420
272cc70b 1421 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1422 mmc->tran_speed = 50000000;
272cc70b 1423 else
ad5fd922 1424 mmc->tran_speed = 25000000;
fc5b32fb
AG		 1425 } else if (mmc->version >= MMC_VERSION_4) {
1426 /* Only version 4 of MMC supports wider bus widths */
7798f6db
AF		 1427 int idx;
1428
1429 /* An array of possible bus widths in order of preference */
1430 static unsigned ext_csd_bits[] = {
d22e3d46
JC		 1431 EXT_CSD_DDR_BUS_WIDTH_8,
1432 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF		 1433 EXT_CSD_BUS_WIDTH_8,
1434 EXT_CSD_BUS_WIDTH_4,
1435 EXT_CSD_BUS_WIDTH_1,
1436 };
1437
1438 /* An array to map CSD bus widths to host cap bits */
1439 static unsigned ext_to_hostcaps[] = {
786e8f81
AG		 1440 [EXT_CSD_DDR_BUS_WIDTH_4] =
1441 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1442 [EXT_CSD_DDR_BUS_WIDTH_8] =
1443 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF		 1444 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1445 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1446 };
1447
1448 /* An array to map chosen bus width to an integer */
1449 static unsigned widths[] = {
d22e3d46 1450 8, 4, 8, 4, 1,
7798f6db
AF		 1451 };
1452
1453 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1454 unsigned int extw = ext_csd_bits[idx];
786e8f81 1455 unsigned int caps = ext_to_hostcaps[extw];
7798f6db 1456
bf477073
AG		 1457 /*
1458 * If the bus width is still not changed,
1459 * don't try to set the default again.
1460 * Otherwise, recover from switch attempts
1461 * by switching to 1-bit bus width.
1462 */
1463 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1464 mmc->bus_width == 1) {
1465 err = 0;
1466 break;
1467 }
1468
7798f6db 1469 /*
786e8f81
AG		 1470 * Check to make sure the card and controller support
1471 * these capabilities
7798f6db 1472 */
786e8f81 1473 if ((mmc->card_caps & caps) != caps)
7798f6db
AF		 1474 continue;
1475
272cc70b 1476 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1477 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF		 1478
1479 if (err)
4137894e 1480 continue;
272cc70b 1481
786e8f81 1482 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1483 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW		 1484
1485 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG		 1486
1487 if (err)
1488 continue;
1489
786a27b7 1490 /* Only compare read only fields */
786e8f81
AG		 1491 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1492 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1493 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1494 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1495 ext_csd[EXT_CSD_REV]
1496 == test_csd[EXT_CSD_REV] &&
1497 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1498 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1499 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1500 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1501 break;
786e8f81 1502 else
915ffa52 1503 err = -EBADMSG;
272cc70b
AF		 1504 }
1505
786e8f81
AG		 1506 if (err)
1507 return err;
1508
272cc70b
AF		 1509 if (mmc->card_caps & MMC_MODE_HS) {
1510 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1511 mmc->tran_speed = 52000000;
272cc70b 1512 else
ad5fd922
JC		 1513 mmc->tran_speed = 26000000;
1514 }
272cc70b
AF		 1515 }
1516
ad5fd922
JC		 1517 mmc_set_clock(mmc, mmc->tran_speed);
1518
5af8f45c
AG		 1519 /* Fix the block length for DDR mode */
1520 if (mmc->ddr_mode) {
1521 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1522 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1523 }
1524
272cc70b 1525 /* fill in device description */
c40fdca6
SG		 1526 bdesc = mmc_get_blk_desc(mmc);
1527 bdesc->lun = 0;
1528 bdesc->hwpart = 0;
1529 bdesc->type = 0;
1530 bdesc->blksz = mmc->read_bl_len;
1531 bdesc->log2blksz = LOG2(bdesc->blksz);
1532 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 1533#if !defined(CONFIG_SPL_BUILD) || \
1534 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1535 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 1536 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 1537 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1538 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 1539 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 1540 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1541 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1542 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 1543 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 1544 (mmc->cid[2] >> 16) & 0xf);
56196826 1545#else
c40fdca6
SG		 1546 bdesc->vendor[0] = 0;
1547 bdesc->product[0] = 0;
1548 bdesc->revision[0] = 0;
56196826 1549#endif
122efd43 1550#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
c40fdca6 1551 part_init(bdesc);
122efd43 1552#endif
272cc70b
AF		 1553
1554 return 0;
1555}
1556
fdbb873e 1557static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 1558{
1559 struct mmc_cmd cmd;
1560 int err;
1561
1562 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1563 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1564 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1565 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 1566
1567 err = mmc_send_cmd(mmc, &cmd, NULL);
1568
1569 if (err)
1570 return err;
1571
998be3dd 1572 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 1573 return -EOPNOTSUPP;
272cc70b
AF		 1574 else
1575 mmc->version = SD_VERSION_2;
1576
1577 return 0;
1578}
1579
95de9ab2
PK		 1580/* board-specific MMC power initializations. */
1581__weak void board_mmc_power_init(void)
1582{
1583}
1584
e9550449 1585int mmc_start_init(struct mmc *mmc)
272cc70b 1586{
8ca51e51 1587 bool no_card;
afd5932b 1588 int err;
272cc70b 1589
ab769f22 1590 /* we pretend there's no card when init is NULL */
8ca51e51
SG		 1591 no_card = mmc_getcd(mmc) == 0;
1592#ifndef CONFIG_DM_MMC_OPS
1593 no_card = no_card || (mmc->cfg->ops->init == NULL);
1594#endif
1595 if (no_card) {
48972d90 1596 mmc->has_init = 0;
56196826 1597#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1598 printf("MMC: no card present\n");
56196826 1599#endif
915ffa52 1600 return -ENOMEDIUM;
48972d90
TR		 1601 }
1602
bc897b1d
LW		 1603 if (mmc->has_init)
1604 return 0;
1605
5a8dbdc6
YL		 1606#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1607 mmc_adapter_card_type_ident();
1608#endif
95de9ab2
PK		 1609 board_mmc_power_init();
1610
8ca51e51
SG		 1611#ifdef CONFIG_DM_MMC_OPS
1612 /* The device has already been probed ready for use */
1613#else
ab769f22 1614 /* made sure it's not NULL earlier */
93bfd616 1615 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 1616 if (err)
1617 return err;
8ca51e51 1618#endif
786e8f81 1619 mmc->ddr_mode = 0;
b86b85e2
IY		 1620 mmc_set_bus_width(mmc, 1);
1621 mmc_set_clock(mmc, 1);
1622
272cc70b
AF		 1623 /* Reset the Card */
1624 err = mmc_go_idle(mmc);
1625
1626 if (err)
1627 return err;
1628
bc897b1d 1629 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 1630 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 1631
272cc70b 1632 /* Test for SD version 2 */
afd5932b 1633 err = mmc_send_if_cond(mmc);
272cc70b 1634
272cc70b
AF		 1635 /* Now try to get the SD card's operating condition */
1636 err = sd_send_op_cond(mmc);
1637
1638 /* If the command timed out, we check for an MMC card */
915ffa52 1639 if (err == -ETIMEDOUT) {
272cc70b
AF		 1640 err = mmc_send_op_cond(mmc);
1641
bd47c135 1642 if (err) {
56196826 1643#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1644 printf("Card did not respond to voltage select!\n");
56196826 1645#endif
915ffa52 1646 return -EOPNOTSUPP;
272cc70b
AF		 1647 }
1648 }
1649
bd47c135 1650 if (!err)
e9550449
CLC		 1651 mmc->init_in_progress = 1;
1652
1653 return err;
1654}
1655
1656static int mmc_complete_init(struct mmc *mmc)
1657{
1658 int err = 0;
1659
bd47c135 1660 mmc->init_in_progress = 0;
e9550449
CLC		 1661 if (mmc->op_cond_pending)
1662 err = mmc_complete_op_cond(mmc);
1663
1664 if (!err)
1665 err = mmc_startup(mmc);
bc897b1d
LW		 1666 if (err)
1667 mmc->has_init = 0;
1668 else
1669 mmc->has_init = 1;
e9550449
CLC		 1670 return err;
1671}
1672
1673int mmc_init(struct mmc *mmc)
1674{
bd47c135 1675 int err = 0;
d803fea5 1676 unsigned start;
33fb211d
SG		 1677#ifdef CONFIG_DM_MMC
1678 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 1679
33fb211d
SG		 1680 upriv->mmc = mmc;
1681#endif
e9550449
CLC		 1682 if (mmc->has_init)
1683 return 0;
d803fea5
MZ		 1684
1685 start = get_timer(0);
1686
e9550449
CLC		 1687 if (!mmc->init_in_progress)
1688 err = mmc_start_init(mmc);
1689
bd47c135 1690 if (!err)
e9550449
CLC		 1691 err = mmc_complete_init(mmc);
1692 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1693 return err;
272cc70b
AF		 1694}
1695
ab71188c
MN		 1696int mmc_set_dsr(struct mmc *mmc, u16 val)
1697{
1698 mmc->dsr = val;
1699 return 0;
1700}
1701
cee9ab7c
JH		 1702/* CPU-specific MMC initializations */
1703__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 1704{
1705 return -1;
1706}
1707
cee9ab7c
JH		 1708/* board-specific MMC initializations. */
1709__weak int board_mmc_init(bd_t *bis)
1710{
1711 return -1;
1712}
272cc70b 1713
e9550449
CLC		 1714void mmc_set_preinit(struct mmc *mmc, int preinit)
1715{
1716 mmc->preinit = preinit;
1717}
1718
8e3332e2
SS		 1719#if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1720static int mmc_probe(bd_t *bis)
1721{
1722 return 0;
1723}
1724#elif defined(CONFIG_DM_MMC)
1725static int mmc_probe(bd_t *bis)
1726{
4a1db6d8 1727 int ret, i;
8e3332e2 1728 struct uclass *uc;
4a1db6d8 1729 struct udevice *dev;
8e3332e2
SS		 1730
1731 ret = uclass_get(UCLASS_MMC, &uc);
1732 if (ret)
1733 return ret;
1734
4a1db6d8
SG		 1735 /*
1736 * Try to add them in sequence order. Really with driver model we
1737 * should allow holes, but the current MMC list does not allow that.
1738 * So if we request 0, 1, 3 we will get 0, 1, 2.
1739 */
1740 for (i = 0; ; i++) {
1741 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1742 if (ret == -ENODEV)
1743 break;
1744 }
1745 uclass_foreach_dev(dev, uc) {
1746 ret = device_probe(dev);
8e3332e2 1747 if (ret)
4a1db6d8 1748 printf("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 1749 }
1750
1751 return 0;
1752}
1753#else
1754static int mmc_probe(bd_t *bis)
1755{
1756 if (board_mmc_init(bis) < 0)
1757 cpu_mmc_init(bis);
1758
1759 return 0;
1760}
1761#endif
e9550449 1762
272cc70b
AF		 1763int mmc_initialize(bd_t *bis)
1764{
1b26bab1 1765 static int initialized = 0;
8e3332e2 1766 int ret;
1b26bab1
DK		 1767 if (initialized) /* Avoid initializing mmc multiple times */
1768 return 0;
1769 initialized = 1;
1770
c40fdca6
SG		 1771#ifndef CONFIG_BLK
1772 mmc_list_init();
1773#endif
8e3332e2
SS		 1774 ret = mmc_probe(bis);
1775 if (ret)
1776 return ret;
272cc70b 1777
bb0dc108 1778#ifndef CONFIG_SPL_BUILD
272cc70b 1779 print_mmc_devices(',');
bb0dc108 1780#endif
272cc70b 1781
c40fdca6 1782 mmc_do_preinit();
272cc70b
AF		 1783 return 0;
1784}
"Das U-Boot" Source Tree