]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mmc/mmc.c
mmc: add mmc hwpartition sub-command to do eMMC hardware partitioning
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF
1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF
8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
d4622df3 13#include <errno.h>
272cc70b
AF
14#include <mmc.h>
15#include <part.h>
16#include <malloc.h>
17#include <linux/list.h>
9b1f942c 18#include <div64.h>
da61fa5f 19#include "mmc_private.h"
272cc70b
AF
20
21static struct list_head mmc_devices;
22static int cur_dev_num = -1;
23
750121c3 24__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK
25{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
d4e1da4e 35 if (wp < 0) {
93bfd616
PA
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK
38 else
39 wp = 0;
40 }
d23d8d7e
NK
41
42 return wp;
43}
44
cee9ab7c
JH
45__weak int board_mmc_getcd(struct mmc *mmc)
46{
11fdade2
SB
47 return -1;
48}
49
da61fa5f 50int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 51{
5db2fe3a 52 int ret;
8635ff9e 53
8635ff9e 54#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR
55 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR
61 switch (cmd->resp_type) {
62 case MMC_RSP_NONE:
63 printf("\t\tMMC_RSP_NONE\n");
64 break;
65 case MMC_RSP_R1:
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
67 cmd->response[0]);
68 break;
69 case MMC_RSP_R1b:
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
71 cmd->response[0]);
72 break;
73 case MMC_RSP_R2:
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
75 cmd->response[0]);
76 printf("\t\t \t\t 0x%08X \n",
77 cmd->response[1]);
78 printf("\t\t \t\t 0x%08X \n",
79 cmd->response[2]);
80 printf("\t\t \t\t 0x%08X \n",
81 cmd->response[3]);
82 printf("\n");
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
85 int j;
86 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 87 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR
88 ptr += 3;
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
91 printf("\n");
92 }
93 break;
94 case MMC_RSP_R3:
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
96 cmd->response[0]);
97 break;
98 default:
99 printf("\t\tERROR MMC rsp not supported\n");
100 break;
101 }
5db2fe3a 102#else
93bfd616 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 104#endif
8635ff9e 105 return ret;
272cc70b
AF
106}
107
da61fa5f 108int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR
109{
110 struct mmc_cmd cmd;
d617c426 111 int err, retries = 5;
5d4fc8d9
RR
112#ifdef CONFIG_MMC_TRACE
113 int status;
114#endif
115
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV
118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9
RR
120
121 do {
122 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK
123 if (!err) {
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
126 MMC_STATE_PRG)
127 break;
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK
130 printf("Status Error: 0x%08X\n",
131 cmd.response[0]);
56196826 132#endif
d617c426
JK
133 return COMM_ERR;
134 }
135 } else if (--retries < 0)
5d4fc8d9 136 return err;
5d4fc8d9
RR
137
138 udelay(1000);
139
5d4fc8d9
RR
140 } while (timeout--);
141
5db2fe3a
RR
142#ifdef CONFIG_MMC_TRACE
143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
144 printf("CURR STATE:%d\n", status);
145#endif
5b0c942f 146 if (timeout <= 0) {
56196826 147#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 148 printf("Timeout waiting card ready\n");
56196826 149#endif
5d4fc8d9
RR
150 return TIMEOUT;
151 }
6b2221b0
AG
152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
153 return SWITCH_ERR;
5d4fc8d9
RR
154
155 return 0;
156}
157
da61fa5f 158int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF
159{
160 struct mmc_cmd cmd;
161
786e8f81 162 if (mmc->ddr_mode)
d22e3d46
JC
163 return 0;
164
272cc70b
AF
165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
166 cmd.resp_type = MMC_RSP_R1;
167 cmd.cmdarg = len;
272cc70b
AF
168
169 return mmc_send_cmd(mmc, &cmd, NULL);
170}
171
172struct mmc *find_mmc_device(int dev_num)
173{
174 struct mmc *m;
175 struct list_head *entry;
176
177 list_for_each(entry, &mmc_devices) {
178 m = list_entry(entry, struct mmc, link);
179
180 if (m->block_dev.dev == dev_num)
181 return m;
182 }
183
56196826 184#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 185 printf("MMC Device %d not found\n", dev_num);
56196826 186#endif
272cc70b
AF
187
188 return NULL;
189}
190
ff8fef56 191static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 192 lbaint_t blkcnt)
272cc70b
AF
193{
194 struct mmc_cmd cmd;
195 struct mmc_data data;
196
4a1a06bc
AS
197 if (blkcnt > 1)
198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
199 else
200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF
201
202 if (mmc->high_capacity)
4a1a06bc 203 cmd.cmdarg = start;
272cc70b 204 else
4a1a06bc 205 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF
206
207 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF
208
209 data.dest = dst;
4a1a06bc 210 data.blocks = blkcnt;
272cc70b
AF
211 data.blocksize = mmc->read_bl_len;
212 data.flags = MMC_DATA_READ;
213
4a1a06bc
AS
214 if (mmc_send_cmd(mmc, &cmd, &data))
215 return 0;
272cc70b 216
4a1a06bc
AS
217 if (blkcnt > 1) {
218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
219 cmd.cmdarg = 0;
220 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 221 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 222#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 223 printf("mmc fail to send stop cmd\n");
56196826 224#endif
4a1a06bc
AS
225 return 0;
226 }
272cc70b
AF
227 }
228
4a1a06bc 229 return blkcnt;
272cc70b
AF
230}
231
ff8fef56 232static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 233{
4a1a06bc
AS
234 lbaint_t cur, blocks_todo = blkcnt;
235
236 if (blkcnt == 0)
237 return 0;
272cc70b 238
4a1a06bc 239 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF
240 if (!mmc)
241 return 0;
242
d2bf29e3 243 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 244#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 246 start + blkcnt, mmc->block_dev.lba);
56196826 247#endif
d2bf29e3
LW
248 return 0;
249 }
272cc70b 250
4a1a06bc 251 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 252 return 0;
272cc70b 253
4a1a06bc 254 do {
93bfd616
PA
255 cur = (blocks_todo > mmc->cfg->b_max) ?
256 mmc->cfg->b_max : blocks_todo;
4a1a06bc
AS
257 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
258 return 0;
259 blocks_todo -= cur;
260 start += cur;
261 dst += cur * mmc->read_bl_len;
262 } while (blocks_todo > 0);
272cc70b
AF
263
264 return blkcnt;
265}
266
fdbb873e 267static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF
268{
269 struct mmc_cmd cmd;
270 int err;
271
272 udelay(1000);
273
274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
275 cmd.cmdarg = 0;
276 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF
277
278 err = mmc_send_cmd(mmc, &cmd, NULL);
279
280 if (err)
281 return err;
282
283 udelay(2000);
284
285 return 0;
286}
287
fdbb873e 288static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF
289{
290 int timeout = 1000;
291 int err;
292 struct mmc_cmd cmd;
293
294 do {
295 cmd.cmdidx = MMC_CMD_APP_CMD;
296 cmd.resp_type = MMC_RSP_R1;
297 cmd.cmdarg = 0;
272cc70b
AF
298
299 err = mmc_send_cmd(mmc, &cmd, NULL);
300
301 if (err)
302 return err;
303
304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
305 cmd.resp_type = MMC_RSP_R3;
250de12b
SB
306
307 /*
308 * Most cards do not answer if some reserved bits
309 * in the ocr are set. However, Some controller
310 * can set bit 7 (reserved for low voltages), but
311 * how to manage low voltages SD card is not yet
312 * specified.
313 */
d52ebf10 314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 315 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF
316
317 if (mmc->version == SD_VERSION_2)
318 cmd.cmdarg |= OCR_HCS;
319
320 err = mmc_send_cmd(mmc, &cmd, NULL);
321
322 if (err)
323 return err;
324
325 udelay(1000);
326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
327
328 if (timeout <= 0)
329 return UNUSABLE_ERR;
330
331 if (mmc->version != SD_VERSION_2)
332 mmc->version = SD_VERSION_1_0;
333
d52ebf10
TC
334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
336 cmd.resp_type = MMC_RSP_R3;
337 cmd.cmdarg = 0;
d52ebf10
TC
338
339 err = mmc_send_cmd(mmc, &cmd, NULL);
340
341 if (err)
342 return err;
343 }
344
998be3dd 345 mmc->ocr = cmd.response[0];
272cc70b
AF
346
347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
348 mmc->rca = 0;
349
350 return 0;
351}
352
e9550449
CLC
353/* We pass in the cmd since otherwise the init seems to fail */
354static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
355 int use_arg)
272cc70b 356{
272cc70b
AF
357 int err;
358
e9550449
CLC
359 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
360 cmd->resp_type = MMC_RSP_R3;
361 cmd->cmdarg = 0;
362 if (use_arg && !mmc_host_is_spi(mmc)) {
363 cmd->cmdarg =
93bfd616 364 (mmc->cfg->voltages &
e9550449
CLC
365 (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
366 (mmc->op_cond_response & OCR_ACCESS_MODE);
367
93bfd616 368 if (mmc->cfg->host_caps & MMC_MODE_HC)
e9550449
CLC
369 cmd->cmdarg |= OCR_HCS;
370 }
371 err = mmc_send_cmd(mmc, cmd, NULL);
372 if (err)
373 return err;
374 mmc->op_cond_response = cmd->response[0];
375 return 0;
376}
377
750121c3 378static int mmc_send_op_cond(struct mmc *mmc)
e9550449
CLC
379{
380 struct mmc_cmd cmd;
381 int err, i;
382
272cc70b
AF
383 /* Some cards seem to need this */
384 mmc_go_idle(mmc);
385
31cacbab 386 /* Asking to the card its capabilities */
e9550449
CLC
387 mmc->op_cond_pending = 1;
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
390 if (err)
391 return err;
cd6881b5 392
e9550449
CLC
393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->op_cond_response & OCR_BUSY)
395 return 0;
396 }
397 return IN_PROGRESS;
398}
cd6881b5 399
750121c3 400static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC
401{
402 struct mmc_cmd cmd;
403 int timeout = 1000;
404 uint start;
405 int err;
cd6881b5 406
e9550449
CLC
407 mmc->op_cond_pending = 0;
408 start = get_timer(0);
272cc70b 409 do {
e9550449 410 err = mmc_send_op_cond_iter(mmc, &cmd, 1);
272cc70b
AF
411 if (err)
412 return err;
e9550449
CLC
413 if (get_timer(start) > timeout)
414 return UNUSABLE_ERR;
415 udelay(100);
416 } while (!(mmc->op_cond_response & OCR_BUSY));
272cc70b 417
d52ebf10
TC
418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
421 cmd.cmdarg = 0;
d52ebf10
TC
422
423 err = mmc_send_cmd(mmc, &cmd, NULL);
424
425 if (err)
426 return err;
427 }
428
272cc70b 429 mmc->version = MMC_VERSION_UNKNOWN;
998be3dd 430 mmc->ocr = cmd.response[0];
272cc70b
AF
431
432 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 433 mmc->rca = 1;
272cc70b
AF
434
435 return 0;
436}
437
438
fdbb873e 439static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF
440{
441 struct mmc_cmd cmd;
442 struct mmc_data data;
443 int err;
444
445 /* Get the Card Status Register */
446 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
447 cmd.resp_type = MMC_RSP_R1;
448 cmd.cmdarg = 0;
272cc70b 449
cdfd1ac6 450 data.dest = (char *)ext_csd;
272cc70b 451 data.blocks = 1;
8bfa195e 452 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF
453 data.flags = MMC_DATA_READ;
454
455 err = mmc_send_cmd(mmc, &cmd, &data);
456
457 return err;
458}
459
460
fdbb873e 461static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF
462{
463 struct mmc_cmd cmd;
5d4fc8d9
RR
464 int timeout = 1000;
465 int ret;
272cc70b
AF
466
467 cmd.cmdidx = MMC_CMD_SWITCH;
468 cmd.resp_type = MMC_RSP_R1b;
469 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR
470 (index << 16) |
471 (value << 8);
272cc70b 472
5d4fc8d9
RR
473 ret = mmc_send_cmd(mmc, &cmd, NULL);
474
475 /* Waiting for the ready status */
93ad0d18
JK
476 if (!ret)
477 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR
478
479 return ret;
480
272cc70b
AF
481}
482
fdbb873e 483static int mmc_change_freq(struct mmc *mmc)
272cc70b 484{
8bfa195e 485 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF
486 char cardtype;
487 int err;
488
786e8f81 489 mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 490
d52ebf10
TC
491 if (mmc_host_is_spi(mmc))
492 return 0;
493
272cc70b
AF
494 /* Only version 4 supports high-speed */
495 if (mmc->version < MMC_VERSION_4)
496 return 0;
497
272cc70b
AF
498 err = mmc_send_ext_csd(mmc, ext_csd);
499
500 if (err)
501 return err;
502
0560db18 503 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF
504
505 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
506
507 if (err)
6b2221b0 508 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF
509
510 /* Now check to see that it worked */
511 err = mmc_send_ext_csd(mmc, ext_csd);
512
513 if (err)
514 return err;
515
516 /* No high-speed support */
0560db18 517 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF
518 return 0;
519
520 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 521 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 522 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 523 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 524 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 525 } else {
272cc70b 526 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 527 }
272cc70b
AF
528
529 return 0;
530}
531
f866a46d
SW
532static int mmc_set_capacity(struct mmc *mmc, int part_num)
533{
534 switch (part_num) {
535 case 0:
536 mmc->capacity = mmc->capacity_user;
537 break;
538 case 1:
539 case 2:
540 mmc->capacity = mmc->capacity_boot;
541 break;
542 case 3:
543 mmc->capacity = mmc->capacity_rpmb;
544 break;
545 case 4:
546 case 5:
547 case 6:
548 case 7:
549 mmc->capacity = mmc->capacity_gp[part_num - 4];
550 break;
551 default:
552 return -1;
553 }
554
555 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
556
557 return 0;
558}
559
d2356284
SW
560int mmc_select_hwpart(int dev_num, int hwpart)
561{
562 struct mmc *mmc = find_mmc_device(dev_num);
563 int ret;
564
565 if (!mmc)
d4622df3 566 return -ENODEV;
d2356284
SW
567
568 if (mmc->part_num == hwpart)
569 return 0;
570
571 if (mmc->part_config == MMCPART_NOAVAILABLE) {
572 printf("Card doesn't support part_switch\n");
d4622df3 573 return -EMEDIUMTYPE;
d2356284
SW
574 }
575
576 ret = mmc_switch_part(dev_num, hwpart);
577 if (ret)
d4622df3 578 return ret;
d2356284
SW
579
580 mmc->part_num = hwpart;
581
582 return 0;
583}
584
585
bc897b1d
LW
586int mmc_switch_part(int dev_num, unsigned int part_num)
587{
588 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 589 int ret;
bc897b1d
LW
590
591 if (!mmc)
592 return -1;
593
f866a46d
SW
594 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
595 (mmc->part_config & ~PART_ACCESS_MASK)
596 | (part_num & PART_ACCESS_MASK));
f866a46d 597
6dc93e70
PB
598 /*
599 * Set the capacity if the switch succeeded or was intended
600 * to return to representing the raw device.
601 */
602 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
603 ret = mmc_set_capacity(mmc, part_num);
604
605 return ret;
bc897b1d
LW
606}
607
ac9da0e0
DSC
608int mmc_hwpart_config(struct mmc *mmc,
609 const struct mmc_hwpart_conf *conf,
610 enum mmc_hwpart_conf_mode mode)
611{
612 u8 part_attrs = 0;
613 u32 enh_size_mult;
614 u32 enh_start_addr;
615 u32 gp_size_mult[4];
616 u32 max_enh_size_mult;
617 u32 tot_enh_size_mult = 0;
618 int i, pidx, err;
619 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
620
621 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
622 return -EINVAL;
623
624 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
625 printf("eMMC >= 4.4 required for enhanced user data area\n");
626 return -EMEDIUMTYPE;
627 }
628
629 if (!(mmc->part_support & PART_SUPPORT)) {
630 printf("Card does not support partitioning\n");
631 return -EMEDIUMTYPE;
632 }
633
634 if (!mmc->hc_wp_grp_size) {
635 printf("Card does not define HC WP group size\n");
636 return -EMEDIUMTYPE;
637 }
638
639 /* check partition alignment and total enhanced size */
640 if (conf->user.enh_size) {
641 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
642 conf->user.enh_start % mmc->hc_wp_grp_size) {
643 printf("User data enhanced area not HC WP group "
644 "size aligned\n");
645 return -EINVAL;
646 }
647 part_attrs |= EXT_CSD_ENH_USR;
648 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
649 if (mmc->high_capacity) {
650 enh_start_addr = conf->user.enh_start;
651 } else {
652 enh_start_addr = (conf->user.enh_start << 9);
653 }
654 } else {
655 enh_size_mult = 0;
656 enh_start_addr = 0;
657 }
658 tot_enh_size_mult += enh_size_mult;
659
660 for (pidx = 0; pidx < 4; pidx++) {
661 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
662 printf("GP%i partition not HC WP group size "
663 "aligned\n", pidx+1);
664 return -EINVAL;
665 }
666 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
667 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
668 part_attrs |= EXT_CSD_ENH_GP(pidx);
669 tot_enh_size_mult += gp_size_mult[pidx];
670 }
671 }
672
673 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
674 printf("Card does not support enhanced attribute\n");
675 return -EMEDIUMTYPE;
676 }
677
678 err = mmc_send_ext_csd(mmc, ext_csd);
679 if (err)
680 return err;
681
682 max_enh_size_mult =
683 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
684 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
685 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
686 if (tot_enh_size_mult > max_enh_size_mult) {
687 printf("Total enhanced size exceeds maximum (%u > %u)\n",
688 tot_enh_size_mult, max_enh_size_mult);
689 return -EMEDIUMTYPE;
690 }
691
692 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
693 EXT_CSD_PARTITION_SETTING_COMPLETED) {
694 printf("Card already partitioned\n");
695 return -EPERM;
696 }
697
698 if (mode == MMC_HWPART_CONF_CHECK)
699 return 0;
700
701 /* Partitioning requires high-capacity size definitions */
702 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
703 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
704 EXT_CSD_ERASE_GROUP_DEF, 1);
705
706 if (err)
707 return err;
708
709 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
710
711 /* update erase group size to be high-capacity */
712 mmc->erase_grp_size =
713 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
714
715 }
716
717 /* all OK, write the configuration */
718 for (i = 0; i < 4; i++) {
719 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
720 EXT_CSD_ENH_START_ADDR+i,
721 (enh_start_addr >> (i*8)) & 0xFF);
722 if (err)
723 return err;
724 }
725 for (i = 0; i < 3; i++) {
726 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
727 EXT_CSD_ENH_SIZE_MULT+i,
728 (enh_size_mult >> (i*8)) & 0xFF);
729 if (err)
730 return err;
731 }
732 for (pidx = 0; pidx < 4; pidx++) {
733 for (i = 0; i < 3; i++) {
734 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
735 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
736 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
737 if (err)
738 return err;
739 }
740 }
741 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
742 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
743 if (err)
744 return err;
745
746 if (mode == MMC_HWPART_CONF_SET)
747 return 0;
748
749 /* Setting PART_SETTING_COMPLETED confirms the partition
750 * configuration but it only becomes effective after power
751 * cycle, so we do not adjust the partition related settings
752 * in the mmc struct. */
753
754 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
755 EXT_CSD_PARTITION_SETTING,
756 EXT_CSD_PARTITION_SETTING_COMPLETED);
757 if (err)
758 return err;
759
760 return 0;
761}
762
48972d90
TR
763int mmc_getcd(struct mmc *mmc)
764{
765 int cd;
766
767 cd = board_mmc_getcd(mmc);
768
d4e1da4e 769 if (cd < 0) {
93bfd616
PA
770 if (mmc->cfg->ops->getcd)
771 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK
772 else
773 cd = 1;
774 }
48972d90
TR
775
776 return cd;
777}
778
fdbb873e 779static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF
780{
781 struct mmc_cmd cmd;
782 struct mmc_data data;
783
784 /* Switch the frequency */
785 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
786 cmd.resp_type = MMC_RSP_R1;
787 cmd.cmdarg = (mode << 31) | 0xffffff;
788 cmd.cmdarg &= ~(0xf << (group * 4));
789 cmd.cmdarg |= value << (group * 4);
272cc70b
AF
790
791 data.dest = (char *)resp;
792 data.blocksize = 64;
793 data.blocks = 1;
794 data.flags = MMC_DATA_READ;
795
796 return mmc_send_cmd(mmc, &cmd, &data);
797}
798
799
fdbb873e 800static int sd_change_freq(struct mmc *mmc)
272cc70b
AF
801{
802 int err;
803 struct mmc_cmd cmd;
f781dd38
A
804 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
805 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF
806 struct mmc_data data;
807 int timeout;
808
809 mmc->card_caps = 0;
810
d52ebf10
TC
811 if (mmc_host_is_spi(mmc))
812 return 0;
813
272cc70b
AF
814 /* Read the SCR to find out if this card supports higher speeds */
815 cmd.cmdidx = MMC_CMD_APP_CMD;
816 cmd.resp_type = MMC_RSP_R1;
817 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
818
819 err = mmc_send_cmd(mmc, &cmd, NULL);
820
821 if (err)
822 return err;
823
824 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
825 cmd.resp_type = MMC_RSP_R1;
826 cmd.cmdarg = 0;
272cc70b
AF
827
828 timeout = 3;
829
830retry_scr:
f781dd38 831 data.dest = (char *)scr;
272cc70b
AF
832 data.blocksize = 8;
833 data.blocks = 1;
834 data.flags = MMC_DATA_READ;
835
836 err = mmc_send_cmd(mmc, &cmd, &data);
837
838 if (err) {
839 if (timeout--)
840 goto retry_scr;
841
842 return err;
843 }
844
4e3d89ba
YK
845 mmc->scr[0] = __be32_to_cpu(scr[0]);
846 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF
847
848 switch ((mmc->scr[0] >> 24) & 0xf) {
849 case 0:
850 mmc->version = SD_VERSION_1_0;
851 break;
852 case 1:
853 mmc->version = SD_VERSION_1_10;
854 break;
855 case 2:
856 mmc->version = SD_VERSION_2;
1741c64d
JC
857 if ((mmc->scr[0] >> 15) & 0x1)
858 mmc->version = SD_VERSION_3;
272cc70b
AF
859 break;
860 default:
861 mmc->version = SD_VERSION_1_0;
862 break;
863 }
864
b44c7083
AS
865 if (mmc->scr[0] & SD_DATA_4BIT)
866 mmc->card_caps |= MMC_MODE_4BIT;
867
272cc70b
AF
868 /* Version 1.0 doesn't support switching */
869 if (mmc->version == SD_VERSION_1_0)
870 return 0;
871
872 timeout = 4;
873 while (timeout--) {
874 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 875 (u8 *)switch_status);
272cc70b
AF
876
877 if (err)
878 return err;
879
880 /* The high-speed function is busy. Try again */
4e3d89ba 881 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF
882 break;
883 }
884
272cc70b 885 /* If high-speed isn't supported, we return */
4e3d89ba 886 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF
887 return 0;
888
2c3fbf4c
ML
889 /*
890 * If the host doesn't support SD_HIGHSPEED, do not switch card to
891 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
892 * This can avoid furthur problem when the card runs in different
893 * mode between the host.
894 */
93bfd616
PA
895 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
896 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML
897 return 0;
898
f781dd38 899 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF
900
901 if (err)
902 return err;
903
4e3d89ba 904 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF
905 mmc->card_caps |= MMC_MODE_HS;
906
907 return 0;
908}
909
910/* frequency bases */
911/* divided by 10 to be nice to platforms without floating point */
5f837c2c 912static const int fbase[] = {
272cc70b
AF
913 10000,
914 100000,
915 1000000,
916 10000000,
917};
918
919/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
920 * to platforms without floating point.
921 */
5f837c2c 922static const int multipliers[] = {
272cc70b
AF
923 0, /* reserved */
924 10,
925 12,
926 13,
927 15,
928 20,
929 25,
930 30,
931 35,
932 40,
933 45,
934 50,
935 55,
936 60,
937 70,
938 80,
939};
940
fdbb873e 941static void mmc_set_ios(struct mmc *mmc)
272cc70b 942{
93bfd616
PA
943 if (mmc->cfg->ops->set_ios)
944 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF
945}
946
947void mmc_set_clock(struct mmc *mmc, uint clock)
948{
93bfd616
PA
949 if (clock > mmc->cfg->f_max)
950 clock = mmc->cfg->f_max;
272cc70b 951
93bfd616
PA
952 if (clock < mmc->cfg->f_min)
953 clock = mmc->cfg->f_min;
272cc70b
AF
954
955 mmc->clock = clock;
956
957 mmc_set_ios(mmc);
958}
959
fdbb873e 960static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF
961{
962 mmc->bus_width = width;
963
964 mmc_set_ios(mmc);
965}
966
fdbb873e 967static int mmc_startup(struct mmc *mmc)
272cc70b 968{
f866a46d 969 int err, i;
272cc70b 970 uint mult, freq;
639b7827 971 u64 cmult, csize, capacity;
272cc70b 972 struct mmc_cmd cmd;
8bfa195e
SG
973 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
974 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 975 int timeout = 1000;
0c453bb7 976 bool has_parts = false;
8a0cf490 977 bool part_completed;
272cc70b 978
d52ebf10
TC
979#ifdef CONFIG_MMC_SPI_CRC_ON
980 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
981 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
982 cmd.resp_type = MMC_RSP_R1;
983 cmd.cmdarg = 1;
d52ebf10
TC
984 err = mmc_send_cmd(mmc, &cmd, NULL);
985
986 if (err)
987 return err;
988 }
989#endif
990
272cc70b 991 /* Put the Card in Identify Mode */
d52ebf10
TC
992 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
993 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF
994 cmd.resp_type = MMC_RSP_R2;
995 cmd.cmdarg = 0;
272cc70b
AF
996
997 err = mmc_send_cmd(mmc, &cmd, NULL);
998
999 if (err)
1000 return err;
1001
1002 memcpy(mmc->cid, cmd.response, 16);
1003
1004 /*
1005 * For MMC cards, set the Relative Address.
1006 * For SD cards, get the Relatvie Address.
1007 * This also puts the cards into Standby State
1008 */
d52ebf10
TC
1009 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1010 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1011 cmd.cmdarg = mmc->rca << 16;
1012 cmd.resp_type = MMC_RSP_R6;
272cc70b 1013
d52ebf10 1014 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1015
d52ebf10
TC
1016 if (err)
1017 return err;
272cc70b 1018
d52ebf10
TC
1019 if (IS_SD(mmc))
1020 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1021 }
272cc70b
AF
1022
1023 /* Get the Card-Specific Data */
1024 cmd.cmdidx = MMC_CMD_SEND_CSD;
1025 cmd.resp_type = MMC_RSP_R2;
1026 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
1027
1028 err = mmc_send_cmd(mmc, &cmd, NULL);
1029
5d4fc8d9
RR
1030 /* Waiting for the ready status */
1031 mmc_send_status(mmc, timeout);
1032
272cc70b
AF
1033 if (err)
1034 return err;
1035
998be3dd
RV
1036 mmc->csd[0] = cmd.response[0];
1037 mmc->csd[1] = cmd.response[1];
1038 mmc->csd[2] = cmd.response[2];
1039 mmc->csd[3] = cmd.response[3];
272cc70b
AF
1040
1041 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1042 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF
1043
1044 switch (version) {
1045 case 0:
1046 mmc->version = MMC_VERSION_1_2;
1047 break;
1048 case 1:
1049 mmc->version = MMC_VERSION_1_4;
1050 break;
1051 case 2:
1052 mmc->version = MMC_VERSION_2_2;
1053 break;
1054 case 3:
1055 mmc->version = MMC_VERSION_3;
1056 break;
1057 case 4:
1058 mmc->version = MMC_VERSION_4;
1059 break;
1060 default:
1061 mmc->version = MMC_VERSION_1_2;
1062 break;
1063 }
1064 }
1065
1066 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV
1067 freq = fbase[(cmd.response[0] & 0x7)];
1068 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF
1069
1070 mmc->tran_speed = freq * mult;
1071
ab71188c 1072 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1073 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF
1074
1075 if (IS_SD(mmc))
1076 mmc->write_bl_len = mmc->read_bl_len;
1077 else
998be3dd 1078 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF
1079
1080 if (mmc->high_capacity) {
1081 csize = (mmc->csd[1] & 0x3f) << 16
1082 | (mmc->csd[2] & 0xffff0000) >> 16;
1083 cmult = 8;
1084 } else {
1085 csize = (mmc->csd[1] & 0x3ff) << 2
1086 | (mmc->csd[2] & 0xc0000000) >> 30;
1087 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1088 }
1089
f866a46d
SW
1090 mmc->capacity_user = (csize + 1) << (cmult + 2);
1091 mmc->capacity_user *= mmc->read_bl_len;
1092 mmc->capacity_boot = 0;
1093 mmc->capacity_rpmb = 0;
1094 for (i = 0; i < 4; i++)
1095 mmc->capacity_gp[i] = 0;
272cc70b 1096
8bfa195e
SG
1097 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1098 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1099
8bfa195e
SG
1100 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1101 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1102
ab71188c
MN
1103 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1104 cmd.cmdidx = MMC_CMD_SET_DSR;
1105 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1106 cmd.resp_type = MMC_RSP_NONE;
1107 if (mmc_send_cmd(mmc, &cmd, NULL))
1108 printf("MMC: SET_DSR failed\n");
1109 }
1110
272cc70b 1111 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC
1112 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1113 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1114 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1115 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1116 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1117
d52ebf10
TC
1118 if (err)
1119 return err;
1120 }
272cc70b 1121
e6f99a56
LW
1122 /*
1123 * For SD, its erase group is always one sector
1124 */
1125 mmc->erase_grp_size = 1;
bc897b1d 1126 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG
1127 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1128 /* check ext_csd version and capacity */
1129 err = mmc_send_ext_csd(mmc, ext_csd);
9cf199eb
DSC
1130 if (err)
1131 return err;
1132 if (ext_csd[EXT_CSD_REV] >= 2) {
639b7827
YS
1133 /*
1134 * According to the JEDEC Standard, the value of
1135 * ext_csd's capacity is valid if the value is more
1136 * than 2GB
1137 */
0560db18
LW
1138 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1139 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1140 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1141 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 1142 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 1143 if ((capacity >> 20) > 2 * 1024)
f866a46d 1144 mmc->capacity_user = capacity;
d23e2c09 1145 }
bc897b1d 1146
64f4a619
JC
1147 switch (ext_csd[EXT_CSD_REV]) {
1148 case 1:
1149 mmc->version = MMC_VERSION_4_1;
1150 break;
1151 case 2:
1152 mmc->version = MMC_VERSION_4_2;
1153 break;
1154 case 3:
1155 mmc->version = MMC_VERSION_4_3;
1156 break;
1157 case 5:
1158 mmc->version = MMC_VERSION_4_41;
1159 break;
1160 case 6:
1161 mmc->version = MMC_VERSION_4_5;
1162 break;
edab723b
MN
1163 case 7:
1164 mmc->version = MMC_VERSION_5_0;
1165 break;
64f4a619
JC
1166 }
1167
8a0cf490
DSC
1168 /* The partition data may be non-zero but it is only
1169 * effective if PARTITION_SETTING_COMPLETED is set in
1170 * EXT_CSD, so ignore any data if this bit is not set,
1171 * except for enabling the high-capacity group size
1172 * definition (see below). */
1173 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1174 EXT_CSD_PARTITION_SETTING_COMPLETED);
1175
0c453bb7
DSC
1176 /* store the partition info of emmc */
1177 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1178 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1179 ext_csd[EXT_CSD_BOOT_MULT])
1180 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
8a0cf490
DSC
1181 if (part_completed &&
1182 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
0c453bb7
DSC
1183 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1184
1185 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1186
1187 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1188
1189 for (i = 0; i < 4; i++) {
1190 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
8a0cf490 1191 uint mult = (ext_csd[idx + 2] << 16) +
0c453bb7 1192 (ext_csd[idx + 1] << 8) + ext_csd[idx];
8a0cf490
DSC
1193 if (mult)
1194 has_parts = true;
1195 if (!part_completed)
1196 continue;
1197 mmc->capacity_gp[i] = mult;
0c453bb7
DSC
1198 mmc->capacity_gp[i] *=
1199 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1200 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
f8e89d67 1201 mmc->capacity_gp[i] <<= 19;
0c453bb7
DSC
1202 }
1203
8a0cf490
DSC
1204 if (part_completed) {
1205 mmc->enh_user_size =
1206 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1207 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1208 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1209 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1210 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1211 mmc->enh_user_size <<= 19;
1212 mmc->enh_user_start =
1213 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1214 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1215 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1216 ext_csd[EXT_CSD_ENH_START_ADDR];
1217 if (mmc->high_capacity)
1218 mmc->enh_user_start <<= 9;
1219 }
a7f852b6 1220
e6f99a56 1221 /*
1937e5aa
OM
1222 * Host needs to enable ERASE_GRP_DEF bit if device is
1223 * partitioned. This bit will be lost every time after a reset
1224 * or power off. This will affect erase size.
e6f99a56 1225 */
8a0cf490 1226 if (part_completed)
0c453bb7 1227 has_parts = true;
1937e5aa 1228 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC
1229 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1230 has_parts = true;
1231 if (has_parts) {
1937e5aa
OM
1232 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1233 EXT_CSD_ERASE_GROUP_DEF, 1);
1234
1235 if (err)
1236 return err;
021a8055
HP
1237 else
1238 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
037dc0ab 1239 }
1937e5aa 1240
037dc0ab 1241 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1937e5aa 1242 /* Read out group size from ext_csd */
0560db18 1243 mmc->erase_grp_size =
a4ff9f83 1244 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
d7b29129
MN
1245 /*
1246 * if high capacity and partition setting completed
1247 * SEC_COUNT is valid even if it is smaller than 2 GiB
1248 * JEDEC Standard JESD84-B45, 6.2.4
1249 */
8a0cf490 1250 if (mmc->high_capacity && part_completed) {
d7b29129
MN
1251 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1252 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1253 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1254 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1255 capacity *= MMC_MAX_BLOCK_LEN;
1256 mmc->capacity_user = capacity;
1257 }
8bfa195e 1258 } else {
1937e5aa 1259 /* Calculate the group size from the csd value. */
e6f99a56
LW
1260 int erase_gsz, erase_gmul;
1261 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1262 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1263 mmc->erase_grp_size = (erase_gsz + 1)
1264 * (erase_gmul + 1);
1265 }
037dc0ab
DSC
1266
1267 mmc->hc_wp_grp_size = 1024
1268 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1269 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
d23e2c09
SG
1270 }
1271
f866a46d
SW
1272 err = mmc_set_capacity(mmc, mmc->part_num);
1273 if (err)
1274 return err;
1275
272cc70b
AF
1276 if (IS_SD(mmc))
1277 err = sd_change_freq(mmc);
1278 else
1279 err = mmc_change_freq(mmc);
1280
1281 if (err)
1282 return err;
1283
1284 /* Restrict card's capabilities by what the host can do */
93bfd616 1285 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF
1286
1287 if (IS_SD(mmc)) {
1288 if (mmc->card_caps & MMC_MODE_4BIT) {
1289 cmd.cmdidx = MMC_CMD_APP_CMD;
1290 cmd.resp_type = MMC_RSP_R1;
1291 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
1292
1293 err = mmc_send_cmd(mmc, &cmd, NULL);
1294 if (err)
1295 return err;
1296
1297 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1298 cmd.resp_type = MMC_RSP_R1;
1299 cmd.cmdarg = 2;
272cc70b
AF
1300 err = mmc_send_cmd(mmc, &cmd, NULL);
1301 if (err)
1302 return err;
1303
1304 mmc_set_bus_width(mmc, 4);
1305 }
1306
1307 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1308 mmc->tran_speed = 50000000;
272cc70b 1309 else
ad5fd922 1310 mmc->tran_speed = 25000000;
272cc70b 1311 } else {
7798f6db
AF
1312 int idx;
1313
1314 /* An array of possible bus widths in order of preference */
1315 static unsigned ext_csd_bits[] = {
d22e3d46
JC
1316 EXT_CSD_DDR_BUS_WIDTH_8,
1317 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF
1318 EXT_CSD_BUS_WIDTH_8,
1319 EXT_CSD_BUS_WIDTH_4,
1320 EXT_CSD_BUS_WIDTH_1,
1321 };
1322
1323 /* An array to map CSD bus widths to host cap bits */
1324 static unsigned ext_to_hostcaps[] = {
786e8f81
AG
1325 [EXT_CSD_DDR_BUS_WIDTH_4] =
1326 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1327 [EXT_CSD_DDR_BUS_WIDTH_8] =
1328 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF
1329 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1330 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1331 };
1332
1333 /* An array to map chosen bus width to an integer */
1334 static unsigned widths[] = {
d22e3d46 1335 8, 4, 8, 4, 1,
7798f6db
AF
1336 };
1337
1338 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1339 unsigned int extw = ext_csd_bits[idx];
786e8f81 1340 unsigned int caps = ext_to_hostcaps[extw];
7798f6db
AF
1341
1342 /*
786e8f81
AG
1343 * Check to make sure the card and controller support
1344 * these capabilities
7798f6db 1345 */
786e8f81 1346 if ((mmc->card_caps & caps) != caps)
7798f6db
AF
1347 continue;
1348
272cc70b 1349 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1350 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF
1351
1352 if (err)
4137894e 1353 continue;
272cc70b 1354
786e8f81 1355 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1356 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW
1357
1358 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG
1359
1360 if (err)
1361 continue;
1362
786a27b7 1363 /* Only compare read only fields */
786e8f81
AG
1364 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1365 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1366 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1367 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1368 ext_csd[EXT_CSD_REV]
1369 == test_csd[EXT_CSD_REV] &&
1370 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1371 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1372 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1373 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1374 break;
786e8f81
AG
1375 else
1376 err = SWITCH_ERR;
272cc70b
AF
1377 }
1378
786e8f81
AG
1379 if (err)
1380 return err;
1381
272cc70b
AF
1382 if (mmc->card_caps & MMC_MODE_HS) {
1383 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1384 mmc->tran_speed = 52000000;
272cc70b 1385 else
ad5fd922
JC
1386 mmc->tran_speed = 26000000;
1387 }
272cc70b
AF
1388 }
1389
ad5fd922
JC
1390 mmc_set_clock(mmc, mmc->tran_speed);
1391
5af8f45c
AG
1392 /* Fix the block length for DDR mode */
1393 if (mmc->ddr_mode) {
1394 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1395 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1396 }
1397
272cc70b
AF
1398 /* fill in device description */
1399 mmc->block_dev.lun = 0;
1400 mmc->block_dev.type = 0;
1401 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1402 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1403 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1404#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH
1405 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1406 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1407 (mmc->cid[3] >> 16) & 0xffff);
1408 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1409 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1410 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1411 (mmc->cid[2] >> 24) & 0xff);
1412 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1413 (mmc->cid[2] >> 16) & 0xf);
56196826
PB
1414#else
1415 mmc->block_dev.vendor[0] = 0;
1416 mmc->block_dev.product[0] = 0;
1417 mmc->block_dev.revision[0] = 0;
1418#endif
122efd43 1419#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1420 init_part(&mmc->block_dev);
122efd43 1421#endif
272cc70b
AF
1422
1423 return 0;
1424}
1425
fdbb873e 1426static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF
1427{
1428 struct mmc_cmd cmd;
1429 int err;
1430
1431 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1432 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1433 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1434 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF
1435
1436 err = mmc_send_cmd(mmc, &cmd, NULL);
1437
1438 if (err)
1439 return err;
1440
998be3dd 1441 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF
1442 return UNUSABLE_ERR;
1443 else
1444 mmc->version = SD_VERSION_2;
1445
1446 return 0;
1447}
1448
93bfd616
PA
1449/* not used any more */
1450int __deprecated mmc_register(struct mmc *mmc)
1451{
1452#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1453 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1454#endif
1455 return -1;
1456}
1457
1458struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1459{
93bfd616
PA
1460 struct mmc *mmc;
1461
1462 /* quick validation */
1463 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1464 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1465 return NULL;
1466
1467 mmc = calloc(1, sizeof(*mmc));
1468 if (mmc == NULL)
1469 return NULL;
1470
1471 mmc->cfg = cfg;
1472 mmc->priv = priv;
1473
1474 /* the following chunk was mmc_register() */
1475
ab71188c
MN
1476 /* Setup dsr related values */
1477 mmc->dsr_imp = 0;
1478 mmc->dsr = 0xffffffff;
272cc70b
AF
1479 /* Setup the universal parts of the block interface just once */
1480 mmc->block_dev.if_type = IF_TYPE_MMC;
1481 mmc->block_dev.dev = cur_dev_num++;
1482 mmc->block_dev.removable = 1;
1483 mmc->block_dev.block_read = mmc_bread;
1484 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1485 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1486
93bfd616
PA
1487 /* setup initial part type */
1488 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1489
93bfd616 1490 INIT_LIST_HEAD(&mmc->link);
272cc70b 1491
93bfd616
PA
1492 list_add_tail(&mmc->link, &mmc_devices);
1493
1494 return mmc;
1495}
1496
1497void mmc_destroy(struct mmc *mmc)
1498{
1499 /* only freeing memory for now */
1500 free(mmc);
272cc70b
AF
1501}
1502
df3fc526 1503#ifdef CONFIG_PARTITIONS
272cc70b
AF
1504block_dev_desc_t *mmc_get_dev(int dev)
1505{
1506 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1507 if (!mmc || mmc_init(mmc))
40242bc3 1508 return NULL;
272cc70b 1509
40242bc3 1510 return &mmc->block_dev;
272cc70b 1511}
df3fc526 1512#endif
272cc70b 1513
95de9ab2
PK
1514/* board-specific MMC power initializations. */
1515__weak void board_mmc_power_init(void)
1516{
1517}
1518
e9550449 1519int mmc_start_init(struct mmc *mmc)
272cc70b 1520{
afd5932b 1521 int err;
272cc70b 1522
ab769f22 1523 /* we pretend there's no card when init is NULL */
93bfd616 1524 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1525 mmc->has_init = 0;
56196826 1526#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1527 printf("MMC: no card present\n");
56196826 1528#endif
48972d90
TR
1529 return NO_CARD_ERR;
1530 }
1531
bc897b1d
LW
1532 if (mmc->has_init)
1533 return 0;
1534
95de9ab2
PK
1535 board_mmc_power_init();
1536
ab769f22 1537 /* made sure it's not NULL earlier */
93bfd616 1538 err = mmc->cfg->ops->init(mmc);
272cc70b
AF
1539
1540 if (err)
1541 return err;
1542
786e8f81 1543 mmc->ddr_mode = 0;
b86b85e2
IY
1544 mmc_set_bus_width(mmc, 1);
1545 mmc_set_clock(mmc, 1);
1546
272cc70b
AF
1547 /* Reset the Card */
1548 err = mmc_go_idle(mmc);
1549
1550 if (err)
1551 return err;
1552
bc897b1d
LW
1553 /* The internal partition reset to user partition(0) at every CMD0*/
1554 mmc->part_num = 0;
1555
272cc70b 1556 /* Test for SD version 2 */
afd5932b 1557 err = mmc_send_if_cond(mmc);
272cc70b 1558
272cc70b
AF
1559 /* Now try to get the SD card's operating condition */
1560 err = sd_send_op_cond(mmc);
1561
1562 /* If the command timed out, we check for an MMC card */
1563 if (err == TIMEOUT) {
1564 err = mmc_send_op_cond(mmc);
1565
e9550449 1566 if (err && err != IN_PROGRESS) {
56196826 1567#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1568 printf("Card did not respond to voltage select!\n");
56196826 1569#endif
272cc70b
AF
1570 return UNUSABLE_ERR;
1571 }
1572 }
1573
e9550449
CLC
1574 if (err == IN_PROGRESS)
1575 mmc->init_in_progress = 1;
1576
1577 return err;
1578}
1579
1580static int mmc_complete_init(struct mmc *mmc)
1581{
1582 int err = 0;
1583
1584 if (mmc->op_cond_pending)
1585 err = mmc_complete_op_cond(mmc);
1586
1587 if (!err)
1588 err = mmc_startup(mmc);
bc897b1d
LW
1589 if (err)
1590 mmc->has_init = 0;
1591 else
1592 mmc->has_init = 1;
e9550449
CLC
1593 mmc->init_in_progress = 0;
1594 return err;
1595}
1596
1597int mmc_init(struct mmc *mmc)
1598{
1599 int err = IN_PROGRESS;
d803fea5 1600 unsigned start;
e9550449
CLC
1601
1602 if (mmc->has_init)
1603 return 0;
d803fea5
MZ
1604
1605 start = get_timer(0);
1606
e9550449
CLC
1607 if (!mmc->init_in_progress)
1608 err = mmc_start_init(mmc);
1609
1610 if (!err || err == IN_PROGRESS)
1611 err = mmc_complete_init(mmc);
1612 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1613 return err;
272cc70b
AF
1614}
1615
ab71188c
MN
1616int mmc_set_dsr(struct mmc *mmc, u16 val)
1617{
1618 mmc->dsr = val;
1619 return 0;
1620}
1621
cee9ab7c
JH
1622/* CPU-specific MMC initializations */
1623__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF
1624{
1625 return -1;
1626}
1627
cee9ab7c
JH
1628/* board-specific MMC initializations. */
1629__weak int board_mmc_init(bd_t *bis)
1630{
1631 return -1;
1632}
272cc70b 1633
56196826
PB
1634#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1635
272cc70b
AF
1636void print_mmc_devices(char separator)
1637{
1638 struct mmc *m;
1639 struct list_head *entry;
1640
1641 list_for_each(entry, &mmc_devices) {
1642 m = list_entry(entry, struct mmc, link);
1643
93bfd616 1644 printf("%s: %d", m->cfg->name, m->block_dev.dev);
272cc70b 1645
e75eaf10
LP
1646 if (entry->next != &mmc_devices) {
1647 printf("%c", separator);
1648 if (separator != '\n')
1649 puts (" ");
1650 }
272cc70b
AF
1651 }
1652
1653 printf("\n");
1654}
1655
56196826
PB
1656#else
1657void print_mmc_devices(char separator) { }
1658#endif
1659
ea6ebe21
LW
1660int get_mmc_num(void)
1661{
1662 return cur_dev_num;
1663}
1664
e9550449
CLC
1665void mmc_set_preinit(struct mmc *mmc, int preinit)
1666{
1667 mmc->preinit = preinit;
1668}
1669
1670static void do_preinit(void)
1671{
1672 struct mmc *m;
1673 struct list_head *entry;
1674
1675 list_for_each(entry, &mmc_devices) {
1676 m = list_entry(entry, struct mmc, link);
1677
1678 if (m->preinit)
1679 mmc_start_init(m);
1680 }
1681}
1682
1683
272cc70b
AF
1684int mmc_initialize(bd_t *bis)
1685{
1686 INIT_LIST_HEAD (&mmc_devices);
1687 cur_dev_num = 0;
1688
1689 if (board_mmc_init(bis) < 0)
1690 cpu_mmc_init(bis);
1691
bb0dc108 1692#ifndef CONFIG_SPL_BUILD
272cc70b 1693 print_mmc_devices(',');
bb0dc108 1694#endif
272cc70b 1695
e9550449 1696 do_preinit();
272cc70b
AF
1697 return 0;
1698}
3690d6d6
A
1699
1700#ifdef CONFIG_SUPPORT_EMMC_BOOT
1701/*
1702 * This function changes the size of boot partition and the size of rpmb
1703 * partition present on EMMC devices.
1704 *
1705 * Input Parameters:
1706 * struct *mmc: pointer for the mmc device strcuture
1707 * bootsize: size of boot partition
1708 * rpmbsize: size of rpmb partition
1709 *
1710 * Returns 0 on success.
1711 */
1712
1713int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1714 unsigned long rpmbsize)
1715{
1716 int err;
1717 struct mmc_cmd cmd;
1718
1719 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1720 cmd.cmdidx = MMC_CMD_RES_MAN;
1721 cmd.resp_type = MMC_RSP_R1b;
1722 cmd.cmdarg = MMC_CMD62_ARG1;
1723
1724 err = mmc_send_cmd(mmc, &cmd, NULL);
1725 if (err) {
1726 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1727 return err;
1728 }
1729
1730 /* Boot partition changing mode */
1731 cmd.cmdidx = MMC_CMD_RES_MAN;
1732 cmd.resp_type = MMC_RSP_R1b;
1733 cmd.cmdarg = MMC_CMD62_ARG2;
1734
1735 err = mmc_send_cmd(mmc, &cmd, NULL);
1736 if (err) {
1737 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1738 return err;
1739 }
1740 /* boot partition size is multiple of 128KB */
1741 bootsize = (bootsize * 1024) / 128;
1742
1743 /* Arg: boot partition size */
1744 cmd.cmdidx = MMC_CMD_RES_MAN;
1745 cmd.resp_type = MMC_RSP_R1b;
1746 cmd.cmdarg = bootsize;
1747
1748 err = mmc_send_cmd(mmc, &cmd, NULL);
1749 if (err) {
1750 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1751 return err;
1752 }
1753 /* RPMB partition size is multiple of 128KB */
1754 rpmbsize = (rpmbsize * 1024) / 128;
1755 /* Arg: RPMB partition size */
1756 cmd.cmdidx = MMC_CMD_RES_MAN;
1757 cmd.resp_type = MMC_RSP_R1b;
1758 cmd.cmdarg = rpmbsize;
1759
1760 err = mmc_send_cmd(mmc, &cmd, NULL);
1761 if (err) {
1762 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1763 return err;
1764 }
1765 return 0;
1766}
1767
5a99b9de
TR
1768/*
1769 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1770 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1771 * and BOOT_MODE.
1772 *
1773 * Returns 0 on success.
1774 */
1775int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1776{
1777 int err;
1778
1779 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1780 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1781 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1782 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1783
1784 if (err)
1785 return err;
1786 return 0;
1787}
1788
792970b0
TR
1789/*
1790 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1791 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1792 * PARTITION_ACCESS.
1793 *
1794 * Returns 0 on success.
1795 */
1796int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1797{
1798 int err;
1799
1800 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1801 EXT_CSD_BOOT_ACK(ack) |
1802 EXT_CSD_BOOT_PART_NUM(part_num) |
1803 EXT_CSD_PARTITION_ACCESS(access));
1804
1805 if (err)
1806 return err;
1807 return 0;
1808}
33ace362
TR
1809
1810/*
1811 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1812 * for enable. Note that this is a write-once field for non-zero values.
1813 *
1814 * Returns 0 on success.
1815 */
1816int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1817{
1818 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1819 enable);
1820}
3690d6d6 1821#endif