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mmc: add bkops-enable command
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
2051aefe 18#include <power/regulator.h>
272cc70b 19#include <malloc.h>
cf92e05c 20#include <memalign.h>
272cc70b 21#include <linux/list.h>
9b1f942c 22#include <div64.h>
da61fa5f 23#include "mmc_private.h"
272cc70b 24
3697e599
PF		 25static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31};
32
8ca51e51 33#ifndef CONFIG_DM_MMC_OPS
750121c3 34__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 35{
36 return -1;
37}
38
39int mmc_getwp(struct mmc *mmc)
40{
41 int wp;
42
43 wp = board_mmc_getwp(mmc);
44
d4e1da4e 45 if (wp < 0) {
93bfd616
PA		 46 if (mmc->cfg->ops->getwp)
47 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 48 else
49 wp = 0;
50 }
d23d8d7e
NK		 51
52 return wp;
53}
54
cee9ab7c
JH		 55__weak int board_mmc_getcd(struct mmc *mmc)
56{
11fdade2
SB		 57 return -1;
58}
8ca51e51 59#endif
11fdade2 60
c0c76eba
SG		 61#ifdef CONFIG_MMC_TRACE
62void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 63{
c0c76eba
SG		 64 printf("CMD_SEND:%d\n", cmd->cmdidx);
65 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
66}
8635ff9e 67
c0c76eba
SG		 68void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
69{
5db2fe3a
RR		 70 int i;
71 u8 *ptr;
72
7863ce58
BM		 73 if (ret) {
74 printf("\t\tRET\t\t\t %d\n", ret);
75 } else {
76 switch (cmd->resp_type) {
77 case MMC_RSP_NONE:
78 printf("\t\tMMC_RSP_NONE\n");
79 break;
80 case MMC_RSP_R1:
81 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
82 cmd->response[0]);
83 break;
84 case MMC_RSP_R1b:
85 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
86 cmd->response[0]);
87 break;
88 case MMC_RSP_R2:
89 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
90 cmd->response[0]);
91 printf("\t\t \t\t 0x%08X \n",
92 cmd->response[1]);
93 printf("\t\t \t\t 0x%08X \n",
94 cmd->response[2]);
95 printf("\t\t \t\t 0x%08X \n",
96 cmd->response[3]);
5db2fe3a 97 printf("\n");
7863ce58
BM		 98 printf("\t\t\t\t\tDUMPING DATA\n");
99 for (i = 0; i < 4; i++) {
100 int j;
101 printf("\t\t\t\t\t%03d - ", i*4);
102 ptr = (u8 *)&cmd->response[i];
103 ptr += 3;
104 for (j = 0; j < 4; j++)
105 printf("%02X ", *ptr--);
106 printf("\n");
107 }
108 break;
109 case MMC_RSP_R3:
110 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
111 cmd->response[0]);
112 break;
113 default:
114 printf("\t\tERROR MMC rsp not supported\n");
115 break;
53e8e40b 116 }
5db2fe3a 117 }
c0c76eba
SG		 118}
119
120void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
121{
122 int status;
123
124 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
125 printf("CURR STATE:%d\n", status);
126}
5db2fe3a 127#endif
c0c76eba 128
8ca51e51 129#ifndef CONFIG_DM_MMC_OPS
c0c76eba
SG		 130int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
131{
132 int ret;
133
134 mmmc_trace_before_send(mmc, cmd);
135 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
136 mmmc_trace_after_send(mmc, cmd, ret);
137
8635ff9e 138 return ret;
272cc70b 139}
8ca51e51 140#endif
272cc70b 141
da61fa5f 142int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 143{
144 struct mmc_cmd cmd;
d617c426 145 int err, retries = 5;
5d4fc8d9
RR		 146
147 cmd.cmdidx = MMC_CMD_SEND_STATUS;
148 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 149 if (!mmc_host_is_spi(mmc))
150 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 151
1677eef4 152 while (1) {
5d4fc8d9 153 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 154 if (!err) {
155 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
156 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
157 MMC_STATE_PRG)
158 break;
159 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 160#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 161 printf("Status Error: 0x%08X\n",
162 cmd.response[0]);
56196826 163#endif
915ffa52 164 return -ECOMM;
d617c426
JK		 165 }
166 } else if (--retries < 0)
5d4fc8d9 167 return err;
5d4fc8d9 168
1677eef4
AG		 169 if (timeout-- <= 0)
170 break;
5d4fc8d9 171
1677eef4
AG		 172 udelay(1000);
173 }
5d4fc8d9 174
c0c76eba 175 mmc_trace_state(mmc, &cmd);
5b0c942f 176 if (timeout <= 0) {
56196826 177#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 178 printf("Timeout waiting card ready\n");
56196826 179#endif
915ffa52 180 return -ETIMEDOUT;
5d4fc8d9
RR		 181 }
182
183 return 0;
184}
185
da61fa5f 186int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 187{
188 struct mmc_cmd cmd;
189
786e8f81 190 if (mmc->ddr_mode)
d22e3d46
JC		 191 return 0;
192
272cc70b
AF		 193 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
194 cmd.resp_type = MMC_RSP_R1;
195 cmd.cmdarg = len;
272cc70b
AF		 196
197 return mmc_send_cmd(mmc, &cmd, NULL);
198}
199
ff8fef56 200static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 201 lbaint_t blkcnt)
272cc70b
AF		 202{
203 struct mmc_cmd cmd;
204 struct mmc_data data;
205
4a1a06bc
AS		 206 if (blkcnt > 1)
207 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
208 else
209 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 210
211 if (mmc->high_capacity)
4a1a06bc 212 cmd.cmdarg = start;
272cc70b 213 else
4a1a06bc 214 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 215
216 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 217
218 data.dest = dst;
4a1a06bc 219 data.blocks = blkcnt;
272cc70b
AF		 220 data.blocksize = mmc->read_bl_len;
221 data.flags = MMC_DATA_READ;
222
4a1a06bc
AS		 223 if (mmc_send_cmd(mmc, &cmd, &data))
224 return 0;
272cc70b 225
4a1a06bc
AS		 226 if (blkcnt > 1) {
227 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
228 cmd.cmdarg = 0;
229 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 230 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 231#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 232 printf("mmc fail to send stop cmd\n");
56196826 233#endif
4a1a06bc
AS		 234 return 0;
235 }
272cc70b
AF		 236 }
237
4a1a06bc 238 return blkcnt;
272cc70b
AF		 239}
240
33fb211d 241#ifdef CONFIG_BLK
7dba0b93 242ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 243#else
7dba0b93
SG		 244ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
245 void *dst)
33fb211d 246#endif
272cc70b 247{
33fb211d
SG		 248#ifdef CONFIG_BLK
249 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
250#endif
bcce53d0 251 int dev_num = block_dev->devnum;
873cc1d7 252 int err;
4a1a06bc
AS		 253 lbaint_t cur, blocks_todo = blkcnt;
254
255 if (blkcnt == 0)
256 return 0;
272cc70b 257
4a1a06bc 258 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 259 if (!mmc)
260 return 0;
261
69f45cd5 262 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
873cc1d7
SW		 263 if (err < 0)
264 return 0;
265
c40fdca6 266 if ((start + blkcnt) > block_dev->lba) {
56196826 267#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 268 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
c40fdca6 269 start + blkcnt, block_dev->lba);
56196826 270#endif
d2bf29e3
LW		 271 return 0;
272 }
272cc70b 273
11692991
SG		 274 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
275 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 276 return 0;
11692991 277 }
272cc70b 278
4a1a06bc 279 do {
93bfd616
PA		 280 cur = (blocks_todo > mmc->cfg->b_max) ?
281 mmc->cfg->b_max : blocks_todo;
11692991
SG		 282 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
283 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 284 return 0;
11692991 285 }
4a1a06bc
AS		 286 blocks_todo -= cur;
287 start += cur;
288 dst += cur * mmc->read_bl_len;
289 } while (blocks_todo > 0);
272cc70b
AF		 290
291 return blkcnt;
292}
293
fdbb873e 294static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 295{
296 struct mmc_cmd cmd;
297 int err;
298
299 udelay(1000);
300
301 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
302 cmd.cmdarg = 0;
303 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 304
305 err = mmc_send_cmd(mmc, &cmd, NULL);
306
307 if (err)
308 return err;
309
310 udelay(2000);
311
312 return 0;
313}
314
fdbb873e 315static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF		 316{
317 int timeout = 1000;
318 int err;
319 struct mmc_cmd cmd;
320
1677eef4 321 while (1) {
272cc70b
AF		 322 cmd.cmdidx = MMC_CMD_APP_CMD;
323 cmd.resp_type = MMC_RSP_R1;
324 cmd.cmdarg = 0;
272cc70b
AF		 325
326 err = mmc_send_cmd(mmc, &cmd, NULL);
327
328 if (err)
329 return err;
330
331 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
332 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 333
334 /*
335 * Most cards do not answer if some reserved bits
336 * in the ocr are set. However, Some controller
337 * can set bit 7 (reserved for low voltages), but
338 * how to manage low voltages SD card is not yet
339 * specified.
340 */
d52ebf10 341 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 342 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 343
344 if (mmc->version == SD_VERSION_2)
345 cmd.cmdarg |= OCR_HCS;
346
347 err = mmc_send_cmd(mmc, &cmd, NULL);
348
349 if (err)
350 return err;
351
1677eef4
AG		 352 if (cmd.response[0] & OCR_BUSY)
353 break;
354
355 if (timeout-- <= 0)
915ffa52 356 return -EOPNOTSUPP;
272cc70b 357
1677eef4
AG		 358 udelay(1000);
359 }
272cc70b
AF		 360
361 if (mmc->version != SD_VERSION_2)
362 mmc->version = SD_VERSION_1_0;
363
d52ebf10
TC		 364 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
365 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
366 cmd.resp_type = MMC_RSP_R3;
367 cmd.cmdarg = 0;
d52ebf10
TC		 368
369 err = mmc_send_cmd(mmc, &cmd, NULL);
370
371 if (err)
372 return err;
373 }
374
998be3dd 375 mmc->ocr = cmd.response[0];
272cc70b
AF		 376
377 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
378 mmc->rca = 0;
379
380 return 0;
381}
382
5289b535 383static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 384{
5289b535 385 struct mmc_cmd cmd;
272cc70b
AF		 386 int err;
387
5289b535
AG		 388 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
389 cmd.resp_type = MMC_RSP_R3;
390 cmd.cmdarg = 0;
5a20397b
RH		 391 if (use_arg && !mmc_host_is_spi(mmc))
392 cmd.cmdarg = OCR_HCS |
93bfd616 393 (mmc->cfg->voltages &
a626c8d4
AG		 394 (mmc->ocr & OCR_VOLTAGE_MASK)) |
395 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 396
5289b535 397 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 398 if (err)
399 return err;
5289b535 400 mmc->ocr = cmd.response[0];
e9550449
CLC		 401 return 0;
402}
403
750121c3 404static int mmc_send_op_cond(struct mmc *mmc)
e9550449 405{
e9550449
CLC		 406 int err, i;
407
272cc70b
AF		 408 /* Some cards seem to need this */
409 mmc_go_idle(mmc);
410
31cacbab 411 /* Asking to the card its capabilities */
e9550449 412 for (i = 0; i < 2; i++) {
5289b535 413 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 414 if (err)
415 return err;
cd6881b5 416
e9550449 417 /* exit if not busy (flag seems to be inverted) */
a626c8d4 418 if (mmc->ocr & OCR_BUSY)
bd47c135 419 break;
e9550449 420 }
bd47c135
AG		 421 mmc->op_cond_pending = 1;
422 return 0;
e9550449 423}
cd6881b5 424
750121c3 425static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 426{
427 struct mmc_cmd cmd;
428 int timeout = 1000;
429 uint start;
430 int err;
cd6881b5 431
e9550449 432 mmc->op_cond_pending = 0;
cc17c01f 433 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 434 /* Some cards seem to need this */
435 mmc_go_idle(mmc);
436
cc17c01f 437 start = get_timer(0);
1677eef4 438 while (1) {
cc17c01f
AG		 439 err = mmc_send_op_cond_iter(mmc, 1);
440 if (err)
441 return err;
1677eef4
AG		 442 if (mmc->ocr & OCR_BUSY)
443 break;
cc17c01f 444 if (get_timer(start) > timeout)
915ffa52 445 return -EOPNOTSUPP;
cc17c01f 446 udelay(100);
1677eef4 447 }
cc17c01f 448 }
272cc70b 449
d52ebf10
TC		 450 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
451 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
452 cmd.resp_type = MMC_RSP_R3;
453 cmd.cmdarg = 0;
d52ebf10
TC		 454
455 err = mmc_send_cmd(mmc, &cmd, NULL);
456
457 if (err)
458 return err;
a626c8d4
AG		 459
460 mmc->ocr = cmd.response[0];
d52ebf10
TC		 461 }
462
272cc70b 463 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 464
465 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 466 mmc->rca = 1;
272cc70b
AF		 467
468 return 0;
469}
470
471
fdbb873e 472static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 473{
474 struct mmc_cmd cmd;
475 struct mmc_data data;
476 int err;
477
478 /* Get the Card Status Register */
479 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
480 cmd.resp_type = MMC_RSP_R1;
481 cmd.cmdarg = 0;
272cc70b 482
cdfd1ac6 483 data.dest = (char *)ext_csd;
272cc70b 484 data.blocks = 1;
8bfa195e 485 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 486 data.flags = MMC_DATA_READ;
487
488 err = mmc_send_cmd(mmc, &cmd, &data);
489
490 return err;
491}
492
c40704f4 493int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 494{
495 struct mmc_cmd cmd;
5d4fc8d9 496 int timeout = 1000;
a9003dc6 497 int retries = 3;
5d4fc8d9 498 int ret;
272cc70b
AF		 499
500 cmd.cmdidx = MMC_CMD_SWITCH;
501 cmd.resp_type = MMC_RSP_R1b;
502 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 503 (index << 16) |
504 (value << 8);
272cc70b 505
a9003dc6
MR		 506 while (retries > 0) {
507 ret = mmc_send_cmd(mmc, &cmd, NULL);
5d4fc8d9 508
a9003dc6
MR		 509 /* Waiting for the ready status */
510 if (!ret) {
511 ret = mmc_send_status(mmc, timeout);
512 return ret;
513 }
514
515 retries--;
516 }
5d4fc8d9
RR		 517
518 return ret;
519
272cc70b
AF		 520}
521
fdbb873e 522static int mmc_change_freq(struct mmc *mmc)
272cc70b 523{
8bfa195e 524 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF		 525 char cardtype;
526 int err;
527
fc5b32fb 528 mmc->card_caps = 0;
272cc70b 529
d52ebf10
TC		 530 if (mmc_host_is_spi(mmc))
531 return 0;
532
272cc70b
AF		 533 /* Only version 4 supports high-speed */
534 if (mmc->version < MMC_VERSION_4)
535 return 0;
536
fc5b32fb
AG		 537 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
538
272cc70b
AF		 539 err = mmc_send_ext_csd(mmc, ext_csd);
540
541 if (err)
542 return err;
543
0560db18 544 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF		 545
546 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
547
548 if (err)
a5e27b41 549 return err;
272cc70b
AF		 550
551 /* Now check to see that it worked */
552 err = mmc_send_ext_csd(mmc, ext_csd);
553
554 if (err)
555 return err;
556
557 /* No high-speed support */
0560db18 558 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF		 559 return 0;
560
561 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 562 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 563 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 564 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 565 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 566 } else {
272cc70b 567 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 568 }
272cc70b
AF		 569
570 return 0;
571}
572
f866a46d
SW		 573static int mmc_set_capacity(struct mmc *mmc, int part_num)
574{
575 switch (part_num) {
576 case 0:
577 mmc->capacity = mmc->capacity_user;
578 break;
579 case 1:
580 case 2:
581 mmc->capacity = mmc->capacity_boot;
582 break;
583 case 3:
584 mmc->capacity = mmc->capacity_rpmb;
585 break;
586 case 4:
587 case 5:
588 case 6:
589 case 7:
590 mmc->capacity = mmc->capacity_gp[part_num - 4];
591 break;
592 default:
593 return -1;
594 }
595
c40fdca6 596 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 597
598 return 0;
599}
600
7dba0b93 601int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 602{
f866a46d 603 int ret;
bc897b1d 604
f866a46d
SW		 605 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
606 (mmc->part_config & ~PART_ACCESS_MASK)
607 | (part_num & PART_ACCESS_MASK));
f866a46d 608
6dc93e70
PB		 609 /*
610 * Set the capacity if the switch succeeded or was intended
611 * to return to representing the raw device.
612 */
873cc1d7 613 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 614 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 615 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 616 }
6dc93e70
PB		 617
618 return ret;
bc897b1d
LW		 619}
620
ac9da0e0
DSC		 621int mmc_hwpart_config(struct mmc *mmc,
622 const struct mmc_hwpart_conf *conf,
623 enum mmc_hwpart_conf_mode mode)
624{
625 u8 part_attrs = 0;
626 u32 enh_size_mult;
627 u32 enh_start_addr;
628 u32 gp_size_mult[4];
629 u32 max_enh_size_mult;
630 u32 tot_enh_size_mult = 0;
8dda5b0e 631 u8 wr_rel_set;
ac9da0e0
DSC		 632 int i, pidx, err;
633 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
634
635 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
636 return -EINVAL;
637
638 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
639 printf("eMMC >= 4.4 required for enhanced user data area\n");
640 return -EMEDIUMTYPE;
641 }
642
643 if (!(mmc->part_support & PART_SUPPORT)) {
644 printf("Card does not support partitioning\n");
645 return -EMEDIUMTYPE;
646 }
647
648 if (!mmc->hc_wp_grp_size) {
649 printf("Card does not define HC WP group size\n");
650 return -EMEDIUMTYPE;
651 }
652
653 /* check partition alignment and total enhanced size */
654 if (conf->user.enh_size) {
655 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
656 conf->user.enh_start % mmc->hc_wp_grp_size) {
657 printf("User data enhanced area not HC WP group "
658 "size aligned\n");
659 return -EINVAL;
660 }
661 part_attrs |= EXT_CSD_ENH_USR;
662 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
663 if (mmc->high_capacity) {
664 enh_start_addr = conf->user.enh_start;
665 } else {
666 enh_start_addr = (conf->user.enh_start << 9);
667 }
668 } else {
669 enh_size_mult = 0;
670 enh_start_addr = 0;
671 }
672 tot_enh_size_mult += enh_size_mult;
673
674 for (pidx = 0; pidx < 4; pidx++) {
675 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
676 printf("GP%i partition not HC WP group size "
677 "aligned\n", pidx+1);
678 return -EINVAL;
679 }
680 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
681 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
682 part_attrs |= EXT_CSD_ENH_GP(pidx);
683 tot_enh_size_mult += gp_size_mult[pidx];
684 }
685 }
686
687 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
688 printf("Card does not support enhanced attribute\n");
689 return -EMEDIUMTYPE;
690 }
691
692 err = mmc_send_ext_csd(mmc, ext_csd);
693 if (err)
694 return err;
695
696 max_enh_size_mult =
697 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
698 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
699 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
700 if (tot_enh_size_mult > max_enh_size_mult) {
701 printf("Total enhanced size exceeds maximum (%u > %u)\n",
702 tot_enh_size_mult, max_enh_size_mult);
703 return -EMEDIUMTYPE;
704 }
705
8dda5b0e
DSC		 706 /* The default value of EXT_CSD_WR_REL_SET is device
707 * dependent, the values can only be changed if the
708 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
709 * changed only once and before partitioning is completed. */
710 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
711 if (conf->user.wr_rel_change) {
712 if (conf->user.wr_rel_set)
713 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
714 else
715 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
716 }
717 for (pidx = 0; pidx < 4; pidx++) {
718 if (conf->gp_part[pidx].wr_rel_change) {
719 if (conf->gp_part[pidx].wr_rel_set)
720 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
721 else
722 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
723 }
724 }
725
726 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
727 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
728 puts("Card does not support host controlled partition write "
729 "reliability settings\n");
730 return -EMEDIUMTYPE;
731 }
732
ac9da0e0
DSC		 733 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
734 EXT_CSD_PARTITION_SETTING_COMPLETED) {
735 printf("Card already partitioned\n");
736 return -EPERM;
737 }
738
739 if (mode == MMC_HWPART_CONF_CHECK)
740 return 0;
741
742 /* Partitioning requires high-capacity size definitions */
743 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
744 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
745 EXT_CSD_ERASE_GROUP_DEF, 1);
746
747 if (err)
748 return err;
749
750 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
751
752 /* update erase group size to be high-capacity */
753 mmc->erase_grp_size =
754 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
755
756 }
757
758 /* all OK, write the configuration */
759 for (i = 0; i < 4; i++) {
760 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
761 EXT_CSD_ENH_START_ADDR+i,
762 (enh_start_addr >> (i*8)) & 0xFF);
763 if (err)
764 return err;
765 }
766 for (i = 0; i < 3; i++) {
767 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
768 EXT_CSD_ENH_SIZE_MULT+i,
769 (enh_size_mult >> (i*8)) & 0xFF);
770 if (err)
771 return err;
772 }
773 for (pidx = 0; pidx < 4; pidx++) {
774 for (i = 0; i < 3; i++) {
775 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
776 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
777 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
778 if (err)
779 return err;
780 }
781 }
782 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
783 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
784 if (err)
785 return err;
786
787 if (mode == MMC_HWPART_CONF_SET)
788 return 0;
789
8dda5b0e
DSC		 790 /* The WR_REL_SET is a write-once register but shall be
791 * written before setting PART_SETTING_COMPLETED. As it is
792 * write-once we can only write it when completing the
793 * partitioning. */
794 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
795 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
796 EXT_CSD_WR_REL_SET, wr_rel_set);
797 if (err)
798 return err;
799 }
800
ac9da0e0
DSC		 801 /* Setting PART_SETTING_COMPLETED confirms the partition
802 * configuration but it only becomes effective after power
803 * cycle, so we do not adjust the partition related settings
804 * in the mmc struct. */
805
806 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
807 EXT_CSD_PARTITION_SETTING,
808 EXT_CSD_PARTITION_SETTING_COMPLETED);
809 if (err)
810 return err;
811
812 return 0;
813}
814
8ca51e51 815#ifndef CONFIG_DM_MMC_OPS
48972d90
TR		 816int mmc_getcd(struct mmc *mmc)
817{
818 int cd;
819
820 cd = board_mmc_getcd(mmc);
821
d4e1da4e 822 if (cd < 0) {
93bfd616
PA		 823 if (mmc->cfg->ops->getcd)
824 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 825 else
826 cd = 1;
827 }
48972d90
TR		 828
829 return cd;
830}
8ca51e51 831#endif
48972d90 832
fdbb873e 833static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 834{
835 struct mmc_cmd cmd;
836 struct mmc_data data;
837
838 /* Switch the frequency */
839 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
840 cmd.resp_type = MMC_RSP_R1;
841 cmd.cmdarg = (mode << 31) | 0xffffff;
842 cmd.cmdarg &= ~(0xf << (group * 4));
843 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 844
845 data.dest = (char *)resp;
846 data.blocksize = 64;
847 data.blocks = 1;
848 data.flags = MMC_DATA_READ;
849
850 return mmc_send_cmd(mmc, &cmd, &data);
851}
852
853
fdbb873e 854static int sd_change_freq(struct mmc *mmc)
272cc70b
AF		 855{
856 int err;
857 struct mmc_cmd cmd;
f781dd38
A		 858 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
859 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF		 860 struct mmc_data data;
861 int timeout;
862
863 mmc->card_caps = 0;
864
d52ebf10
TC		 865 if (mmc_host_is_spi(mmc))
866 return 0;
867
272cc70b
AF		 868 /* Read the SCR to find out if this card supports higher speeds */
869 cmd.cmdidx = MMC_CMD_APP_CMD;
870 cmd.resp_type = MMC_RSP_R1;
871 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 872
873 err = mmc_send_cmd(mmc, &cmd, NULL);
874
875 if (err)
876 return err;
877
878 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
879 cmd.resp_type = MMC_RSP_R1;
880 cmd.cmdarg = 0;
272cc70b
AF		 881
882 timeout = 3;
883
884retry_scr:
f781dd38 885 data.dest = (char *)scr;
272cc70b
AF		 886 data.blocksize = 8;
887 data.blocks = 1;
888 data.flags = MMC_DATA_READ;
889
890 err = mmc_send_cmd(mmc, &cmd, &data);
891
892 if (err) {
893 if (timeout--)
894 goto retry_scr;
895
896 return err;
897 }
898
4e3d89ba
YK		 899 mmc->scr[0] = __be32_to_cpu(scr[0]);
900 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 901
902 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 903 case 0:
904 mmc->version = SD_VERSION_1_0;
905 break;
906 case 1:
907 mmc->version = SD_VERSION_1_10;
908 break;
909 case 2:
910 mmc->version = SD_VERSION_2;
911 if ((mmc->scr[0] >> 15) & 0x1)
912 mmc->version = SD_VERSION_3;
913 break;
914 default:
915 mmc->version = SD_VERSION_1_0;
916 break;
272cc70b
AF		 917 }
918
b44c7083
AS		 919 if (mmc->scr[0] & SD_DATA_4BIT)
920 mmc->card_caps |= MMC_MODE_4BIT;
921
272cc70b
AF		 922 /* Version 1.0 doesn't support switching */
923 if (mmc->version == SD_VERSION_1_0)
924 return 0;
925
926 timeout = 4;
927 while (timeout--) {
928 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 929 (u8 *)switch_status);
272cc70b
AF		 930
931 if (err)
932 return err;
933
934 /* The high-speed function is busy. Try again */
4e3d89ba 935 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 936 break;
937 }
938
272cc70b 939 /* If high-speed isn't supported, we return */
4e3d89ba 940 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF		 941 return 0;
942
2c3fbf4c
ML		 943 /*
944 * If the host doesn't support SD_HIGHSPEED, do not switch card to
945 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
946 * This can avoid furthur problem when the card runs in different
947 * mode between the host.
948 */
93bfd616
PA		 949 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
950 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML		 951 return 0;
952
f781dd38 953 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF		 954
955 if (err)
956 return err;
957
4e3d89ba 958 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF		 959 mmc->card_caps |= MMC_MODE_HS;
960
961 return 0;
962}
963
3697e599
PF		 964static int sd_read_ssr(struct mmc *mmc)
965{
966 int err, i;
967 struct mmc_cmd cmd;
968 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
969 struct mmc_data data;
970 int timeout = 3;
971 unsigned int au, eo, et, es;
972
973 cmd.cmdidx = MMC_CMD_APP_CMD;
974 cmd.resp_type = MMC_RSP_R1;
975 cmd.cmdarg = mmc->rca << 16;
976
977 err = mmc_send_cmd(mmc, &cmd, NULL);
978 if (err)
979 return err;
980
981 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
982 cmd.resp_type = MMC_RSP_R1;
983 cmd.cmdarg = 0;
984
985retry_ssr:
986 data.dest = (char *)ssr;
987 data.blocksize = 64;
988 data.blocks = 1;
989 data.flags = MMC_DATA_READ;
990
991 err = mmc_send_cmd(mmc, &cmd, &data);
992 if (err) {
993 if (timeout--)
994 goto retry_ssr;
995
996 return err;
997 }
998
999 for (i = 0; i < 16; i++)
1000 ssr[i] = be32_to_cpu(ssr[i]);
1001
1002 au = (ssr[2] >> 12) & 0xF;
1003 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1004 mmc->ssr.au = sd_au_size[au];
1005 es = (ssr[3] >> 24) & 0xFF;
1006 es |= (ssr[2] & 0xFF) << 8;
1007 et = (ssr[3] >> 18) & 0x3F;
1008 if (es && et) {
1009 eo = (ssr[3] >> 16) & 0x3;
1010 mmc->ssr.erase_timeout = (et * 1000) / es;
1011 mmc->ssr.erase_offset = eo * 1000;
1012 }
1013 } else {
1014 debug("Invalid Allocation Unit Size.\n");
1015 }
1016
1017 return 0;
1018}
1019
272cc70b
AF		 1020/* frequency bases */
1021/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1022static const int fbase[] = {
272cc70b
AF		 1023 10000,
1024 100000,
1025 1000000,
1026 10000000,
1027};
1028
1029/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1030 * to platforms without floating point.
1031 */
61fe076f 1032static const u8 multipliers[] = {
272cc70b
AF		 1033 0, /* reserved */
1034 10,
1035 12,
1036 13,
1037 15,
1038 20,
1039 25,
1040 30,
1041 35,
1042 40,
1043 45,
1044 50,
1045 55,
1046 60,
1047 70,
1048 80,
1049};
1050
8ca51e51 1051#ifndef CONFIG_DM_MMC_OPS
fdbb873e 1052static void mmc_set_ios(struct mmc *mmc)
272cc70b 1053{
93bfd616
PA		 1054 if (mmc->cfg->ops->set_ios)
1055 mmc->cfg->ops->set_ios(mmc);
272cc70b 1056}
8ca51e51 1057#endif
272cc70b
AF		 1058
1059void mmc_set_clock(struct mmc *mmc, uint clock)
1060{
93bfd616
PA		 1061 if (clock > mmc->cfg->f_max)
1062 clock = mmc->cfg->f_max;
272cc70b 1063
93bfd616
PA		 1064 if (clock < mmc->cfg->f_min)
1065 clock = mmc->cfg->f_min;
272cc70b
AF		 1066
1067 mmc->clock = clock;
1068
1069 mmc_set_ios(mmc);
1070}
1071
fdbb873e 1072static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1073{
1074 mmc->bus_width = width;
1075
1076 mmc_set_ios(mmc);
1077}
1078
fdbb873e 1079static int mmc_startup(struct mmc *mmc)
272cc70b 1080{
f866a46d 1081 int err, i;
272cc70b 1082 uint mult, freq;
639b7827 1083 u64 cmult, csize, capacity;
272cc70b 1084 struct mmc_cmd cmd;
8bfa195e
SG		 1085 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1086 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 1087 int timeout = 1000;
0c453bb7 1088 bool has_parts = false;
8a0cf490 1089 bool part_completed;
c40fdca6 1090 struct blk_desc *bdesc;
272cc70b 1091
d52ebf10
TC		 1092#ifdef CONFIG_MMC_SPI_CRC_ON
1093 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1094 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1095 cmd.resp_type = MMC_RSP_R1;
1096 cmd.cmdarg = 1;
d52ebf10
TC		 1097 err = mmc_send_cmd(mmc, &cmd, NULL);
1098
1099 if (err)
1100 return err;
1101 }
1102#endif
1103
272cc70b 1104 /* Put the Card in Identify Mode */
d52ebf10
TC		 1105 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1106 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1107 cmd.resp_type = MMC_RSP_R2;
1108 cmd.cmdarg = 0;
272cc70b
AF		 1109
1110 err = mmc_send_cmd(mmc, &cmd, NULL);
1111
1112 if (err)
1113 return err;
1114
1115 memcpy(mmc->cid, cmd.response, 16);
1116
1117 /*
1118 * For MMC cards, set the Relative Address.
1119 * For SD cards, get the Relatvie Address.
1120 * This also puts the cards into Standby State
1121 */
d52ebf10
TC		 1122 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1123 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1124 cmd.cmdarg = mmc->rca << 16;
1125 cmd.resp_type = MMC_RSP_R6;
272cc70b 1126
d52ebf10 1127 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1128
d52ebf10
TC		 1129 if (err)
1130 return err;
272cc70b 1131
d52ebf10
TC		 1132 if (IS_SD(mmc))
1133 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1134 }
272cc70b
AF		 1135
1136 /* Get the Card-Specific Data */
1137 cmd.cmdidx = MMC_CMD_SEND_CSD;
1138 cmd.resp_type = MMC_RSP_R2;
1139 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1140
1141 err = mmc_send_cmd(mmc, &cmd, NULL);
1142
5d4fc8d9
RR		 1143 /* Waiting for the ready status */
1144 mmc_send_status(mmc, timeout);
1145
272cc70b
AF		 1146 if (err)
1147 return err;
1148
998be3dd
RV		 1149 mmc->csd[0] = cmd.response[0];
1150 mmc->csd[1] = cmd.response[1];
1151 mmc->csd[2] = cmd.response[2];
1152 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1153
1154 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1155 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1156
1157 switch (version) {
53e8e40b
BM		 1158 case 0:
1159 mmc->version = MMC_VERSION_1_2;
1160 break;
1161 case 1:
1162 mmc->version = MMC_VERSION_1_4;
1163 break;
1164 case 2:
1165 mmc->version = MMC_VERSION_2_2;
1166 break;
1167 case 3:
1168 mmc->version = MMC_VERSION_3;
1169 break;
1170 case 4:
1171 mmc->version = MMC_VERSION_4;
1172 break;
1173 default:
1174 mmc->version = MMC_VERSION_1_2;
1175 break;
272cc70b
AF		 1176 }
1177 }
1178
1179 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1180 freq = fbase[(cmd.response[0] & 0x7)];
1181 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF		 1182
1183 mmc->tran_speed = freq * mult;
1184
ab71188c 1185 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1186 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 1187
1188 if (IS_SD(mmc))
1189 mmc->write_bl_len = mmc->read_bl_len;
1190 else
998be3dd 1191 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 1192
1193 if (mmc->high_capacity) {
1194 csize = (mmc->csd[1] & 0x3f) << 16
1195 | (mmc->csd[2] & 0xffff0000) >> 16;
1196 cmult = 8;
1197 } else {
1198 csize = (mmc->csd[1] & 0x3ff) << 2
1199 | (mmc->csd[2] & 0xc0000000) >> 30;
1200 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1201 }
1202
f866a46d
SW		 1203 mmc->capacity_user = (csize + 1) << (cmult + 2);
1204 mmc->capacity_user *= mmc->read_bl_len;
1205 mmc->capacity_boot = 0;
1206 mmc->capacity_rpmb = 0;
1207 for (i = 0; i < 4; i++)
1208 mmc->capacity_gp[i] = 0;
272cc70b 1209
8bfa195e
SG		 1210 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1211 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1212
8bfa195e
SG		 1213 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1214 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1215
ab71188c
MN		 1216 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1217 cmd.cmdidx = MMC_CMD_SET_DSR;
1218 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1219 cmd.resp_type = MMC_RSP_NONE;
1220 if (mmc_send_cmd(mmc, &cmd, NULL))
1221 printf("MMC: SET_DSR failed\n");
1222 }
1223
272cc70b 1224 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 1225 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1226 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1227 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1228 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1229 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1230
d52ebf10
TC		 1231 if (err)
1232 return err;
1233 }
272cc70b 1234
e6f99a56
LW		 1235 /*
1236 * For SD, its erase group is always one sector
1237 */
1238 mmc->erase_grp_size = 1;
bc897b1d 1239 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG		 1240 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1241 /* check ext_csd version and capacity */
1242 err = mmc_send_ext_csd(mmc, ext_csd);
9cf199eb
DSC		 1243 if (err)
1244 return err;
1245 if (ext_csd[EXT_CSD_REV] >= 2) {
639b7827
YS		 1246 /*
1247 * According to the JEDEC Standard, the value of
1248 * ext_csd's capacity is valid if the value is more
1249 * than 2GB
1250 */
0560db18
LW		 1251 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1252 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1253 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1254 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 1255 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 1256 if ((capacity >> 20) > 2 * 1024)
f866a46d 1257 mmc->capacity_user = capacity;
d23e2c09 1258 }
bc897b1d 1259
64f4a619
JC		 1260 switch (ext_csd[EXT_CSD_REV]) {
1261 case 1:
1262 mmc->version = MMC_VERSION_4_1;
1263 break;
1264 case 2:
1265 mmc->version = MMC_VERSION_4_2;
1266 break;
1267 case 3:
1268 mmc->version = MMC_VERSION_4_3;
1269 break;
1270 case 5:
1271 mmc->version = MMC_VERSION_4_41;
1272 break;
1273 case 6:
1274 mmc->version = MMC_VERSION_4_5;
1275 break;
edab723b
MN		 1276 case 7:
1277 mmc->version = MMC_VERSION_5_0;
1278 break;
1a3619cf
SW		 1279 case 8:
1280 mmc->version = MMC_VERSION_5_1;
1281 break;
64f4a619
JC		 1282 }
1283
8a0cf490
DSC		 1284 /* The partition data may be non-zero but it is only
1285 * effective if PARTITION_SETTING_COMPLETED is set in
1286 * EXT_CSD, so ignore any data if this bit is not set,
1287 * except for enabling the high-capacity group size
1288 * definition (see below). */
1289 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1290 EXT_CSD_PARTITION_SETTING_COMPLETED);
1291
0c453bb7
DSC		 1292 /* store the partition info of emmc */
1293 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1294 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1295 ext_csd[EXT_CSD_BOOT_MULT])
1296 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
8a0cf490
DSC		 1297 if (part_completed &&
1298 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
0c453bb7
DSC		 1299 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1300
1301 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1302
1303 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1304
1305 for (i = 0; i < 4; i++) {
1306 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
8a0cf490 1307 uint mult = (ext_csd[idx + 2] << 16) +
0c453bb7 1308 (ext_csd[idx + 1] << 8) + ext_csd[idx];
8a0cf490
DSC		 1309 if (mult)
1310 has_parts = true;
1311 if (!part_completed)
1312 continue;
1313 mmc->capacity_gp[i] = mult;
0c453bb7
DSC		 1314 mmc->capacity_gp[i] *=
1315 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1316 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
f8e89d67 1317 mmc->capacity_gp[i] <<= 19;
0c453bb7
DSC		 1318 }
1319
8a0cf490
DSC		 1320 if (part_completed) {
1321 mmc->enh_user_size =
1322 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1323 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1324 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1325 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1326 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1327 mmc->enh_user_size <<= 19;
1328 mmc->enh_user_start =
1329 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1330 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1331 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1332 ext_csd[EXT_CSD_ENH_START_ADDR];
1333 if (mmc->high_capacity)
1334 mmc->enh_user_start <<= 9;
1335 }
a7f852b6 1336
e6f99a56 1337 /*
1937e5aa
OM		 1338 * Host needs to enable ERASE_GRP_DEF bit if device is
1339 * partitioned. This bit will be lost every time after a reset
1340 * or power off. This will affect erase size.
e6f99a56 1341 */
8a0cf490 1342 if (part_completed)
0c453bb7 1343 has_parts = true;
1937e5aa 1344 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC		 1345 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1346 has_parts = true;
1347 if (has_parts) {
1937e5aa
OM		 1348 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1349 EXT_CSD_ERASE_GROUP_DEF, 1);
1350
1351 if (err)
1352 return err;
021a8055
HP		 1353 else
1354 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
037dc0ab 1355 }
1937e5aa 1356
037dc0ab 1357 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1937e5aa 1358 /* Read out group size from ext_csd */
0560db18 1359 mmc->erase_grp_size =
a4ff9f83 1360 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
d7b29129
MN		 1361 /*
1362 * if high capacity and partition setting completed
1363 * SEC_COUNT is valid even if it is smaller than 2 GiB
1364 * JEDEC Standard JESD84-B45, 6.2.4
1365 */
8a0cf490 1366 if (mmc->high_capacity && part_completed) {
d7b29129
MN		 1367 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1368 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1369 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1370 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1371 capacity *= MMC_MAX_BLOCK_LEN;
1372 mmc->capacity_user = capacity;
1373 }
8bfa195e 1374 } else {
1937e5aa 1375 /* Calculate the group size from the csd value. */
e6f99a56
LW		 1376 int erase_gsz, erase_gmul;
1377 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1378 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1379 mmc->erase_grp_size = (erase_gsz + 1)
1380 * (erase_gmul + 1);
1381 }
037dc0ab
DSC		 1382
1383 mmc->hc_wp_grp_size = 1024
1384 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1385 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
9e41a00b
DSC		 1386
1387 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
d23e2c09
SG		 1388 }
1389
c40fdca6 1390 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 1391 if (err)
1392 return err;
1393
272cc70b
AF		 1394 if (IS_SD(mmc))
1395 err = sd_change_freq(mmc);
1396 else
1397 err = mmc_change_freq(mmc);
1398
1399 if (err)
1400 return err;
1401
1402 /* Restrict card's capabilities by what the host can do */
93bfd616 1403 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF		 1404
1405 if (IS_SD(mmc)) {
1406 if (mmc->card_caps & MMC_MODE_4BIT) {
1407 cmd.cmdidx = MMC_CMD_APP_CMD;
1408 cmd.resp_type = MMC_RSP_R1;
1409 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1410
1411 err = mmc_send_cmd(mmc, &cmd, NULL);
1412 if (err)
1413 return err;
1414
1415 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1416 cmd.resp_type = MMC_RSP_R1;
1417 cmd.cmdarg = 2;
272cc70b
AF		 1418 err = mmc_send_cmd(mmc, &cmd, NULL);
1419 if (err)
1420 return err;
1421
1422 mmc_set_bus_width(mmc, 4);
1423 }
1424
3697e599
PF		 1425 err = sd_read_ssr(mmc);
1426 if (err)
1427 return err;
1428
272cc70b 1429 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1430 mmc->tran_speed = 50000000;
272cc70b 1431 else
ad5fd922 1432 mmc->tran_speed = 25000000;
fc5b32fb
AG		 1433 } else if (mmc->version >= MMC_VERSION_4) {
1434 /* Only version 4 of MMC supports wider bus widths */
7798f6db
AF		 1435 int idx;
1436
1437 /* An array of possible bus widths in order of preference */
1438 static unsigned ext_csd_bits[] = {
d22e3d46
JC		 1439 EXT_CSD_DDR_BUS_WIDTH_8,
1440 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF		 1441 EXT_CSD_BUS_WIDTH_8,
1442 EXT_CSD_BUS_WIDTH_4,
1443 EXT_CSD_BUS_WIDTH_1,
1444 };
1445
1446 /* An array to map CSD bus widths to host cap bits */
1447 static unsigned ext_to_hostcaps[] = {
786e8f81
AG		 1448 [EXT_CSD_DDR_BUS_WIDTH_4] =
1449 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1450 [EXT_CSD_DDR_BUS_WIDTH_8] =
1451 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF		 1452 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1453 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1454 };
1455
1456 /* An array to map chosen bus width to an integer */
1457 static unsigned widths[] = {
d22e3d46 1458 8, 4, 8, 4, 1,
7798f6db
AF		 1459 };
1460
1461 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1462 unsigned int extw = ext_csd_bits[idx];
786e8f81 1463 unsigned int caps = ext_to_hostcaps[extw];
7798f6db 1464
bf477073
AG		 1465 /*
1466 * If the bus width is still not changed,
1467 * don't try to set the default again.
1468 * Otherwise, recover from switch attempts
1469 * by switching to 1-bit bus width.
1470 */
1471 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1472 mmc->bus_width == 1) {
1473 err = 0;
1474 break;
1475 }
1476
7798f6db 1477 /*
786e8f81
AG		 1478 * Check to make sure the card and controller support
1479 * these capabilities
7798f6db 1480 */
786e8f81 1481 if ((mmc->card_caps & caps) != caps)
7798f6db
AF		 1482 continue;
1483
272cc70b 1484 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1485 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF		 1486
1487 if (err)
4137894e 1488 continue;
272cc70b 1489
786e8f81 1490 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1491 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW		 1492
1493 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG		 1494
1495 if (err)
1496 continue;
1497
786a27b7 1498 /* Only compare read only fields */
786e8f81
AG		 1499 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1500 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1501 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1502 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1503 ext_csd[EXT_CSD_REV]
1504 == test_csd[EXT_CSD_REV] &&
1505 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1506 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1507 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1508 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1509 break;
786e8f81 1510 else
915ffa52 1511 err = -EBADMSG;
272cc70b
AF		 1512 }
1513
786e8f81
AG		 1514 if (err)
1515 return err;
1516
272cc70b
AF		 1517 if (mmc->card_caps & MMC_MODE_HS) {
1518 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1519 mmc->tran_speed = 52000000;
272cc70b 1520 else
ad5fd922
JC		 1521 mmc->tran_speed = 26000000;
1522 }
272cc70b
AF		 1523 }
1524
ad5fd922
JC		 1525 mmc_set_clock(mmc, mmc->tran_speed);
1526
5af8f45c
AG		 1527 /* Fix the block length for DDR mode */
1528 if (mmc->ddr_mode) {
1529 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1530 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1531 }
1532
272cc70b 1533 /* fill in device description */
c40fdca6
SG		 1534 bdesc = mmc_get_blk_desc(mmc);
1535 bdesc->lun = 0;
1536 bdesc->hwpart = 0;
1537 bdesc->type = 0;
1538 bdesc->blksz = mmc->read_bl_len;
1539 bdesc->log2blksz = LOG2(bdesc->blksz);
1540 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 1541#if !defined(CONFIG_SPL_BUILD) || \
1542 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1543 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 1544 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 1545 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1546 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 1547 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 1548 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1549 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1550 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 1551 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 1552 (mmc->cid[2] >> 16) & 0xf);
56196826 1553#else
c40fdca6
SG		 1554 bdesc->vendor[0] = 0;
1555 bdesc->product[0] = 0;
1556 bdesc->revision[0] = 0;
56196826 1557#endif
122efd43 1558#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
c40fdca6 1559 part_init(bdesc);
122efd43 1560#endif
272cc70b
AF		 1561
1562 return 0;
1563}
1564
fdbb873e 1565static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 1566{
1567 struct mmc_cmd cmd;
1568 int err;
1569
1570 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1571 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1572 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1573 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 1574
1575 err = mmc_send_cmd(mmc, &cmd, NULL);
1576
1577 if (err)
1578 return err;
1579
998be3dd 1580 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 1581 return -EOPNOTSUPP;
272cc70b
AF		 1582 else
1583 mmc->version = SD_VERSION_2;
1584
1585 return 0;
1586}
1587
95de9ab2
PK		 1588/* board-specific MMC power initializations. */
1589__weak void board_mmc_power_init(void)
1590{
1591}
1592
2051aefe
PF		 1593static int mmc_power_init(struct mmc *mmc)
1594{
1595 board_mmc_power_init();
1596
1597#if defined(CONFIG_DM_MMC) && defined(CONFIG_DM_REGULATOR) && \
1598 !defined(CONFIG_SPL_BUILD)
1599 struct udevice *vmmc_supply;
1600 int ret;
1601
1602 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
1603 &vmmc_supply);
1604 if (ret) {
288db7c7 1605 debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe
PF		 1606 return 0;
1607 }
1608
1609 ret = regulator_set_enable(vmmc_supply, true);
1610 if (ret) {
1611 puts("Error enabling VMMC supply\n");
1612 return ret;
1613 }
1614#endif
1615 return 0;
1616}
1617
e9550449 1618int mmc_start_init(struct mmc *mmc)
272cc70b 1619{
8ca51e51 1620 bool no_card;
afd5932b 1621 int err;
272cc70b 1622
ab769f22 1623 /* we pretend there's no card when init is NULL */
8ca51e51
SG		 1624 no_card = mmc_getcd(mmc) == 0;
1625#ifndef CONFIG_DM_MMC_OPS
1626 no_card = no_card || (mmc->cfg->ops->init == NULL);
1627#endif
1628 if (no_card) {
48972d90 1629 mmc->has_init = 0;
56196826 1630#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1631 printf("MMC: no card present\n");
56196826 1632#endif
915ffa52 1633 return -ENOMEDIUM;
48972d90
TR		 1634 }
1635
bc897b1d
LW		 1636 if (mmc->has_init)
1637 return 0;
1638
5a8dbdc6
YL		 1639#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1640 mmc_adapter_card_type_ident();
1641#endif
2051aefe
PF		 1642 err = mmc_power_init(mmc);
1643 if (err)
1644 return err;
95de9ab2 1645
8ca51e51
SG		 1646#ifdef CONFIG_DM_MMC_OPS
1647 /* The device has already been probed ready for use */
1648#else
ab769f22 1649 /* made sure it's not NULL earlier */
93bfd616 1650 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 1651 if (err)
1652 return err;
8ca51e51 1653#endif
786e8f81 1654 mmc->ddr_mode = 0;
b86b85e2
IY		 1655 mmc_set_bus_width(mmc, 1);
1656 mmc_set_clock(mmc, 1);
1657
272cc70b
AF		 1658 /* Reset the Card */
1659 err = mmc_go_idle(mmc);
1660
1661 if (err)
1662 return err;
1663
bc897b1d 1664 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 1665 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 1666
272cc70b 1667 /* Test for SD version 2 */
afd5932b 1668 err = mmc_send_if_cond(mmc);
272cc70b 1669
272cc70b
AF		 1670 /* Now try to get the SD card's operating condition */
1671 err = sd_send_op_cond(mmc);
1672
1673 /* If the command timed out, we check for an MMC card */
915ffa52 1674 if (err == -ETIMEDOUT) {
272cc70b
AF		 1675 err = mmc_send_op_cond(mmc);
1676
bd47c135 1677 if (err) {
56196826 1678#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1679 printf("Card did not respond to voltage select!\n");
56196826 1680#endif
915ffa52 1681 return -EOPNOTSUPP;
272cc70b
AF		 1682 }
1683 }
1684
bd47c135 1685 if (!err)
e9550449
CLC		 1686 mmc->init_in_progress = 1;
1687
1688 return err;
1689}
1690
1691static int mmc_complete_init(struct mmc *mmc)
1692{
1693 int err = 0;
1694
bd47c135 1695 mmc->init_in_progress = 0;
e9550449
CLC		 1696 if (mmc->op_cond_pending)
1697 err = mmc_complete_op_cond(mmc);
1698
1699 if (!err)
1700 err = mmc_startup(mmc);
bc897b1d
LW		 1701 if (err)
1702 mmc->has_init = 0;
1703 else
1704 mmc->has_init = 1;
e9550449
CLC		 1705 return err;
1706}
1707
1708int mmc_init(struct mmc *mmc)
1709{
bd47c135 1710 int err = 0;
d803fea5 1711 unsigned start;
33fb211d
SG		 1712#ifdef CONFIG_DM_MMC
1713 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 1714
33fb211d
SG		 1715 upriv->mmc = mmc;
1716#endif
e9550449
CLC		 1717 if (mmc->has_init)
1718 return 0;
d803fea5
MZ		 1719
1720 start = get_timer(0);
1721
e9550449
CLC		 1722 if (!mmc->init_in_progress)
1723 err = mmc_start_init(mmc);
1724
bd47c135 1725 if (!err)
e9550449
CLC		 1726 err = mmc_complete_init(mmc);
1727 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1728 return err;
272cc70b
AF		 1729}
1730
ab71188c
MN		 1731int mmc_set_dsr(struct mmc *mmc, u16 val)
1732{
1733 mmc->dsr = val;
1734 return 0;
1735}
1736
cee9ab7c
JH		 1737/* CPU-specific MMC initializations */
1738__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 1739{
1740 return -1;
1741}
1742
cee9ab7c
JH		 1743/* board-specific MMC initializations. */
1744__weak int board_mmc_init(bd_t *bis)
1745{
1746 return -1;
1747}
272cc70b 1748
e9550449
CLC		 1749void mmc_set_preinit(struct mmc *mmc, int preinit)
1750{
1751 mmc->preinit = preinit;
1752}
1753
8e3332e2
SS		 1754#if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1755static int mmc_probe(bd_t *bis)
1756{
1757 return 0;
1758}
1759#elif defined(CONFIG_DM_MMC)
1760static int mmc_probe(bd_t *bis)
1761{
4a1db6d8 1762 int ret, i;
8e3332e2 1763 struct uclass *uc;
4a1db6d8 1764 struct udevice *dev;
8e3332e2
SS		 1765
1766 ret = uclass_get(UCLASS_MMC, &uc);
1767 if (ret)
1768 return ret;
1769
4a1db6d8
SG		 1770 /*
1771 * Try to add them in sequence order. Really with driver model we
1772 * should allow holes, but the current MMC list does not allow that.
1773 * So if we request 0, 1, 3 we will get 0, 1, 2.
1774 */
1775 for (i = 0; ; i++) {
1776 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1777 if (ret == -ENODEV)
1778 break;
1779 }
1780 uclass_foreach_dev(dev, uc) {
1781 ret = device_probe(dev);
8e3332e2 1782 if (ret)
4a1db6d8 1783 printf("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 1784 }
1785
1786 return 0;
1787}
1788#else
1789static int mmc_probe(bd_t *bis)
1790{
1791 if (board_mmc_init(bis) < 0)
1792 cpu_mmc_init(bis);
1793
1794 return 0;
1795}
1796#endif
e9550449 1797
272cc70b
AF		 1798int mmc_initialize(bd_t *bis)
1799{
1b26bab1 1800 static int initialized = 0;
8e3332e2 1801 int ret;
1b26bab1
DK		 1802 if (initialized) /* Avoid initializing mmc multiple times */
1803 return 0;
1804 initialized = 1;
1805
c40fdca6
SG		 1806#ifndef CONFIG_BLK
1807 mmc_list_init();
1808#endif
8e3332e2
SS		 1809 ret = mmc_probe(bis);
1810 if (ret)
1811 return ret;
272cc70b 1812
bb0dc108 1813#ifndef CONFIG_SPL_BUILD
272cc70b 1814 print_mmc_devices(',');
bb0dc108 1815#endif
272cc70b 1816
c40fdca6 1817 mmc_do_preinit();
272cc70b
AF		 1818 return 0;
1819}
cd3d4880
TM		 1820
1821#ifdef CONFIG_CMD_BKOPS_ENABLE
1822int mmc_set_bkops_enable(struct mmc *mmc)
1823{
1824 int err;
1825 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1826
1827 err = mmc_send_ext_csd(mmc, ext_csd);
1828 if (err) {
1829 puts("Could not get ext_csd register values\n");
1830 return err;
1831 }
1832
1833 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
1834 puts("Background operations not supported on device\n");
1835 return -EMEDIUMTYPE;
1836 }
1837
1838 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
1839 puts("Background operations already enabled\n");
1840 return 0;
1841 }
1842
1843 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
1844 if (err) {
1845 puts("Failed to enable manual background operations\n");
1846 return err;
1847 }
1848
1849 puts("Enabled manual background operations\n");
1850
1851 return 0;
1852}
1853#endif
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