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mmc: convert most of printf() to pr_err() and pr_warn()
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
2051aefe 18#include <power/regulator.h>
272cc70b 19#include <malloc.h>
cf92e05c 20#include <memalign.h>
272cc70b 21#include <linux/list.h>
9b1f942c 22#include <div64.h>
da61fa5f 23#include "mmc_private.h"
272cc70b 24
3697e599
PF		 25static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31};
32
aff5d3c8 33static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
fb7c3beb 34static int mmc_power_cycle(struct mmc *mmc);
01298da3 35static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
aff5d3c8 36
b5b838f1
MV		 37#if CONFIG_IS_ENABLED(MMC_TINY)
38static struct mmc mmc_static;
39struct mmc *find_mmc_device(int dev_num)
40{
41 return &mmc_static;
42}
43
44void mmc_do_preinit(void)
45{
46 struct mmc *m = &mmc_static;
47#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
48 mmc_set_preinit(m, 1);
49#endif
50 if (m->preinit)
51 mmc_start_init(m);
52}
53
54struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
55{
56 return &mmc->block_dev;
57}
58#endif
59
e7881d85 60#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6
JJH		 61
62static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
63{
64 return -ENOSYS;
65}
66
750121c3 67__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 68{
69 return -1;
70}
71
72int mmc_getwp(struct mmc *mmc)
73{
74 int wp;
75
76 wp = board_mmc_getwp(mmc);
77
d4e1da4e 78 if (wp < 0) {
93bfd616
PA		 79 if (mmc->cfg->ops->getwp)
80 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 81 else
82 wp = 0;
83 }
d23d8d7e
NK		 84
85 return wp;
86}
87
cee9ab7c
JH		 88__weak int board_mmc_getcd(struct mmc *mmc)
89{
11fdade2
SB		 90 return -1;
91}
8ca51e51 92#endif
11fdade2 93
c0c76eba
SG		 94#ifdef CONFIG_MMC_TRACE
95void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 96{
c0c76eba
SG		 97 printf("CMD_SEND:%d\n", cmd->cmdidx);
98 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
99}
8635ff9e 100
c0c76eba
SG		 101void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
102{
5db2fe3a
RR		 103 int i;
104 u8 *ptr;
105
7863ce58
BM		 106 if (ret) {
107 printf("\t\tRET\t\t\t %d\n", ret);
108 } else {
109 switch (cmd->resp_type) {
110 case MMC_RSP_NONE:
111 printf("\t\tMMC_RSP_NONE\n");
112 break;
113 case MMC_RSP_R1:
114 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
115 cmd->response[0]);
116 break;
117 case MMC_RSP_R1b:
118 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
119 cmd->response[0]);
120 break;
121 case MMC_RSP_R2:
122 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
123 cmd->response[0]);
124 printf("\t\t \t\t 0x%08X \n",
125 cmd->response[1]);
126 printf("\t\t \t\t 0x%08X \n",
127 cmd->response[2]);
128 printf("\t\t \t\t 0x%08X \n",
129 cmd->response[3]);
5db2fe3a 130 printf("\n");
7863ce58
BM		 131 printf("\t\t\t\t\tDUMPING DATA\n");
132 for (i = 0; i < 4; i++) {
133 int j;
134 printf("\t\t\t\t\t%03d - ", i*4);
135 ptr = (u8 *)&cmd->response[i];
136 ptr += 3;
137 for (j = 0; j < 4; j++)
138 printf("%02X ", *ptr--);
139 printf("\n");
140 }
141 break;
142 case MMC_RSP_R3:
143 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
144 cmd->response[0]);
145 break;
146 default:
147 printf("\t\tERROR MMC rsp not supported\n");
148 break;
53e8e40b 149 }
5db2fe3a 150 }
c0c76eba
SG		 151}
152
153void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
154{
155 int status;
156
157 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
158 printf("CURR STATE:%d\n", status);
159}
5db2fe3a 160#endif
c0c76eba 161
35f9e196
JJH		 162#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
163const char *mmc_mode_name(enum bus_mode mode)
164{
165 static const char *const names[] = {
166 [MMC_LEGACY] = "MMC legacy",
167 [SD_LEGACY] = "SD Legacy",
168 [MMC_HS] = "MMC High Speed (26MHz)",
169 [SD_HS] = "SD High Speed (50MHz)",
170 [UHS_SDR12] = "UHS SDR12 (25MHz)",
171 [UHS_SDR25] = "UHS SDR25 (50MHz)",
172 [UHS_SDR50] = "UHS SDR50 (100MHz)",
173 [UHS_SDR104] = "UHS SDR104 (208MHz)",
174 [UHS_DDR50] = "UHS DDR50 (50MHz)",
175 [MMC_HS_52] = "MMC High Speed (52MHz)",
176 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
177 [MMC_HS_200] = "HS200 (200MHz)",
178 };
179
180 if (mode >= MMC_MODES_END)
181 return "Unknown mode";
182 else
183 return names[mode];
184}
185#endif
186
05038576
JJH		 187static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
188{
189 static const int freqs[] = {
190 [SD_LEGACY] = 25000000,
191 [MMC_HS] = 26000000,
192 [SD_HS] = 50000000,
193 [UHS_SDR12] = 25000000,
194 [UHS_SDR25] = 50000000,
195 [UHS_SDR50] = 100000000,
196 [UHS_SDR104] = 208000000,
197 [UHS_DDR50] = 50000000,
198 [MMC_HS_52] = 52000000,
199 [MMC_DDR_52] = 52000000,
200 [MMC_HS_200] = 200000000,
201 };
202
203 if (mode == MMC_LEGACY)
204 return mmc->legacy_speed;
205 else if (mode >= MMC_MODES_END)
206 return 0;
207 else
208 return freqs[mode];
209}
210
35f9e196
JJH		 211static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
212{
213 mmc->selected_mode = mode;
05038576 214 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 215 mmc->ddr_mode = mmc_is_mode_ddr(mode);
35f9e196
JJH		 216 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
217 mmc->tran_speed / 1000000);
218 return 0;
219}
220
e7881d85 221#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 222int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
223{
224 int ret;
225
226 mmmc_trace_before_send(mmc, cmd);
227 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
228 mmmc_trace_after_send(mmc, cmd, ret);
229
8635ff9e 230 return ret;
272cc70b 231}
8ca51e51 232#endif
272cc70b 233
da61fa5f 234int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 235{
236 struct mmc_cmd cmd;
d617c426 237 int err, retries = 5;
5d4fc8d9
RR		 238
239 cmd.cmdidx = MMC_CMD_SEND_STATUS;
240 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 241 if (!mmc_host_is_spi(mmc))
242 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 243
1677eef4 244 while (1) {
5d4fc8d9 245 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 246 if (!err) {
247 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
248 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
249 MMC_STATE_PRG)
250 break;
d0c221fe
JJH		 251
252 if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 253#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420
JJH		 254 pr_err("Status Error: 0x%08X\n",
255 cmd.response[0]);
56196826 256#endif
915ffa52 257 return -ECOMM;
d617c426
JK		 258 }
259 } else if (--retries < 0)
5d4fc8d9 260 return err;
5d4fc8d9 261
1677eef4
AG		 262 if (timeout-- <= 0)
263 break;
5d4fc8d9 264
1677eef4
AG		 265 udelay(1000);
266 }
5d4fc8d9 267
c0c76eba 268 mmc_trace_state(mmc, &cmd);
5b0c942f 269 if (timeout <= 0) {
56196826 270#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 271 pr_err("Timeout waiting card ready\n");
56196826 272#endif
915ffa52 273 return -ETIMEDOUT;
5d4fc8d9
RR		 274 }
275
276 return 0;
277}
278
da61fa5f 279int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 280{
281 struct mmc_cmd cmd;
83dc4227 282 int err;
272cc70b 283
786e8f81 284 if (mmc->ddr_mode)
d22e3d46
JC		 285 return 0;
286
272cc70b
AF		 287 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
288 cmd.resp_type = MMC_RSP_R1;
289 cmd.cmdarg = len;
272cc70b 290
83dc4227
KVA		 291 err = mmc_send_cmd(mmc, &cmd, NULL);
292
293#ifdef CONFIG_MMC_QUIRKS
294 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
295 int retries = 4;
296 /*
297 * It has been seen that SET_BLOCKLEN may fail on the first
298 * attempt, let's try a few more time
299 */
300 do {
301 err = mmc_send_cmd(mmc, &cmd, NULL);
302 if (!err)
303 break;
304 } while (retries--);
305 }
306#endif
307
308 return err;
272cc70b
AF		 309}
310
9815e3ba
JJH		 311static const u8 tuning_blk_pattern_4bit[] = {
312 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
313 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
314 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
315 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
316 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
317 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
318 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
319 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
320};
321
322static const u8 tuning_blk_pattern_8bit[] = {
323 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
324 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
325 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
326 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
327 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
328 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
329 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
330 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
331 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
332 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
333 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
334 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
335 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
336 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
337 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
338 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
339};
340
341int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
342{
343 struct mmc_cmd cmd;
344 struct mmc_data data;
345 const u8 *tuning_block_pattern;
346 int size, err;
347
348 if (mmc->bus_width == 8) {
349 tuning_block_pattern = tuning_blk_pattern_8bit;
350 size = sizeof(tuning_blk_pattern_8bit);
351 } else if (mmc->bus_width == 4) {
352 tuning_block_pattern = tuning_blk_pattern_4bit;
353 size = sizeof(tuning_blk_pattern_4bit);
354 } else {
355 return -EINVAL;
356 }
357
358 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
359
360 cmd.cmdidx = opcode;
361 cmd.cmdarg = 0;
362 cmd.resp_type = MMC_RSP_R1;
363
364 data.dest = (void *)data_buf;
365 data.blocks = 1;
366 data.blocksize = size;
367 data.flags = MMC_DATA_READ;
368
369 err = mmc_send_cmd(mmc, &cmd, &data);
370 if (err)
371 return err;
372
373 if (memcmp(data_buf, tuning_block_pattern, size))
374 return -EIO;
375
376 return 0;
377}
378
ff8fef56 379static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 380 lbaint_t blkcnt)
272cc70b
AF		 381{
382 struct mmc_cmd cmd;
383 struct mmc_data data;
384
4a1a06bc
AS		 385 if (blkcnt > 1)
386 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
387 else
388 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 389
390 if (mmc->high_capacity)
4a1a06bc 391 cmd.cmdarg = start;
272cc70b 392 else
4a1a06bc 393 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 394
395 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 396
397 data.dest = dst;
4a1a06bc 398 data.blocks = blkcnt;
272cc70b
AF		 399 data.blocksize = mmc->read_bl_len;
400 data.flags = MMC_DATA_READ;
401
4a1a06bc
AS		 402 if (mmc_send_cmd(mmc, &cmd, &data))
403 return 0;
272cc70b 404
4a1a06bc
AS		 405 if (blkcnt > 1) {
406 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
407 cmd.cmdarg = 0;
408 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 409 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 410#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 411 pr_err("mmc fail to send stop cmd\n");
56196826 412#endif
4a1a06bc
AS		 413 return 0;
414 }
272cc70b
AF		 415 }
416
4a1a06bc 417 return blkcnt;
272cc70b
AF		 418}
419
c4d660d4 420#if CONFIG_IS_ENABLED(BLK)
7dba0b93 421ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 422#else
7dba0b93
SG		 423ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
424 void *dst)
33fb211d 425#endif
272cc70b 426{
c4d660d4 427#if CONFIG_IS_ENABLED(BLK)
33fb211d
SG		 428 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
429#endif
bcce53d0 430 int dev_num = block_dev->devnum;
873cc1d7 431 int err;
4a1a06bc
AS		 432 lbaint_t cur, blocks_todo = blkcnt;
433
434 if (blkcnt == 0)
435 return 0;
272cc70b 436
4a1a06bc 437 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 438 if (!mmc)
439 return 0;
440
b5b838f1
MV		 441 if (CONFIG_IS_ENABLED(MMC_TINY))
442 err = mmc_switch_part(mmc, block_dev->hwpart);
443 else
444 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
445
873cc1d7
SW		 446 if (err < 0)
447 return 0;
448
c40fdca6 449 if ((start + blkcnt) > block_dev->lba) {
56196826 450#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420
JJH		 451 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
452 start + blkcnt, block_dev->lba);
56196826 453#endif
d2bf29e3
LW		 454 return 0;
455 }
272cc70b 456
11692991
SG		 457 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
458 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 459 return 0;
11692991 460 }
272cc70b 461
4a1a06bc 462 do {
93bfd616
PA		 463 cur = (blocks_todo > mmc->cfg->b_max) ?
464 mmc->cfg->b_max : blocks_todo;
11692991
SG		 465 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
466 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 467 return 0;
11692991 468 }
4a1a06bc
AS		 469 blocks_todo -= cur;
470 start += cur;
471 dst += cur * mmc->read_bl_len;
472 } while (blocks_todo > 0);
272cc70b
AF		 473
474 return blkcnt;
475}
476
fdbb873e 477static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 478{
479 struct mmc_cmd cmd;
480 int err;
481
482 udelay(1000);
483
484 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
485 cmd.cmdarg = 0;
486 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 487
488 err = mmc_send_cmd(mmc, &cmd, NULL);
489
490 if (err)
491 return err;
492
493 udelay(2000);
494
495 return 0;
496}
497
c10b85d6
JJH		 498static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
499{
500 struct mmc_cmd cmd;
501 int err = 0;
502
503 /*
504 * Send CMD11 only if the request is to switch the card to
505 * 1.8V signalling.
506 */
507 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
508 return mmc_set_signal_voltage(mmc, signal_voltage);
509
510 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
511 cmd.cmdarg = 0;
512 cmd.resp_type = MMC_RSP_R1;
513
514 err = mmc_send_cmd(mmc, &cmd, NULL);
515 if (err)
516 return err;
517
518 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
519 return -EIO;
520
521 /*
522 * The card should drive cmd and dat[0:3] low immediately
523 * after the response of cmd11, but wait 100 us to be sure
524 */
525 err = mmc_wait_dat0(mmc, 0, 100);
526 if (err == -ENOSYS)
527 udelay(100);
528 else if (err)
529 return -ETIMEDOUT;
530
531 /*
532 * During a signal voltage level switch, the clock must be gated
533 * for 5 ms according to the SD spec
534 */
535 mmc_set_clock(mmc, mmc->clock, true);
536
537 err = mmc_set_signal_voltage(mmc, signal_voltage);
538 if (err)
539 return err;
540
541 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
542 mdelay(10);
543 mmc_set_clock(mmc, mmc->clock, false);
544
545 /*
546 * Failure to switch is indicated by the card holding
547 * dat[0:3] low. Wait for at least 1 ms according to spec
548 */
549 err = mmc_wait_dat0(mmc, 1, 1000);
550 if (err == -ENOSYS)
551 udelay(1000);
552 else if (err)
553 return -ETIMEDOUT;
554
555 return 0;
556}
557
558static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 559{
560 int timeout = 1000;
561 int err;
562 struct mmc_cmd cmd;
563
1677eef4 564 while (1) {
272cc70b
AF		 565 cmd.cmdidx = MMC_CMD_APP_CMD;
566 cmd.resp_type = MMC_RSP_R1;
567 cmd.cmdarg = 0;
272cc70b
AF		 568
569 err = mmc_send_cmd(mmc, &cmd, NULL);
570
571 if (err)
572 return err;
573
574 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
575 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 576
577 /*
578 * Most cards do not answer if some reserved bits
579 * in the ocr are set. However, Some controller
580 * can set bit 7 (reserved for low voltages), but
581 * how to manage low voltages SD card is not yet
582 * specified.
583 */
d52ebf10 584 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 585 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 586
587 if (mmc->version == SD_VERSION_2)
588 cmd.cmdarg |= OCR_HCS;
589
c10b85d6
JJH		 590 if (uhs_en)
591 cmd.cmdarg |= OCR_S18R;
592
272cc70b
AF		 593 err = mmc_send_cmd(mmc, &cmd, NULL);
594
595 if (err)
596 return err;
597
1677eef4
AG		 598 if (cmd.response[0] & OCR_BUSY)
599 break;
600
601 if (timeout-- <= 0)
915ffa52 602 return -EOPNOTSUPP;
272cc70b 603
1677eef4
AG		 604 udelay(1000);
605 }
272cc70b
AF		 606
607 if (mmc->version != SD_VERSION_2)
608 mmc->version = SD_VERSION_1_0;
609
d52ebf10
TC		 610 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
611 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
612 cmd.resp_type = MMC_RSP_R3;
613 cmd.cmdarg = 0;
d52ebf10
TC		 614
615 err = mmc_send_cmd(mmc, &cmd, NULL);
616
617 if (err)
618 return err;
619 }
620
998be3dd 621 mmc->ocr = cmd.response[0];
272cc70b 622
c10b85d6
JJH		 623 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
624 == 0x41000000) {
625 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
626 if (err)
627 return err;
628 }
629
272cc70b
AF		 630 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
631 mmc->rca = 0;
632
633 return 0;
634}
635
5289b535 636static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 637{
5289b535 638 struct mmc_cmd cmd;
272cc70b
AF		 639 int err;
640
5289b535
AG		 641 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
642 cmd.resp_type = MMC_RSP_R3;
643 cmd.cmdarg = 0;
5a20397b
RH		 644 if (use_arg && !mmc_host_is_spi(mmc))
645 cmd.cmdarg = OCR_HCS |
93bfd616 646 (mmc->cfg->voltages &
a626c8d4
AG		 647 (mmc->ocr & OCR_VOLTAGE_MASK)) |
648 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 649
5289b535 650 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 651 if (err)
652 return err;
5289b535 653 mmc->ocr = cmd.response[0];
e9550449
CLC		 654 return 0;
655}
656
750121c3 657static int mmc_send_op_cond(struct mmc *mmc)
e9550449 658{
e9550449
CLC		 659 int err, i;
660
272cc70b
AF		 661 /* Some cards seem to need this */
662 mmc_go_idle(mmc);
663
31cacbab 664 /* Asking to the card its capabilities */
e9550449 665 for (i = 0; i < 2; i++) {
5289b535 666 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 667 if (err)
668 return err;
cd6881b5 669
e9550449 670 /* exit if not busy (flag seems to be inverted) */
a626c8d4 671 if (mmc->ocr & OCR_BUSY)
bd47c135 672 break;
e9550449 673 }
bd47c135
AG		 674 mmc->op_cond_pending = 1;
675 return 0;
e9550449 676}
cd6881b5 677
750121c3 678static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 679{
680 struct mmc_cmd cmd;
681 int timeout = 1000;
682 uint start;
683 int err;
cd6881b5 684
e9550449 685 mmc->op_cond_pending = 0;
cc17c01f 686 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 687 /* Some cards seem to need this */
688 mmc_go_idle(mmc);
689
cc17c01f 690 start = get_timer(0);
1677eef4 691 while (1) {
cc17c01f
AG		 692 err = mmc_send_op_cond_iter(mmc, 1);
693 if (err)
694 return err;
1677eef4
AG		 695 if (mmc->ocr & OCR_BUSY)
696 break;
cc17c01f 697 if (get_timer(start) > timeout)
915ffa52 698 return -EOPNOTSUPP;
cc17c01f 699 udelay(100);
1677eef4 700 }
cc17c01f 701 }
272cc70b 702
d52ebf10
TC		 703 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
704 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
705 cmd.resp_type = MMC_RSP_R3;
706 cmd.cmdarg = 0;
d52ebf10
TC		 707
708 err = mmc_send_cmd(mmc, &cmd, NULL);
709
710 if (err)
711 return err;
a626c8d4
AG		 712
713 mmc->ocr = cmd.response[0];
d52ebf10
TC		 714 }
715
272cc70b 716 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 717
718 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 719 mmc->rca = 1;
272cc70b
AF		 720
721 return 0;
722}
723
724
fdbb873e 725static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 726{
727 struct mmc_cmd cmd;
728 struct mmc_data data;
729 int err;
730
731 /* Get the Card Status Register */
732 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
733 cmd.resp_type = MMC_RSP_R1;
734 cmd.cmdarg = 0;
272cc70b 735
cdfd1ac6 736 data.dest = (char *)ext_csd;
272cc70b 737 data.blocks = 1;
8bfa195e 738 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 739 data.flags = MMC_DATA_READ;
740
741 err = mmc_send_cmd(mmc, &cmd, &data);
742
743 return err;
744}
745
c40704f4 746int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 747{
748 struct mmc_cmd cmd;
5d4fc8d9 749 int timeout = 1000;
a9003dc6 750 int retries = 3;
5d4fc8d9 751 int ret;
272cc70b
AF		 752
753 cmd.cmdidx = MMC_CMD_SWITCH;
754 cmd.resp_type = MMC_RSP_R1b;
755 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 756 (index << 16) |
757 (value << 8);
272cc70b 758
a9003dc6
MR		 759 while (retries > 0) {
760 ret = mmc_send_cmd(mmc, &cmd, NULL);
5d4fc8d9 761
a9003dc6
MR		 762 /* Waiting for the ready status */
763 if (!ret) {
764 ret = mmc_send_status(mmc, timeout);
765 return ret;
766 }
767
768 retries--;
769 }
5d4fc8d9
RR		 770
771 return ret;
772
272cc70b
AF		 773}
774
3862b854 775static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
272cc70b 776{
272cc70b 777 int err;
3862b854
JJH		 778 int speed_bits;
779
780 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
781
782 switch (mode) {
783 case MMC_HS:
784 case MMC_HS_52:
785 case MMC_DDR_52:
786 speed_bits = EXT_CSD_TIMING_HS;
634d4849
KVA		 787 break;
788 case MMC_HS_200:
789 speed_bits = EXT_CSD_TIMING_HS200;
790 break;
3862b854
JJH		 791 case MMC_LEGACY:
792 speed_bits = EXT_CSD_TIMING_LEGACY;
793 break;
794 default:
795 return -EINVAL;
796 }
797 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
798 speed_bits);
799 if (err)
800 return err;
801
802 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
803 /* Now check to see that it worked */
804 err = mmc_send_ext_csd(mmc, test_csd);
805 if (err)
806 return err;
807
808 /* No high-speed support */
809 if (!test_csd[EXT_CSD_HS_TIMING])
810 return -ENOTSUPP;
811 }
812
813 return 0;
814}
815
816static int mmc_get_capabilities(struct mmc *mmc)
817{
818 u8 *ext_csd = mmc->ext_csd;
819 char cardtype;
272cc70b 820
00e446fa 821 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 822
d52ebf10
TC		 823 if (mmc_host_is_spi(mmc))
824 return 0;
825
272cc70b
AF		 826 /* Only version 4 supports high-speed */
827 if (mmc->version < MMC_VERSION_4)
828 return 0;
829
3862b854 830 if (!ext_csd) {
d8e3d420 831 pr_err("No ext_csd found!\n"); /* this should enver happen */
3862b854
JJH		 832 return -ENOTSUPP;
833 }
272cc70b 834
3862b854 835 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 836
634d4849 837 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
bc1e3272 838 mmc->cardtype = cardtype;
272cc70b 839
634d4849
KVA		 840 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
841 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
842 mmc->card_caps |= MMC_MODE_HS200;
843 }
d22e3d46 844 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 845 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 846 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 847 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 848 }
3862b854
JJH		 849 if (cardtype & EXT_CSD_CARD_TYPE_26)
850 mmc->card_caps |= MMC_MODE_HS;
272cc70b
AF		 851
852 return 0;
853}
854
f866a46d
SW		 855static int mmc_set_capacity(struct mmc *mmc, int part_num)
856{
857 switch (part_num) {
858 case 0:
859 mmc->capacity = mmc->capacity_user;
860 break;
861 case 1:
862 case 2:
863 mmc->capacity = mmc->capacity_boot;
864 break;
865 case 3:
866 mmc->capacity = mmc->capacity_rpmb;
867 break;
868 case 4:
869 case 5:
870 case 6:
871 case 7:
872 mmc->capacity = mmc->capacity_gp[part_num - 4];
873 break;
874 default:
875 return -1;
876 }
877
c40fdca6 878 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 879
880 return 0;
881}
882
01298da3
JJH		 883static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
884{
885 int forbidden = 0;
886 bool change = false;
887
888 if (part_num & PART_ACCESS_MASK)
889 forbidden = MMC_CAP(MMC_HS_200);
890
891 if (MMC_CAP(mmc->selected_mode) & forbidden) {
892 debug("selected mode (%s) is forbidden for part %d\n",
893 mmc_mode_name(mmc->selected_mode), part_num);
894 change = true;
895 } else if (mmc->selected_mode != mmc->best_mode) {
896 debug("selected mode is not optimal\n");
897 change = true;
898 }
899
900 if (change)
901 return mmc_select_mode_and_width(mmc,
902 mmc->card_caps & ~forbidden);
903
904 return 0;
905}
906
7dba0b93 907int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 908{
f866a46d 909 int ret;
bc897b1d 910
01298da3
JJH		 911 ret = mmc_boot_part_access_chk(mmc, part_num);
912 if (ret)
913 return ret;
914
f866a46d
SW		 915 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
916 (mmc->part_config & ~PART_ACCESS_MASK)
917 | (part_num & PART_ACCESS_MASK));
f866a46d 918
6dc93e70
PB		 919 /*
920 * Set the capacity if the switch succeeded or was intended
921 * to return to representing the raw device.
922 */
873cc1d7 923 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 924 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 925 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 926 }
6dc93e70
PB		 927
928 return ret;
bc897b1d
LW		 929}
930
ac9da0e0
DSC		 931int mmc_hwpart_config(struct mmc *mmc,
932 const struct mmc_hwpart_conf *conf,
933 enum mmc_hwpart_conf_mode mode)
934{
935 u8 part_attrs = 0;
936 u32 enh_size_mult;
937 u32 enh_start_addr;
938 u32 gp_size_mult[4];
939 u32 max_enh_size_mult;
940 u32 tot_enh_size_mult = 0;
8dda5b0e 941 u8 wr_rel_set;
ac9da0e0
DSC		 942 int i, pidx, err;
943 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
944
945 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
946 return -EINVAL;
947
948 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
d8e3d420 949 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
ac9da0e0
DSC		 950 return -EMEDIUMTYPE;
951 }
952
953 if (!(mmc->part_support & PART_SUPPORT)) {
d8e3d420 954 pr_err("Card does not support partitioning\n");
ac9da0e0
DSC		 955 return -EMEDIUMTYPE;
956 }
957
958 if (!mmc->hc_wp_grp_size) {
d8e3d420 959 pr_err("Card does not define HC WP group size\n");
ac9da0e0
DSC		 960 return -EMEDIUMTYPE;
961 }
962
963 /* check partition alignment and total enhanced size */
964 if (conf->user.enh_size) {
965 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
966 conf->user.enh_start % mmc->hc_wp_grp_size) {
d8e3d420 967 pr_err("User data enhanced area not HC WP group "
ac9da0e0
DSC		 968 "size aligned\n");
969 return -EINVAL;
970 }
971 part_attrs |= EXT_CSD_ENH_USR;
972 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
973 if (mmc->high_capacity) {
974 enh_start_addr = conf->user.enh_start;
975 } else {
976 enh_start_addr = (conf->user.enh_start << 9);
977 }
978 } else {
979 enh_size_mult = 0;
980 enh_start_addr = 0;
981 }
982 tot_enh_size_mult += enh_size_mult;
983
984 for (pidx = 0; pidx < 4; pidx++) {
985 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
d8e3d420 986 pr_err("GP%i partition not HC WP group size "
ac9da0e0
DSC		 987 "aligned\n", pidx+1);
988 return -EINVAL;
989 }
990 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
991 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
992 part_attrs |= EXT_CSD_ENH_GP(pidx);
993 tot_enh_size_mult += gp_size_mult[pidx];
994 }
995 }
996
997 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
d8e3d420 998 pr_err("Card does not support enhanced attribute\n");
ac9da0e0
DSC		 999 return -EMEDIUMTYPE;
1000 }
1001
1002 err = mmc_send_ext_csd(mmc, ext_csd);
1003 if (err)
1004 return err;
1005
1006 max_enh_size_mult =
1007 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1008 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1009 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1010 if (tot_enh_size_mult > max_enh_size_mult) {
d8e3d420 1011 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
ac9da0e0
DSC		 1012 tot_enh_size_mult, max_enh_size_mult);
1013 return -EMEDIUMTYPE;
1014 }
1015
8dda5b0e
DSC		 1016 /* The default value of EXT_CSD_WR_REL_SET is device
1017 * dependent, the values can only be changed if the
1018 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1019 * changed only once and before partitioning is completed. */
1020 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1021 if (conf->user.wr_rel_change) {
1022 if (conf->user.wr_rel_set)
1023 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1024 else
1025 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1026 }
1027 for (pidx = 0; pidx < 4; pidx++) {
1028 if (conf->gp_part[pidx].wr_rel_change) {
1029 if (conf->gp_part[pidx].wr_rel_set)
1030 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1031 else
1032 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1033 }
1034 }
1035
1036 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1037 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1038 puts("Card does not support host controlled partition write "
1039 "reliability settings\n");
1040 return -EMEDIUMTYPE;
1041 }
1042
ac9da0e0
DSC		 1043 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1044 EXT_CSD_PARTITION_SETTING_COMPLETED) {
d8e3d420 1045 pr_err("Card already partitioned\n");
ac9da0e0
DSC		 1046 return -EPERM;
1047 }
1048
1049 if (mode == MMC_HWPART_CONF_CHECK)
1050 return 0;
1051
1052 /* Partitioning requires high-capacity size definitions */
1053 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1054 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1055 EXT_CSD_ERASE_GROUP_DEF, 1);
1056
1057 if (err)
1058 return err;
1059
1060 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1061
1062 /* update erase group size to be high-capacity */
1063 mmc->erase_grp_size =
1064 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1065
1066 }
1067
1068 /* all OK, write the configuration */
1069 for (i = 0; i < 4; i++) {
1070 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1071 EXT_CSD_ENH_START_ADDR+i,
1072 (enh_start_addr >> (i*8)) & 0xFF);
1073 if (err)
1074 return err;
1075 }
1076 for (i = 0; i < 3; i++) {
1077 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1078 EXT_CSD_ENH_SIZE_MULT+i,
1079 (enh_size_mult >> (i*8)) & 0xFF);
1080 if (err)
1081 return err;
1082 }
1083 for (pidx = 0; pidx < 4; pidx++) {
1084 for (i = 0; i < 3; i++) {
1085 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1086 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1087 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1088 if (err)
1089 return err;
1090 }
1091 }
1092 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1093 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1094 if (err)
1095 return err;
1096
1097 if (mode == MMC_HWPART_CONF_SET)
1098 return 0;
1099
8dda5b0e
DSC		 1100 /* The WR_REL_SET is a write-once register but shall be
1101 * written before setting PART_SETTING_COMPLETED. As it is
1102 * write-once we can only write it when completing the
1103 * partitioning. */
1104 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1105 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1106 EXT_CSD_WR_REL_SET, wr_rel_set);
1107 if (err)
1108 return err;
1109 }
1110
ac9da0e0
DSC		 1111 /* Setting PART_SETTING_COMPLETED confirms the partition
1112 * configuration but it only becomes effective after power
1113 * cycle, so we do not adjust the partition related settings
1114 * in the mmc struct. */
1115
1116 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1117 EXT_CSD_PARTITION_SETTING,
1118 EXT_CSD_PARTITION_SETTING_COMPLETED);
1119 if (err)
1120 return err;
1121
1122 return 0;
1123}
1124
e7881d85 1125#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1126int mmc_getcd(struct mmc *mmc)
1127{
1128 int cd;
1129
1130 cd = board_mmc_getcd(mmc);
1131
d4e1da4e 1132 if (cd < 0) {
93bfd616
PA		 1133 if (mmc->cfg->ops->getcd)
1134 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1135 else
1136 cd = 1;
1137 }
48972d90
TR		 1138
1139 return cd;
1140}
8ca51e51 1141#endif
48972d90 1142
fdbb873e 1143static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1144{
1145 struct mmc_cmd cmd;
1146 struct mmc_data data;
1147
1148 /* Switch the frequency */
1149 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1150 cmd.resp_type = MMC_RSP_R1;
1151 cmd.cmdarg = (mode << 31) | 0xffffff;
1152 cmd.cmdarg &= ~(0xf << (group * 4));
1153 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1154
1155 data.dest = (char *)resp;
1156 data.blocksize = 64;
1157 data.blocks = 1;
1158 data.flags = MMC_DATA_READ;
1159
1160 return mmc_send_cmd(mmc, &cmd, &data);
1161}
1162
1163
d0c221fe 1164static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1165{
1166 int err;
1167 struct mmc_cmd cmd;
18e7c8f6
SM		 1168 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1169 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1170 struct mmc_data data;
1171 int timeout;
c10b85d6 1172 u32 sd3_bus_mode;
272cc70b 1173
00e446fa 1174 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
272cc70b 1175
d52ebf10
TC		 1176 if (mmc_host_is_spi(mmc))
1177 return 0;
1178
272cc70b
AF		 1179 /* Read the SCR to find out if this card supports higher speeds */
1180 cmd.cmdidx = MMC_CMD_APP_CMD;
1181 cmd.resp_type = MMC_RSP_R1;
1182 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1183
1184 err = mmc_send_cmd(mmc, &cmd, NULL);
1185
1186 if (err)
1187 return err;
1188
1189 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1190 cmd.resp_type = MMC_RSP_R1;
1191 cmd.cmdarg = 0;
272cc70b
AF		 1192
1193 timeout = 3;
1194
1195retry_scr:
f781dd38 1196 data.dest = (char *)scr;
272cc70b
AF		 1197 data.blocksize = 8;
1198 data.blocks = 1;
1199 data.flags = MMC_DATA_READ;
1200
1201 err = mmc_send_cmd(mmc, &cmd, &data);
1202
1203 if (err) {
1204 if (timeout--)
1205 goto retry_scr;
1206
1207 return err;
1208 }
1209
4e3d89ba
YK		 1210 mmc->scr[0] = __be32_to_cpu(scr[0]);
1211 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1212
1213 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1214 case 0:
1215 mmc->version = SD_VERSION_1_0;
1216 break;
1217 case 1:
1218 mmc->version = SD_VERSION_1_10;
1219 break;
1220 case 2:
1221 mmc->version = SD_VERSION_2;
1222 if ((mmc->scr[0] >> 15) & 0x1)
1223 mmc->version = SD_VERSION_3;
1224 break;
1225 default:
1226 mmc->version = SD_VERSION_1_0;
1227 break;
272cc70b
AF		 1228 }
1229
b44c7083
AS		 1230 if (mmc->scr[0] & SD_DATA_4BIT)
1231 mmc->card_caps |= MMC_MODE_4BIT;
1232
272cc70b
AF		 1233 /* Version 1.0 doesn't support switching */
1234 if (mmc->version == SD_VERSION_1_0)
1235 return 0;
1236
1237 timeout = 4;
1238 while (timeout--) {
1239 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1240 (u8 *)switch_status);
272cc70b
AF		 1241
1242 if (err)
1243 return err;
1244
1245 /* The high-speed function is busy. Try again */
4e3d89ba 1246 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1247 break;
1248 }
1249
272cc70b 1250 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1251 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1252 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1253
c10b85d6
JJH		 1254 /* Version before 3.0 don't support UHS modes */
1255 if (mmc->version < SD_VERSION_3)
1256 return 0;
1257
1258 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1259 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1260 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1261 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1262 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1263 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1264 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1265 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1266 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1267 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1268 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1269
d0c221fe
JJH		 1270 return 0;
1271}
1272
1273static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1274{
1275 int err;
1276
1277 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1278 int speed;
2c3fbf4c 1279
c10b85d6
JJH		 1280 switch (mode) {
1281 case SD_LEGACY:
1282 case UHS_SDR12:
1283 speed = UHS_SDR12_BUS_SPEED;
1284 break;
1285 case SD_HS:
1286 case UHS_SDR25:
1287 speed = UHS_SDR25_BUS_SPEED;
1288 break;
1289 case UHS_SDR50:
1290 speed = UHS_SDR50_BUS_SPEED;
1291 break;
1292 case UHS_DDR50:
1293 speed = UHS_DDR50_BUS_SPEED;
1294 break;
1295 case UHS_SDR104:
1296 speed = UHS_SDR104_BUS_SPEED;
1297 break;
1298 default:
1299 return -EINVAL;
1300 }
1301
1302 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1303 if (err)
1304 return err;
1305
c10b85d6 1306 if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
d0c221fe 1307 return -ENOTSUPP;
272cc70b 1308
d0c221fe
JJH		 1309 return 0;
1310}
1311
1312int sd_select_bus_width(struct mmc *mmc, int w)
1313{
1314 int err;
1315 struct mmc_cmd cmd;
1316
1317 if ((w != 4) && (w != 1))
1318 return -EINVAL;
1319
1320 cmd.cmdidx = MMC_CMD_APP_CMD;
1321 cmd.resp_type = MMC_RSP_R1;
1322 cmd.cmdarg = mmc->rca << 16;
1323
1324 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1325 if (err)
1326 return err;
1327
d0c221fe
JJH		 1328 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1329 cmd.resp_type = MMC_RSP_R1;
1330 if (w == 4)
1331 cmd.cmdarg = 2;
1332 else if (w == 1)
1333 cmd.cmdarg = 0;
1334 err = mmc_send_cmd(mmc, &cmd, NULL);
1335 if (err)
1336 return err;
272cc70b
AF		 1337
1338 return 0;
1339}
1340
3697e599
PF		 1341static int sd_read_ssr(struct mmc *mmc)
1342{
1343 int err, i;
1344 struct mmc_cmd cmd;
1345 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1346 struct mmc_data data;
1347 int timeout = 3;
1348 unsigned int au, eo, et, es;
1349
1350 cmd.cmdidx = MMC_CMD_APP_CMD;
1351 cmd.resp_type = MMC_RSP_R1;
1352 cmd.cmdarg = mmc->rca << 16;
1353
1354 err = mmc_send_cmd(mmc, &cmd, NULL);
1355 if (err)
1356 return err;
1357
1358 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1359 cmd.resp_type = MMC_RSP_R1;
1360 cmd.cmdarg = 0;
1361
1362retry_ssr:
1363 data.dest = (char *)ssr;
1364 data.blocksize = 64;
1365 data.blocks = 1;
1366 data.flags = MMC_DATA_READ;
1367
1368 err = mmc_send_cmd(mmc, &cmd, &data);
1369 if (err) {
1370 if (timeout--)
1371 goto retry_ssr;
1372
1373 return err;
1374 }
1375
1376 for (i = 0; i < 16; i++)
1377 ssr[i] = be32_to_cpu(ssr[i]);
1378
1379 au = (ssr[2] >> 12) & 0xF;
1380 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1381 mmc->ssr.au = sd_au_size[au];
1382 es = (ssr[3] >> 24) & 0xFF;
1383 es |= (ssr[2] & 0xFF) << 8;
1384 et = (ssr[3] >> 18) & 0x3F;
1385 if (es && et) {
1386 eo = (ssr[3] >> 16) & 0x3;
1387 mmc->ssr.erase_timeout = (et * 1000) / es;
1388 mmc->ssr.erase_offset = eo * 1000;
1389 }
1390 } else {
1391 debug("Invalid Allocation Unit Size.\n");
1392 }
1393
1394 return 0;
1395}
1396
272cc70b
AF		 1397/* frequency bases */
1398/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1399static const int fbase[] = {
272cc70b
AF		 1400 10000,
1401 100000,
1402 1000000,
1403 10000000,
1404};
1405
1406/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1407 * to platforms without floating point.
1408 */
61fe076f 1409static const u8 multipliers[] = {
272cc70b
AF		 1410 0, /* reserved */
1411 10,
1412 12,
1413 13,
1414 15,
1415 20,
1416 25,
1417 30,
1418 35,
1419 40,
1420 45,
1421 50,
1422 55,
1423 60,
1424 70,
1425 80,
1426};
1427
d0c221fe
JJH		 1428static inline int bus_width(uint cap)
1429{
1430 if (cap == MMC_MODE_8BIT)
1431 return 8;
1432 if (cap == MMC_MODE_4BIT)
1433 return 4;
1434 if (cap == MMC_MODE_1BIT)
1435 return 1;
d8e3d420 1436 pr_warn("invalid bus witdh capability 0x%x\n", cap);
d0c221fe
JJH		 1437 return 0;
1438}
1439
e7881d85 1440#if !CONFIG_IS_ENABLED(DM_MMC)
ec841209
KVA		 1441static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1442{
1443 return -ENOTSUPP;
1444}
1445
318a7a57
JJH		 1446static void mmc_send_init_stream(struct mmc *mmc)
1447{
1448}
1449
2a4d212f 1450static int mmc_set_ios(struct mmc *mmc)
272cc70b 1451{
2a4d212f
KVA		 1452 int ret = 0;
1453
93bfd616 1454 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1455 ret = mmc->cfg->ops->set_ios(mmc);
1456
1457 return ret;
272cc70b 1458}
8ca51e51 1459#endif
272cc70b 1460
35f67820 1461int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1462{
93bfd616
PA		 1463 if (clock > mmc->cfg->f_max)
1464 clock = mmc->cfg->f_max;
272cc70b 1465
93bfd616
PA		 1466 if (clock < mmc->cfg->f_min)
1467 clock = mmc->cfg->f_min;
272cc70b
AF		 1468
1469 mmc->clock = clock;
35f67820 1470 mmc->clk_disable = disable;
272cc70b 1471
2a4d212f 1472 return mmc_set_ios(mmc);
272cc70b
AF		 1473}
1474
2a4d212f 1475static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1476{
1477 mmc->bus_width = width;
1478
2a4d212f 1479 return mmc_set_ios(mmc);
272cc70b
AF		 1480}
1481
4c9d2aaa
JJH		 1482#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1483/*
1484 * helper function to display the capabilities in a human
1485 * friendly manner. The capabilities include bus width and
1486 * supported modes.
1487 */
1488void mmc_dump_capabilities(const char *text, uint caps)
1489{
1490 enum bus_mode mode;
1491
1492 printf("%s: widths [", text);
1493 if (caps & MMC_MODE_8BIT)
1494 printf("8, ");
1495 if (caps & MMC_MODE_4BIT)
1496 printf("4, ");
d0c221fe
JJH		 1497 if (caps & MMC_MODE_1BIT)
1498 printf("1, ");
1499 printf("\b\b] modes [");
4c9d2aaa
JJH		 1500 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1501 if (MMC_CAP(mode) & caps)
1502 printf("%s, ", mmc_mode_name(mode));
1503 printf("\b\b]\n");
1504}
1505#endif
1506
d0c221fe
JJH		 1507struct mode_width_tuning {
1508 enum bus_mode mode;
1509 uint widths;
634d4849 1510 uint tuning;
d0c221fe
JJH		 1511};
1512
bc1e3272
JJH		 1513int mmc_voltage_to_mv(enum mmc_voltage voltage)
1514{
1515 switch (voltage) {
1516 case MMC_SIGNAL_VOLTAGE_000: return 0;
1517 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1518 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1519 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1520 }
1521 return -EINVAL;
1522}
1523
aff5d3c8
KVA		 1524static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1525{
bc1e3272
JJH		 1526 int err;
1527
1528 if (mmc->signal_voltage == signal_voltage)
1529 return 0;
1530
aff5d3c8 1531 mmc->signal_voltage = signal_voltage;
bc1e3272
JJH		 1532 err = mmc_set_ios(mmc);
1533 if (err)
1534 debug("unable to set voltage (err %d)\n", err);
1535
1536 return err;
aff5d3c8
KVA		 1537}
1538
d0c221fe 1539static const struct mode_width_tuning sd_modes_by_pref[] = {
c10b85d6
JJH		 1540 {
1541 .mode = UHS_SDR104,
1542 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1543 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1544 },
1545 {
1546 .mode = UHS_SDR50,
1547 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1548 },
1549 {
1550 .mode = UHS_DDR50,
1551 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1552 },
1553 {
1554 .mode = UHS_SDR25,
1555 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1556 },
d0c221fe
JJH		 1557 {
1558 .mode = SD_HS,
1559 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1560 },
c10b85d6
JJH		 1561 {
1562 .mode = UHS_SDR12,
1563 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1564 },
d0c221fe
JJH		 1565 {
1566 .mode = SD_LEGACY,
1567 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1568 }
1569};
1570
1571#define for_each_sd_mode_by_pref(caps, mwt) \
1572 for (mwt = sd_modes_by_pref;\
1573 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1574 mwt++) \
1575 if (caps & MMC_CAP(mwt->mode))
1576
01298da3 1577static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1578{
1579 int err;
d0c221fe
JJH		 1580 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1581 const struct mode_width_tuning *mwt;
c10b85d6
JJH		 1582 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1583 uint caps;
1584
52d241df
JJH		 1585#ifdef DEBUG
1586 mmc_dump_capabilities("sd card", card_caps);
1da8eb59 1587 mmc_dump_capabilities("host", mmc->host_caps);
52d241df 1588#endif
8ac8a263 1589
8ac8a263 1590 /* Restrict card's capabilities by what the host can do */
1da8eb59 1591 caps = card_caps & mmc->host_caps;
d0c221fe 1592
c10b85d6
JJH		 1593 if (!uhs_en)
1594 caps &= ~UHS_CAPS;
1595
1596 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1597 uint *w;
1598
1599 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1600 if (*w & caps & mwt->widths) {
d0c221fe
JJH		 1601 debug("trying mode %s width %d (at %d MHz)\n",
1602 mmc_mode_name(mwt->mode),
1603 bus_width(*w),
1604 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1605
1606 /* configure the bus width (card + host) */
1607 err = sd_select_bus_width(mmc, bus_width(*w));
1608 if (err)
1609 goto error;
1610 mmc_set_bus_width(mmc, bus_width(*w));
1611
1612 /* configure the bus mode (card) */
1613 err = sd_set_card_speed(mmc, mwt->mode);
1614 if (err)
1615 goto error;
1616
1617 /* configure the bus mode (host) */
1618 mmc_select_mode(mmc, mwt->mode);
35f67820 1619 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe 1620
c10b85d6
JJH		 1621 /* execute tuning if needed */
1622 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1623 err = mmc_execute_tuning(mmc,
1624 mwt->tuning);
1625 if (err) {
1626 debug("tuning failed\n");
1627 goto error;
1628 }
1629 }
1630
d0c221fe
JJH		 1631 err = sd_read_ssr(mmc);
1632 if (!err)
1633 return 0;
1634
d8e3d420 1635 pr_warn("bad ssr\n");
d0c221fe
JJH		 1636
1637error:
1638 /* revert to a safer bus speed */
1639 mmc_select_mode(mmc, SD_LEGACY);
35f67820 1640 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe
JJH		 1641 }
1642 }
8ac8a263
JJH		 1643 }
1644
d0c221fe
JJH		 1645 printf("unable to select a mode\n");
1646 return -ENOTSUPP;
8ac8a263
JJH		 1647}
1648
7382e691
JJH		 1649/*
1650 * read the compare the part of ext csd that is constant.
1651 * This can be used to check that the transfer is working
1652 * as expected.
1653 */
1654static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1655{
7382e691 1656 int err;
dfda9d88 1657 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1658 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1659
1de06b9f
JJH		 1660 if (mmc->version < MMC_VERSION_4)
1661 return 0;
1662
7382e691
JJH		 1663 err = mmc_send_ext_csd(mmc, test_csd);
1664 if (err)
1665 return err;
1666
1667 /* Only compare read only fields */
1668 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1669 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1670 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1671 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1672 ext_csd[EXT_CSD_REV]
1673 == test_csd[EXT_CSD_REV] &&
1674 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1675 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1676 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1677 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1678 return 0;
1679
1680 return -EBADMSG;
1681}
1682
bc1e3272
JJH		 1683static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1684 uint32_t allowed_mask)
1685{
1686 u32 card_mask = 0;
1687
1688 switch (mode) {
1689 case MMC_HS_200:
1690 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
1691 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1692 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
1693 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1694 break;
1695 case MMC_DDR_52:
1696 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1697 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1698 MMC_SIGNAL_VOLTAGE_180;
1699 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1700 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1701 break;
1702 default:
1703 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1704 break;
1705 }
1706
1707 while (card_mask & allowed_mask) {
1708 enum mmc_voltage best_match;
1709
1710 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1711 if (!mmc_set_signal_voltage(mmc, best_match))
1712 return 0;
1713
1714 allowed_mask &= ~best_match;
1715 }
1716
1717 return -ENOTSUPP;
1718}
1719
3862b854
JJH		 1720static const struct mode_width_tuning mmc_modes_by_pref[] = {
1721 {
1722 .mode = MMC_HS_200,
1723 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1724 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854
JJH		 1725 },
1726 {
1727 .mode = MMC_DDR_52,
1728 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1729 },
1730 {
1731 .mode = MMC_HS_52,
1732 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1733 },
1734 {
1735 .mode = MMC_HS,
1736 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1737 },
1738 {
1739 .mode = MMC_LEGACY,
1740 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1741 }
1742};
1743
1744#define for_each_mmc_mode_by_pref(caps, mwt) \
1745 for (mwt = mmc_modes_by_pref;\
1746 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1747 mwt++) \
1748 if (caps & MMC_CAP(mwt->mode))
1749
1750static const struct ext_csd_bus_width {
1751 uint cap;
1752 bool is_ddr;
1753 uint ext_csd_bits;
1754} ext_csd_bus_width[] = {
1755 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1756 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1757 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1758 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1759 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1760};
1761
1762#define for_each_supported_width(caps, ddr, ecbv) \
1763 for (ecbv = ext_csd_bus_width;\
1764 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1765 ecbv++) \
1766 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1767
01298da3 1768static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 1769{
8ac8a263 1770 int err;
3862b854
JJH		 1771 const struct mode_width_tuning *mwt;
1772 const struct ext_csd_bus_width *ecbw;
8ac8a263 1773
52d241df
JJH		 1774#ifdef DEBUG
1775 mmc_dump_capabilities("mmc", card_caps);
1da8eb59 1776 mmc_dump_capabilities("host", mmc->host_caps);
52d241df
JJH		 1777#endif
1778
8ac8a263 1779 /* Restrict card's capabilities by what the host can do */
1da8eb59 1780 card_caps &= mmc->host_caps;
8ac8a263
JJH		 1781
1782 /* Only version 4 of MMC supports wider bus widths */
1783 if (mmc->version < MMC_VERSION_4)
1784 return 0;
1785
dfda9d88
JJH		 1786 if (!mmc->ext_csd) {
1787 debug("No ext_csd found!\n"); /* this should enver happen */
1788 return -ENOTSUPP;
1789 }
1790
01298da3
JJH		 1791 mmc_set_clock(mmc, mmc->legacy_speed, false);
1792
1793 for_each_mmc_mode_by_pref(card_caps, mwt) {
1794 for_each_supported_width(card_caps & mwt->widths,
3862b854 1795 mmc_is_mode_ddr(mwt->mode), ecbw) {
bc1e3272 1796 enum mmc_voltage old_voltage;
3862b854
JJH		 1797 debug("trying mode %s width %d (at %d MHz)\n",
1798 mmc_mode_name(mwt->mode),
1799 bus_width(ecbw->cap),
1800 mmc_mode2freq(mmc, mwt->mode) / 1000000);
bc1e3272
JJH		 1801 old_voltage = mmc->signal_voltage;
1802 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1803 MMC_ALL_SIGNAL_VOLTAGE);
1804 if (err)
1805 continue;
1806
3862b854
JJH		 1807 /* configure the bus width (card + host) */
1808 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1809 EXT_CSD_BUS_WIDTH,
1810 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1811 if (err)
1812 goto error;
1813 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 1814
3862b854
JJH		 1815 /* configure the bus speed (card) */
1816 err = mmc_set_card_speed(mmc, mwt->mode);
1817 if (err)
1818 goto error;
1819
1820 /*
1821 * configure the bus width AND the ddr mode (card)
1822 * The host side will be taken care of in the next step
1823 */
1824 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1825 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1826 EXT_CSD_BUS_WIDTH,
1827 ecbw->ext_csd_bits);
1828 if (err)
1829 goto error;
1830 }
8ac8a263 1831
3862b854
JJH		 1832 /* configure the bus mode (host) */
1833 mmc_select_mode(mmc, mwt->mode);
35f67820 1834 mmc_set_clock(mmc, mmc->tran_speed, false);
8ac8a263 1835
634d4849
KVA		 1836 /* execute tuning if needed */
1837 if (mwt->tuning) {
1838 err = mmc_execute_tuning(mmc, mwt->tuning);
1839 if (err) {
1840 debug("tuning failed\n");
1841 goto error;
1842 }
1843 }
1844
3862b854
JJH		 1845 /* do a transfer to check the configuration */
1846 err = mmc_read_and_compare_ext_csd(mmc);
1847 if (!err)
1848 return 0;
1849error:
bc1e3272 1850 mmc_set_signal_voltage(mmc, old_voltage);
3862b854
JJH		 1851 /* if an error occured, revert to a safer bus mode */
1852 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1853 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1854 mmc_select_mode(mmc, MMC_LEGACY);
1855 mmc_set_bus_width(mmc, 1);
1856 }
8ac8a263
JJH		 1857 }
1858
d8e3d420 1859 pr_err("unable to select a mode\n");
8ac8a263 1860
3862b854 1861 return -ENOTSUPP;
8ac8a263
JJH		 1862}
1863
dfda9d88 1864static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 1865{
1866 int err, i;
1867 u64 capacity;
1868 bool has_parts = false;
1869 bool part_completed;
f7d5dffc 1870 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
c744b6f6
JJH		 1871
1872 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1873 return 0;
1874
1875 /* check ext_csd version and capacity */
1876 err = mmc_send_ext_csd(mmc, ext_csd);
1877 if (err)
f7d5dffc
JJH		 1878 goto error;
1879
1880 /* store the ext csd for future reference */
1881 if (!mmc->ext_csd)
1882 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
1883 if (!mmc->ext_csd)
1884 return -ENOMEM;
1885 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
1886
c744b6f6
JJH		 1887 if (ext_csd[EXT_CSD_REV] >= 2) {
1888 /*
1889 * According to the JEDEC Standard, the value of
1890 * ext_csd's capacity is valid if the value is more
1891 * than 2GB
1892 */
1893 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1894 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1895 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1896 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1897 capacity *= MMC_MAX_BLOCK_LEN;
1898 if ((capacity >> 20) > 2 * 1024)
1899 mmc->capacity_user = capacity;
1900 }
1901
1902 switch (ext_csd[EXT_CSD_REV]) {
1903 case 1:
1904 mmc->version = MMC_VERSION_4_1;
1905 break;
1906 case 2:
1907 mmc->version = MMC_VERSION_4_2;
1908 break;
1909 case 3:
1910 mmc->version = MMC_VERSION_4_3;
1911 break;
1912 case 5:
1913 mmc->version = MMC_VERSION_4_41;
1914 break;
1915 case 6:
1916 mmc->version = MMC_VERSION_4_5;
1917 break;
1918 case 7:
1919 mmc->version = MMC_VERSION_5_0;
1920 break;
1921 case 8:
1922 mmc->version = MMC_VERSION_5_1;
1923 break;
1924 }
1925
1926 /* The partition data may be non-zero but it is only
1927 * effective if PARTITION_SETTING_COMPLETED is set in
1928 * EXT_CSD, so ignore any data if this bit is not set,
1929 * except for enabling the high-capacity group size
1930 * definition (see below).
1931 */
1932 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1933 EXT_CSD_PARTITION_SETTING_COMPLETED);
1934
1935 /* store the partition info of emmc */
1936 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1937 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1938 ext_csd[EXT_CSD_BOOT_MULT])
1939 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1940 if (part_completed &&
1941 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1942 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1943
1944 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1945
1946 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1947
1948 for (i = 0; i < 4; i++) {
1949 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1950 uint mult = (ext_csd[idx + 2] << 16) +
1951 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1952 if (mult)
1953 has_parts = true;
1954 if (!part_completed)
1955 continue;
1956 mmc->capacity_gp[i] = mult;
1957 mmc->capacity_gp[i] *=
1958 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1959 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1960 mmc->capacity_gp[i] <<= 19;
1961 }
1962
1963 if (part_completed) {
1964 mmc->enh_user_size =
1965 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1966 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1967 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1968 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1969 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1970 mmc->enh_user_size <<= 19;
1971 mmc->enh_user_start =
1972 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1973 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1974 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1975 ext_csd[EXT_CSD_ENH_START_ADDR];
1976 if (mmc->high_capacity)
1977 mmc->enh_user_start <<= 9;
1978 }
1979
1980 /*
1981 * Host needs to enable ERASE_GRP_DEF bit if device is
1982 * partitioned. This bit will be lost every time after a reset
1983 * or power off. This will affect erase size.
1984 */
1985 if (part_completed)
1986 has_parts = true;
1987 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1988 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1989 has_parts = true;
1990 if (has_parts) {
1991 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1992 EXT_CSD_ERASE_GROUP_DEF, 1);
1993
1994 if (err)
f7d5dffc 1995 goto error;
c744b6f6
JJH		 1996
1997 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1998 }
1999
2000 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2001 /* Read out group size from ext_csd */
2002 mmc->erase_grp_size =
2003 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2004 /*
2005 * if high capacity and partition setting completed
2006 * SEC_COUNT is valid even if it is smaller than 2 GiB
2007 * JEDEC Standard JESD84-B45, 6.2.4
2008 */
2009 if (mmc->high_capacity && part_completed) {
2010 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2011 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2012 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2013 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2014 capacity *= MMC_MAX_BLOCK_LEN;
2015 mmc->capacity_user = capacity;
2016 }
2017 } else {
2018 /* Calculate the group size from the csd value. */
2019 int erase_gsz, erase_gmul;
2020
2021 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2022 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2023 mmc->erase_grp_size = (erase_gsz + 1)
2024 * (erase_gmul + 1);
2025 }
2026
2027 mmc->hc_wp_grp_size = 1024
2028 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2029 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2030
2031 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2032
2033 return 0;
f7d5dffc
JJH		 2034error:
2035 if (mmc->ext_csd) {
2036 free(mmc->ext_csd);
2037 mmc->ext_csd = NULL;
2038 }
2039 return err;
c744b6f6
JJH		 2040}
2041
fdbb873e 2042static int mmc_startup(struct mmc *mmc)
272cc70b 2043{
f866a46d 2044 int err, i;
272cc70b 2045 uint mult, freq;
c744b6f6 2046 u64 cmult, csize;
272cc70b 2047 struct mmc_cmd cmd;
c40fdca6 2048 struct blk_desc *bdesc;
272cc70b 2049
d52ebf10
TC		 2050#ifdef CONFIG_MMC_SPI_CRC_ON
2051 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2052 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2053 cmd.resp_type = MMC_RSP_R1;
2054 cmd.cmdarg = 1;
d52ebf10 2055 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 2056 if (err)
2057 return err;
2058 }
2059#endif
2060
272cc70b 2061 /* Put the Card in Identify Mode */
d52ebf10
TC		 2062 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2063 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 2064 cmd.resp_type = MMC_RSP_R2;
2065 cmd.cmdarg = 0;
272cc70b
AF		 2066
2067 err = mmc_send_cmd(mmc, &cmd, NULL);
2068
83dc4227
KVA		 2069#ifdef CONFIG_MMC_QUIRKS
2070 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2071 int retries = 4;
2072 /*
2073 * It has been seen that SEND_CID may fail on the first
2074 * attempt, let's try a few more time
2075 */
2076 do {
2077 err = mmc_send_cmd(mmc, &cmd, NULL);
2078 if (!err)
2079 break;
2080 } while (retries--);
2081 }
2082#endif
2083
272cc70b
AF		 2084 if (err)
2085 return err;
2086
2087 memcpy(mmc->cid, cmd.response, 16);
2088
2089 /*
2090 * For MMC cards, set the Relative Address.
2091 * For SD cards, get the Relatvie Address.
2092 * This also puts the cards into Standby State
2093 */
d52ebf10
TC		 2094 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2095 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2096 cmd.cmdarg = mmc->rca << 16;
2097 cmd.resp_type = MMC_RSP_R6;
272cc70b 2098
d52ebf10 2099 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2100
d52ebf10
TC		 2101 if (err)
2102 return err;
272cc70b 2103
d52ebf10
TC		 2104 if (IS_SD(mmc))
2105 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2106 }
272cc70b
AF		 2107
2108 /* Get the Card-Specific Data */
2109 cmd.cmdidx = MMC_CMD_SEND_CSD;
2110 cmd.resp_type = MMC_RSP_R2;
2111 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 2112
2113 err = mmc_send_cmd(mmc, &cmd, NULL);
2114
2115 if (err)
2116 return err;
2117
998be3dd
RV		 2118 mmc->csd[0] = cmd.response[0];
2119 mmc->csd[1] = cmd.response[1];
2120 mmc->csd[2] = cmd.response[2];
2121 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 2122
2123 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 2124 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 2125
2126 switch (version) {
53e8e40b
BM		 2127 case 0:
2128 mmc->version = MMC_VERSION_1_2;
2129 break;
2130 case 1:
2131 mmc->version = MMC_VERSION_1_4;
2132 break;
2133 case 2:
2134 mmc->version = MMC_VERSION_2_2;
2135 break;
2136 case 3:
2137 mmc->version = MMC_VERSION_3;
2138 break;
2139 case 4:
2140 mmc->version = MMC_VERSION_4;
2141 break;
2142 default:
2143 mmc->version = MMC_VERSION_1_2;
2144 break;
272cc70b
AF		 2145 }
2146 }
2147
2148 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 2149 freq = fbase[(cmd.response[0] & 0x7)];
2150 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 2151
35f9e196 2152 mmc->legacy_speed = freq * mult;
35f9e196 2153 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2154
ab71188c 2155 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2156 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 2157
2158 if (IS_SD(mmc))
2159 mmc->write_bl_len = mmc->read_bl_len;
2160 else
998be3dd 2161 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 2162
2163 if (mmc->high_capacity) {
2164 csize = (mmc->csd[1] & 0x3f) << 16
2165 | (mmc->csd[2] & 0xffff0000) >> 16;
2166 cmult = 8;
2167 } else {
2168 csize = (mmc->csd[1] & 0x3ff) << 2
2169 | (mmc->csd[2] & 0xc0000000) >> 30;
2170 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2171 }
2172
f866a46d
SW		 2173 mmc->capacity_user = (csize + 1) << (cmult + 2);
2174 mmc->capacity_user *= mmc->read_bl_len;
2175 mmc->capacity_boot = 0;
2176 mmc->capacity_rpmb = 0;
2177 for (i = 0; i < 4; i++)
2178 mmc->capacity_gp[i] = 0;
272cc70b 2179
8bfa195e
SG		 2180 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2181 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2182
8bfa195e
SG		 2183 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2184 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2185
ab71188c
MN		 2186 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2187 cmd.cmdidx = MMC_CMD_SET_DSR;
2188 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2189 cmd.resp_type = MMC_RSP_NONE;
2190 if (mmc_send_cmd(mmc, &cmd, NULL))
d8e3d420 2191 pr_warn("MMC: SET_DSR failed\n");
ab71188c
MN		 2192 }
2193
272cc70b 2194 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2195 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2196 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2197 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2198 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2199 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2200
d52ebf10
TC		 2201 if (err)
2202 return err;
2203 }
272cc70b 2204
e6f99a56
LW		 2205 /*
2206 * For SD, its erase group is always one sector
2207 */
2208 mmc->erase_grp_size = 1;
bc897b1d 2209 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2210
dfda9d88 2211 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2212 if (err)
2213 return err;
d23e2c09 2214
c40fdca6 2215 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2216 if (err)
2217 return err;
2218
01298da3
JJH		 2219 if (IS_SD(mmc)) {
2220 err = sd_get_capabilities(mmc);
2221 if (err)
2222 return err;
2223 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2224 } else {
2225 err = mmc_get_capabilities(mmc);
2226 if (err)
2227 return err;
2228 mmc_select_mode_and_width(mmc, mmc->card_caps);
2229 }
272cc70b
AF		 2230
2231 if (err)
2232 return err;
2233
01298da3 2234 mmc->best_mode = mmc->selected_mode;
ad5fd922 2235
5af8f45c
AG		 2236 /* Fix the block length for DDR mode */
2237 if (mmc->ddr_mode) {
2238 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2239 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2240 }
2241
272cc70b 2242 /* fill in device description */
c40fdca6
SG		 2243 bdesc = mmc_get_blk_desc(mmc);
2244 bdesc->lun = 0;
2245 bdesc->hwpart = 0;
2246 bdesc->type = 0;
2247 bdesc->blksz = mmc->read_bl_len;
2248 bdesc->log2blksz = LOG2(bdesc->blksz);
2249 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2250#if !defined(CONFIG_SPL_BUILD) || \
2251 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2252 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 2253 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2254 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2255 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2256 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2257 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2258 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2259 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2260 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2261 (mmc->cid[2] >> 16) & 0xf);
56196826 2262#else
c40fdca6
SG		 2263 bdesc->vendor[0] = 0;
2264 bdesc->product[0] = 0;
2265 bdesc->revision[0] = 0;
56196826 2266#endif
122efd43 2267#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
c40fdca6 2268 part_init(bdesc);
122efd43 2269#endif
272cc70b
AF		 2270
2271 return 0;
2272}
2273
fdbb873e 2274static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2275{
2276 struct mmc_cmd cmd;
2277 int err;
2278
2279 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2280 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2281 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2282 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2283
2284 err = mmc_send_cmd(mmc, &cmd, NULL);
2285
2286 if (err)
2287 return err;
2288
998be3dd 2289 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2290 return -EOPNOTSUPP;
272cc70b
AF		 2291 else
2292 mmc->version = SD_VERSION_2;
2293
2294 return 0;
2295}
2296
c4d660d4 2297#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2298/* board-specific MMC power initializations. */
2299__weak void board_mmc_power_init(void)
2300{
2301}
05cbeb7c 2302#endif
95de9ab2 2303
2051aefe
PF		 2304static int mmc_power_init(struct mmc *mmc)
2305{
c4d660d4 2306#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2307#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2308 int ret;
2309
2310 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2311 &mmc->vmmc_supply);
2312 if (ret)
288db7c7 2313 debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2314
06ec045f
JJH		 2315 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2316 &mmc->vqmmc_supply);
2317 if (ret)
2318 debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2319#endif
2320#else /* !CONFIG_DM_MMC */
2321 /*
2322 * Driver model should use a regulator, as above, rather than calling
2323 * out to board code.
2324 */
2325 board_mmc_power_init();
2326#endif
2327 return 0;
2328}
2329
2330/*
2331 * put the host in the initial state:
2332 * - turn on Vdd (card power supply)
2333 * - configure the bus width and clock to minimal values
2334 */
2335static void mmc_set_initial_state(struct mmc *mmc)
2336{
2337 int err;
2338
2339 /* First try to set 3.3V. If it fails set to 1.8V */
2340 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2341 if (err != 0)
2342 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2343 if (err != 0)
d8e3d420 2344 pr_warn("mmc: failed to set signal voltage\n");
fb7c3beb
KVA		 2345
2346 mmc_select_mode(mmc, MMC_LEGACY);
2347 mmc_set_bus_width(mmc, 1);
35f67820 2348 mmc_set_clock(mmc, 0, false);
fb7c3beb 2349}
06ec045f 2350
fb7c3beb
KVA		 2351static int mmc_power_on(struct mmc *mmc)
2352{
2353#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2354 if (mmc->vmmc_supply) {
fb7c3beb
KVA		 2355 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2356
06ec045f
JJH		 2357 if (ret) {
2358 puts("Error enabling VMMC supply\n");
2359 return ret;
2360 }
2051aefe 2361 }
05cbeb7c 2362#endif
fb7c3beb
KVA		 2363 return 0;
2364}
2365
2366static int mmc_power_off(struct mmc *mmc)
2367{
2e7410d7 2368 mmc_set_clock(mmc, 1, true);
fb7c3beb
KVA		 2369#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2370 if (mmc->vmmc_supply) {
2371 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2372
2373 if (ret) {
c10b85d6 2374 debug("Error disabling VMMC supply\n");
fb7c3beb
KVA		 2375 return ret;
2376 }
2377 }
2051aefe
PF		 2378#endif
2379 return 0;
2380}
2381
fb7c3beb
KVA		 2382static int mmc_power_cycle(struct mmc *mmc)
2383{
2384 int ret;
2385
2386 ret = mmc_power_off(mmc);
2387 if (ret)
2388 return ret;
2389 /*
2390 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2391 * to be on the safer side.
2392 */
2393 udelay(2000);
2394 return mmc_power_on(mmc);
2395}
2396
e9550449 2397int mmc_start_init(struct mmc *mmc)
272cc70b 2398{
8ca51e51 2399 bool no_card;
c10b85d6 2400 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2401 int err;
272cc70b 2402
1da8eb59
JJH		 2403 /*
2404 * all hosts are capable of 1 bit bus-width and able to use the legacy
2405 * timings.
2406 */
2407 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2408 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
04a2ea24 2409
ab769f22 2410 /* we pretend there's no card when init is NULL */
8ca51e51 2411 no_card = mmc_getcd(mmc) == 0;
e7881d85 2412#if !CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2413 no_card = no_card || (mmc->cfg->ops->init == NULL);
2414#endif
2415 if (no_card) {
48972d90 2416 mmc->has_init = 0;
56196826 2417#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 2418 printf("MMC: no card present\n");
56196826 2419#endif
915ffa52 2420 return -ENOMEDIUM;
48972d90
TR		 2421 }
2422
bc897b1d
LW		 2423 if (mmc->has_init)
2424 return 0;
2425
5a8dbdc6
YL		 2426#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2427 mmc_adapter_card_type_ident();
2428#endif
2051aefe
PF		 2429 err = mmc_power_init(mmc);
2430 if (err)
2431 return err;
95de9ab2 2432
83dc4227
KVA		 2433#ifdef CONFIG_MMC_QUIRKS
2434 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2435 MMC_QUIRK_RETRY_SEND_CID;
2436#endif
2437
04a2ea24
JJH		 2438 err = mmc_power_cycle(mmc);
2439 if (err) {
2440 /*
2441 * if power cycling is not supported, we should not try
2442 * to use the UHS modes, because we wouldn't be able to
2443 * recover from an error during the UHS initialization.
2444 */
2445 debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2446 uhs_en = false;
2447 mmc->host_caps &= ~UHS_CAPS;
2448 err = mmc_power_on(mmc);
2449 }
fb7c3beb
KVA		 2450 if (err)
2451 return err;
2452
e7881d85 2453#if CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2454 /* The device has already been probed ready for use */
2455#else
ab769f22 2456 /* made sure it's not NULL earlier */
93bfd616 2457 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 2458 if (err)
2459 return err;
8ca51e51 2460#endif
786e8f81 2461 mmc->ddr_mode = 0;
aff5d3c8 2462
c10b85d6 2463retry:
fb7c3beb 2464 mmc_set_initial_state(mmc);
318a7a57
JJH		 2465 mmc_send_init_stream(mmc);
2466
272cc70b
AF		 2467 /* Reset the Card */
2468 err = mmc_go_idle(mmc);
2469
2470 if (err)
2471 return err;
2472
bc897b1d 2473 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 2474 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2475
272cc70b 2476 /* Test for SD version 2 */
afd5932b 2477 err = mmc_send_if_cond(mmc);
272cc70b 2478
272cc70b 2479 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2480 err = sd_send_op_cond(mmc, uhs_en);
2481 if (err && uhs_en) {
2482 uhs_en = false;
2483 mmc_power_cycle(mmc);
2484 goto retry;
2485 }
272cc70b
AF		 2486
2487 /* If the command timed out, we check for an MMC card */
915ffa52 2488 if (err == -ETIMEDOUT) {
272cc70b
AF		 2489 err = mmc_send_op_cond(mmc);
2490
bd47c135 2491 if (err) {
56196826 2492#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 2493 pr_err("Card did not respond to voltage select!\n");
56196826 2494#endif
915ffa52 2495 return -EOPNOTSUPP;
272cc70b
AF		 2496 }
2497 }
2498
bd47c135 2499 if (!err)
e9550449
CLC		 2500 mmc->init_in_progress = 1;
2501
2502 return err;
2503}
2504
2505static int mmc_complete_init(struct mmc *mmc)
2506{
2507 int err = 0;
2508
bd47c135 2509 mmc->init_in_progress = 0;
e9550449
CLC		 2510 if (mmc->op_cond_pending)
2511 err = mmc_complete_op_cond(mmc);
2512
2513 if (!err)
2514 err = mmc_startup(mmc);
bc897b1d
LW		 2515 if (err)
2516 mmc->has_init = 0;
2517 else
2518 mmc->has_init = 1;
e9550449
CLC		 2519 return err;
2520}
2521
2522int mmc_init(struct mmc *mmc)
2523{
bd47c135 2524 int err = 0;
ce9eca94 2525 __maybe_unused unsigned start;
c4d660d4 2526#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 2527 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 2528
33fb211d
SG		 2529 upriv->mmc = mmc;
2530#endif
e9550449
CLC		 2531 if (mmc->has_init)
2532 return 0;
d803fea5
MZ		 2533
2534 start = get_timer(0);
2535
e9550449
CLC		 2536 if (!mmc->init_in_progress)
2537 err = mmc_start_init(mmc);
2538
bd47c135 2539 if (!err)
e9550449 2540 err = mmc_complete_init(mmc);
919b4858
JT		 2541 if (err)
2542 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2543
bc897b1d 2544 return err;
272cc70b
AF		 2545}
2546
ab71188c
MN		 2547int mmc_set_dsr(struct mmc *mmc, u16 val)
2548{
2549 mmc->dsr = val;
2550 return 0;
2551}
2552
cee9ab7c
JH		 2553/* CPU-specific MMC initializations */
2554__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 2555{
2556 return -1;
2557}
2558
cee9ab7c
JH		 2559/* board-specific MMC initializations. */
2560__weak int board_mmc_init(bd_t *bis)
2561{
2562 return -1;
2563}
272cc70b 2564
e9550449
CLC		 2565void mmc_set_preinit(struct mmc *mmc, int preinit)
2566{
2567 mmc->preinit = preinit;
2568}
2569
c4d660d4 2570#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
8e3332e2
SS		 2571static int mmc_probe(bd_t *bis)
2572{
2573 return 0;
2574}
c4d660d4 2575#elif CONFIG_IS_ENABLED(DM_MMC)
8e3332e2
SS		 2576static int mmc_probe(bd_t *bis)
2577{
4a1db6d8 2578 int ret, i;
8e3332e2 2579 struct uclass *uc;
4a1db6d8 2580 struct udevice *dev;
8e3332e2
SS		 2581
2582 ret = uclass_get(UCLASS_MMC, &uc);
2583 if (ret)
2584 return ret;
2585
4a1db6d8
SG		 2586 /*
2587 * Try to add them in sequence order. Really with driver model we
2588 * should allow holes, but the current MMC list does not allow that.
2589 * So if we request 0, 1, 3 we will get 0, 1, 2.
2590 */
2591 for (i = 0; ; i++) {
2592 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2593 if (ret == -ENODEV)
2594 break;
2595 }
2596 uclass_foreach_dev(dev, uc) {
2597 ret = device_probe(dev);
8e3332e2 2598 if (ret)
d8e3d420 2599 pr_err("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 2600 }
2601
2602 return 0;
2603}
2604#else
2605static int mmc_probe(bd_t *bis)
2606{
2607 if (board_mmc_init(bis) < 0)
2608 cpu_mmc_init(bis);
2609
2610 return 0;
2611}
2612#endif
e9550449 2613
272cc70b
AF		 2614int mmc_initialize(bd_t *bis)
2615{
1b26bab1 2616 static int initialized = 0;
8e3332e2 2617 int ret;
1b26bab1
DK		 2618 if (initialized) /* Avoid initializing mmc multiple times */
2619 return 0;
2620 initialized = 1;
2621
c4d660d4 2622#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 2623#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 2624 mmc_list_init();
b5b838f1 2625#endif
c40fdca6 2626#endif
8e3332e2
SS		 2627 ret = mmc_probe(bis);
2628 if (ret)
2629 return ret;
272cc70b 2630
bb0dc108 2631#ifndef CONFIG_SPL_BUILD
272cc70b 2632 print_mmc_devices(',');
bb0dc108 2633#endif
272cc70b 2634
c40fdca6 2635 mmc_do_preinit();
272cc70b
AF		 2636 return 0;
2637}
cd3d4880
TM		 2638
2639#ifdef CONFIG_CMD_BKOPS_ENABLE
2640int mmc_set_bkops_enable(struct mmc *mmc)
2641{
2642 int err;
2643 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2644
2645 err = mmc_send_ext_csd(mmc, ext_csd);
2646 if (err) {
2647 puts("Could not get ext_csd register values\n");
2648 return err;
2649 }
2650
2651 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2652 puts("Background operations not supported on device\n");
2653 return -EMEDIUMTYPE;
2654 }
2655
2656 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2657 puts("Background operations already enabled\n");
2658 return 0;
2659 }
2660
2661 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2662 if (err) {
2663 puts("Failed to enable manual background operations\n");
2664 return err;
2665 }
2666
2667 puts("Enabled manual background operations\n");
2668
2669 return 0;
2670}
2671#endif
"Das U-Boot" Source Tree