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dm: mmc: Add an MMC uclass
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
d4622df3 13#include <errno.h>
272cc70b
AF		 14#include <mmc.h>
15#include <part.h>
16#include <malloc.h>
17#include <linux/list.h>
9b1f942c 18#include <div64.h>
da61fa5f 19#include "mmc_private.h"
272cc70b
AF		 20
21static struct list_head mmc_devices;
22static int cur_dev_num = -1;
23
750121c3 24__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 25{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
d4e1da4e 35 if (wp < 0) {
93bfd616
PA		 36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 38 else
39 wp = 0;
40 }
d23d8d7e
NK		 41
42 return wp;
43}
44
cee9ab7c
JH		 45__weak int board_mmc_getcd(struct mmc *mmc)
46{
11fdade2
SB		 47 return -1;
48}
49
da61fa5f 50int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 51{
5db2fe3a 52 int ret;
8635ff9e 53
8635ff9e 54#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR		 55 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR		 61 switch (cmd->resp_type) {
62 case MMC_RSP_NONE:
63 printf("\t\tMMC_RSP_NONE\n");
64 break;
65 case MMC_RSP_R1:
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
67 cmd->response[0]);
68 break;
69 case MMC_RSP_R1b:
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
71 cmd->response[0]);
72 break;
73 case MMC_RSP_R2:
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
75 cmd->response[0]);
76 printf("\t\t \t\t 0x%08X \n",
77 cmd->response[1]);
78 printf("\t\t \t\t 0x%08X \n",
79 cmd->response[2]);
80 printf("\t\t \t\t 0x%08X \n",
81 cmd->response[3]);
82 printf("\n");
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
85 int j;
86 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 87 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR		 88 ptr += 3;
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
91 printf("\n");
92 }
93 break;
94 case MMC_RSP_R3:
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
96 cmd->response[0]);
97 break;
98 default:
99 printf("\t\tERROR MMC rsp not supported\n");
100 break;
101 }
5db2fe3a 102#else
93bfd616 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 104#endif
8635ff9e 105 return ret;
272cc70b
AF		 106}
107
da61fa5f 108int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 109{
110 struct mmc_cmd cmd;
d617c426 111 int err, retries = 5;
5d4fc8d9
RR		 112#ifdef CONFIG_MMC_TRACE
113 int status;
114#endif
115
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 120
1677eef4 121 while (1) {
5d4fc8d9 122 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 123 if (!err) {
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
126 MMC_STATE_PRG)
127 break;
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 130 printf("Status Error: 0x%08X\n",
131 cmd.response[0]);
56196826 132#endif
d617c426
JK		 133 return COMM_ERR;
134 }
135 } else if (--retries < 0)
5d4fc8d9 136 return err;
5d4fc8d9 137
1677eef4
AG		 138 if (timeout-- <= 0)
139 break;
5d4fc8d9 140
1677eef4
AG		 141 udelay(1000);
142 }
5d4fc8d9 143
5db2fe3a
RR		 144#ifdef CONFIG_MMC_TRACE
145 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
146 printf("CURR STATE:%d\n", status);
147#endif
5b0c942f 148 if (timeout <= 0) {
56196826 149#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 150 printf("Timeout waiting card ready\n");
56196826 151#endif
5d4fc8d9
RR		 152 return TIMEOUT;
153 }
6b2221b0
AG		 154 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
155 return SWITCH_ERR;
5d4fc8d9
RR		 156
157 return 0;
158}
159
da61fa5f 160int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 161{
162 struct mmc_cmd cmd;
163
786e8f81 164 if (mmc->ddr_mode)
d22e3d46
JC		 165 return 0;
166
272cc70b
AF		 167 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
168 cmd.resp_type = MMC_RSP_R1;
169 cmd.cmdarg = len;
272cc70b
AF		 170
171 return mmc_send_cmd(mmc, &cmd, NULL);
172}
173
174struct mmc *find_mmc_device(int dev_num)
175{
176 struct mmc *m;
177 struct list_head *entry;
178
179 list_for_each(entry, &mmc_devices) {
180 m = list_entry(entry, struct mmc, link);
181
182 if (m->block_dev.dev == dev_num)
183 return m;
184 }
185
56196826 186#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 187 printf("MMC Device %d not found\n", dev_num);
56196826 188#endif
272cc70b
AF		 189
190 return NULL;
191}
192
ff8fef56 193static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 194 lbaint_t blkcnt)
272cc70b
AF		 195{
196 struct mmc_cmd cmd;
197 struct mmc_data data;
198
4a1a06bc
AS		 199 if (blkcnt > 1)
200 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
201 else
202 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 203
204 if (mmc->high_capacity)
4a1a06bc 205 cmd.cmdarg = start;
272cc70b 206 else
4a1a06bc 207 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 208
209 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 210
211 data.dest = dst;
4a1a06bc 212 data.blocks = blkcnt;
272cc70b
AF		 213 data.blocksize = mmc->read_bl_len;
214 data.flags = MMC_DATA_READ;
215
4a1a06bc
AS		 216 if (mmc_send_cmd(mmc, &cmd, &data))
217 return 0;
272cc70b 218
4a1a06bc
AS		 219 if (blkcnt > 1) {
220 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
221 cmd.cmdarg = 0;
222 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 223 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 224#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 225 printf("mmc fail to send stop cmd\n");
56196826 226#endif
4a1a06bc
AS		 227 return 0;
228 }
272cc70b
AF		 229 }
230
4a1a06bc 231 return blkcnt;
272cc70b
AF		 232}
233
ff8fef56 234static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 235{
4a1a06bc
AS		 236 lbaint_t cur, blocks_todo = blkcnt;
237
238 if (blkcnt == 0)
239 return 0;
272cc70b 240
4a1a06bc 241 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 242 if (!mmc)
243 return 0;
244
d2bf29e3 245 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 246#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 247 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 248 start + blkcnt, mmc->block_dev.lba);
56196826 249#endif
d2bf29e3
LW		 250 return 0;
251 }
272cc70b 252
4a1a06bc 253 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 254 return 0;
272cc70b 255
4a1a06bc 256 do {
93bfd616
PA		 257 cur = (blocks_todo > mmc->cfg->b_max) ?
258 mmc->cfg->b_max : blocks_todo;
4a1a06bc
AS		 259 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
260 return 0;
261 blocks_todo -= cur;
262 start += cur;
263 dst += cur * mmc->read_bl_len;
264 } while (blocks_todo > 0);
272cc70b
AF		 265
266 return blkcnt;
267}
268
fdbb873e 269static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 270{
271 struct mmc_cmd cmd;
272 int err;
273
274 udelay(1000);
275
276 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
277 cmd.cmdarg = 0;
278 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 279
280 err = mmc_send_cmd(mmc, &cmd, NULL);
281
282 if (err)
283 return err;
284
285 udelay(2000);
286
287 return 0;
288}
289
fdbb873e 290static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF		 291{
292 int timeout = 1000;
293 int err;
294 struct mmc_cmd cmd;
295
1677eef4 296 while (1) {
272cc70b
AF		 297 cmd.cmdidx = MMC_CMD_APP_CMD;
298 cmd.resp_type = MMC_RSP_R1;
299 cmd.cmdarg = 0;
272cc70b
AF		 300
301 err = mmc_send_cmd(mmc, &cmd, NULL);
302
303 if (err)
304 return err;
305
306 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
307 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 308
309 /*
310 * Most cards do not answer if some reserved bits
311 * in the ocr are set. However, Some controller
312 * can set bit 7 (reserved for low voltages), but
313 * how to manage low voltages SD card is not yet
314 * specified.
315 */
d52ebf10 316 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 317 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 318
319 if (mmc->version == SD_VERSION_2)
320 cmd.cmdarg |= OCR_HCS;
321
322 err = mmc_send_cmd(mmc, &cmd, NULL);
323
324 if (err)
325 return err;
326
1677eef4
AG		 327 if (cmd.response[0] & OCR_BUSY)
328 break;
329
330 if (timeout-- <= 0)
331 return UNUSABLE_ERR;
272cc70b 332
1677eef4
AG		 333 udelay(1000);
334 }
272cc70b
AF		 335
336 if (mmc->version != SD_VERSION_2)
337 mmc->version = SD_VERSION_1_0;
338
d52ebf10
TC		 339 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
340 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
341 cmd.resp_type = MMC_RSP_R3;
342 cmd.cmdarg = 0;
d52ebf10
TC		 343
344 err = mmc_send_cmd(mmc, &cmd, NULL);
345
346 if (err)
347 return err;
348 }
349
998be3dd 350 mmc->ocr = cmd.response[0];
272cc70b
AF		 351
352 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
353 mmc->rca = 0;
354
355 return 0;
356}
357
5289b535 358static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 359{
5289b535 360 struct mmc_cmd cmd;
272cc70b
AF		 361 int err;
362
5289b535
AG		 363 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
364 cmd.resp_type = MMC_RSP_R3;
365 cmd.cmdarg = 0;
5a20397b
RH		 366 if (use_arg && !mmc_host_is_spi(mmc))
367 cmd.cmdarg = OCR_HCS |
93bfd616 368 (mmc->cfg->voltages &
a626c8d4
AG		 369 (mmc->ocr & OCR_VOLTAGE_MASK)) |
370 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 371
5289b535 372 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 373 if (err)
374 return err;
5289b535 375 mmc->ocr = cmd.response[0];
e9550449
CLC		 376 return 0;
377}
378
750121c3 379static int mmc_send_op_cond(struct mmc *mmc)
e9550449 380{
e9550449
CLC		 381 int err, i;
382
272cc70b
AF		 383 /* Some cards seem to need this */
384 mmc_go_idle(mmc);
385
31cacbab 386 /* Asking to the card its capabilities */
e9550449 387 for (i = 0; i < 2; i++) {
5289b535 388 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 389 if (err)
390 return err;
cd6881b5 391
e9550449 392 /* exit if not busy (flag seems to be inverted) */
a626c8d4 393 if (mmc->ocr & OCR_BUSY)
bd47c135 394 break;
e9550449 395 }
bd47c135
AG		 396 mmc->op_cond_pending = 1;
397 return 0;
e9550449 398}
cd6881b5 399
750121c3 400static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 401{
402 struct mmc_cmd cmd;
403 int timeout = 1000;
404 uint start;
405 int err;
cd6881b5 406
e9550449 407 mmc->op_cond_pending = 0;
cc17c01f
AG		 408 if (!(mmc->ocr & OCR_BUSY)) {
409 start = get_timer(0);
1677eef4 410 while (1) {
cc17c01f
AG		 411 err = mmc_send_op_cond_iter(mmc, 1);
412 if (err)
413 return err;
1677eef4
AG		 414 if (mmc->ocr & OCR_BUSY)
415 break;
cc17c01f
AG		 416 if (get_timer(start) > timeout)
417 return UNUSABLE_ERR;
418 udelay(100);
1677eef4 419 }
cc17c01f 420 }
272cc70b 421
d52ebf10
TC		 422 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
423 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
424 cmd.resp_type = MMC_RSP_R3;
425 cmd.cmdarg = 0;
d52ebf10
TC		 426
427 err = mmc_send_cmd(mmc, &cmd, NULL);
428
429 if (err)
430 return err;
a626c8d4
AG		 431
432 mmc->ocr = cmd.response[0];
d52ebf10
TC		 433 }
434
272cc70b 435 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 436
437 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 438 mmc->rca = 1;
272cc70b
AF		 439
440 return 0;
441}
442
443
fdbb873e 444static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 445{
446 struct mmc_cmd cmd;
447 struct mmc_data data;
448 int err;
449
450 /* Get the Card Status Register */
451 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
452 cmd.resp_type = MMC_RSP_R1;
453 cmd.cmdarg = 0;
272cc70b 454
cdfd1ac6 455 data.dest = (char *)ext_csd;
272cc70b 456 data.blocks = 1;
8bfa195e 457 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 458 data.flags = MMC_DATA_READ;
459
460 err = mmc_send_cmd(mmc, &cmd, &data);
461
462 return err;
463}
464
465
fdbb873e 466static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 467{
468 struct mmc_cmd cmd;
5d4fc8d9
RR		 469 int timeout = 1000;
470 int ret;
272cc70b
AF		 471
472 cmd.cmdidx = MMC_CMD_SWITCH;
473 cmd.resp_type = MMC_RSP_R1b;
474 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 475 (index << 16) |
476 (value << 8);
272cc70b 477
5d4fc8d9
RR		 478 ret = mmc_send_cmd(mmc, &cmd, NULL);
479
480 /* Waiting for the ready status */
93ad0d18
JK		 481 if (!ret)
482 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR		 483
484 return ret;
485
272cc70b
AF		 486}
487
fdbb873e 488static int mmc_change_freq(struct mmc *mmc)
272cc70b 489{
8bfa195e 490 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF		 491 char cardtype;
492 int err;
493
fc5b32fb 494 mmc->card_caps = 0;
272cc70b 495
d52ebf10
TC		 496 if (mmc_host_is_spi(mmc))
497 return 0;
498
272cc70b
AF		 499 /* Only version 4 supports high-speed */
500 if (mmc->version < MMC_VERSION_4)
501 return 0;
502
fc5b32fb
AG		 503 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
504
272cc70b
AF		 505 err = mmc_send_ext_csd(mmc, ext_csd);
506
507 if (err)
508 return err;
509
0560db18 510 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF		 511
512 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
513
514 if (err)
6b2221b0 515 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF		 516
517 /* Now check to see that it worked */
518 err = mmc_send_ext_csd(mmc, ext_csd);
519
520 if (err)
521 return err;
522
523 /* No high-speed support */
0560db18 524 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF		 525 return 0;
526
527 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 528 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 529 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 530 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 531 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 532 } else {
272cc70b 533 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 534 }
272cc70b
AF		 535
536 return 0;
537}
538
f866a46d
SW		 539static int mmc_set_capacity(struct mmc *mmc, int part_num)
540{
541 switch (part_num) {
542 case 0:
543 mmc->capacity = mmc->capacity_user;
544 break;
545 case 1:
546 case 2:
547 mmc->capacity = mmc->capacity_boot;
548 break;
549 case 3:
550 mmc->capacity = mmc->capacity_rpmb;
551 break;
552 case 4:
553 case 5:
554 case 6:
555 case 7:
556 mmc->capacity = mmc->capacity_gp[part_num - 4];
557 break;
558 default:
559 return -1;
560 }
561
562 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
563
564 return 0;
565}
566
d2356284
SW		 567int mmc_select_hwpart(int dev_num, int hwpart)
568{
569 struct mmc *mmc = find_mmc_device(dev_num);
570 int ret;
571
572 if (!mmc)
d4622df3 573 return -ENODEV;
d2356284
SW		 574
575 if (mmc->part_num == hwpart)
576 return 0;
577
578 if (mmc->part_config == MMCPART_NOAVAILABLE) {
579 printf("Card doesn't support part_switch\n");
d4622df3 580 return -EMEDIUMTYPE;
d2356284
SW		 581 }
582
583 ret = mmc_switch_part(dev_num, hwpart);
584 if (ret)
d4622df3 585 return ret;
d2356284
SW		 586
587 mmc->part_num = hwpart;
588
589 return 0;
590}
591
592
bc897b1d
LW		 593int mmc_switch_part(int dev_num, unsigned int part_num)
594{
595 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 596 int ret;
bc897b1d
LW		 597
598 if (!mmc)
599 return -1;
600
f866a46d
SW		 601 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
602 (mmc->part_config & ~PART_ACCESS_MASK)
603 | (part_num & PART_ACCESS_MASK));
f866a46d 604
6dc93e70
PB		 605 /*
606 * Set the capacity if the switch succeeded or was intended
607 * to return to representing the raw device.
608 */
609 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
610 ret = mmc_set_capacity(mmc, part_num);
611
612 return ret;
bc897b1d
LW		 613}
614
ac9da0e0
DSC		 615int mmc_hwpart_config(struct mmc *mmc,
616 const struct mmc_hwpart_conf *conf,
617 enum mmc_hwpart_conf_mode mode)
618{
619 u8 part_attrs = 0;
620 u32 enh_size_mult;
621 u32 enh_start_addr;
622 u32 gp_size_mult[4];
623 u32 max_enh_size_mult;
624 u32 tot_enh_size_mult = 0;
8dda5b0e 625 u8 wr_rel_set;
ac9da0e0
DSC		 626 int i, pidx, err;
627 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
628
629 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
630 return -EINVAL;
631
632 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
633 printf("eMMC >= 4.4 required for enhanced user data area\n");
634 return -EMEDIUMTYPE;
635 }
636
637 if (!(mmc->part_support & PART_SUPPORT)) {
638 printf("Card does not support partitioning\n");
639 return -EMEDIUMTYPE;
640 }
641
642 if (!mmc->hc_wp_grp_size) {
643 printf("Card does not define HC WP group size\n");
644 return -EMEDIUMTYPE;
645 }
646
647 /* check partition alignment and total enhanced size */
648 if (conf->user.enh_size) {
649 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
650 conf->user.enh_start % mmc->hc_wp_grp_size) {
651 printf("User data enhanced area not HC WP group "
652 "size aligned\n");
653 return -EINVAL;
654 }
655 part_attrs |= EXT_CSD_ENH_USR;
656 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
657 if (mmc->high_capacity) {
658 enh_start_addr = conf->user.enh_start;
659 } else {
660 enh_start_addr = (conf->user.enh_start << 9);
661 }
662 } else {
663 enh_size_mult = 0;
664 enh_start_addr = 0;
665 }
666 tot_enh_size_mult += enh_size_mult;
667
668 for (pidx = 0; pidx < 4; pidx++) {
669 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
670 printf("GP%i partition not HC WP group size "
671 "aligned\n", pidx+1);
672 return -EINVAL;
673 }
674 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
675 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
676 part_attrs |= EXT_CSD_ENH_GP(pidx);
677 tot_enh_size_mult += gp_size_mult[pidx];
678 }
679 }
680
681 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
682 printf("Card does not support enhanced attribute\n");
683 return -EMEDIUMTYPE;
684 }
685
686 err = mmc_send_ext_csd(mmc, ext_csd);
687 if (err)
688 return err;
689
690 max_enh_size_mult =
691 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
692 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
693 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
694 if (tot_enh_size_mult > max_enh_size_mult) {
695 printf("Total enhanced size exceeds maximum (%u > %u)\n",
696 tot_enh_size_mult, max_enh_size_mult);
697 return -EMEDIUMTYPE;
698 }
699
8dda5b0e
DSC		 700 /* The default value of EXT_CSD_WR_REL_SET is device
701 * dependent, the values can only be changed if the
702 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
703 * changed only once and before partitioning is completed. */
704 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
705 if (conf->user.wr_rel_change) {
706 if (conf->user.wr_rel_set)
707 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
708 else
709 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
710 }
711 for (pidx = 0; pidx < 4; pidx++) {
712 if (conf->gp_part[pidx].wr_rel_change) {
713 if (conf->gp_part[pidx].wr_rel_set)
714 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
715 else
716 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
717 }
718 }
719
720 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
721 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
722 puts("Card does not support host controlled partition write "
723 "reliability settings\n");
724 return -EMEDIUMTYPE;
725 }
726
ac9da0e0
DSC		 727 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
728 EXT_CSD_PARTITION_SETTING_COMPLETED) {
729 printf("Card already partitioned\n");
730 return -EPERM;
731 }
732
733 if (mode == MMC_HWPART_CONF_CHECK)
734 return 0;
735
736 /* Partitioning requires high-capacity size definitions */
737 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
738 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
739 EXT_CSD_ERASE_GROUP_DEF, 1);
740
741 if (err)
742 return err;
743
744 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
745
746 /* update erase group size to be high-capacity */
747 mmc->erase_grp_size =
748 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
749
750 }
751
752 /* all OK, write the configuration */
753 for (i = 0; i < 4; i++) {
754 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
755 EXT_CSD_ENH_START_ADDR+i,
756 (enh_start_addr >> (i*8)) & 0xFF);
757 if (err)
758 return err;
759 }
760 for (i = 0; i < 3; i++) {
761 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
762 EXT_CSD_ENH_SIZE_MULT+i,
763 (enh_size_mult >> (i*8)) & 0xFF);
764 if (err)
765 return err;
766 }
767 for (pidx = 0; pidx < 4; pidx++) {
768 for (i = 0; i < 3; i++) {
769 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
770 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
771 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
772 if (err)
773 return err;
774 }
775 }
776 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
777 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
778 if (err)
779 return err;
780
781 if (mode == MMC_HWPART_CONF_SET)
782 return 0;
783
8dda5b0e
DSC		 784 /* The WR_REL_SET is a write-once register but shall be
785 * written before setting PART_SETTING_COMPLETED. As it is
786 * write-once we can only write it when completing the
787 * partitioning. */
788 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
789 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
790 EXT_CSD_WR_REL_SET, wr_rel_set);
791 if (err)
792 return err;
793 }
794
ac9da0e0
DSC		 795 /* Setting PART_SETTING_COMPLETED confirms the partition
796 * configuration but it only becomes effective after power
797 * cycle, so we do not adjust the partition related settings
798 * in the mmc struct. */
799
800 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
801 EXT_CSD_PARTITION_SETTING,
802 EXT_CSD_PARTITION_SETTING_COMPLETED);
803 if (err)
804 return err;
805
806 return 0;
807}
808
48972d90
TR		 809int mmc_getcd(struct mmc *mmc)
810{
811 int cd;
812
813 cd = board_mmc_getcd(mmc);
814
d4e1da4e 815 if (cd < 0) {
93bfd616
PA		 816 if (mmc->cfg->ops->getcd)
817 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 818 else
819 cd = 1;
820 }
48972d90
TR		 821
822 return cd;
823}
824
fdbb873e 825static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 826{
827 struct mmc_cmd cmd;
828 struct mmc_data data;
829
830 /* Switch the frequency */
831 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
832 cmd.resp_type = MMC_RSP_R1;
833 cmd.cmdarg = (mode << 31) | 0xffffff;
834 cmd.cmdarg &= ~(0xf << (group * 4));
835 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 836
837 data.dest = (char *)resp;
838 data.blocksize = 64;
839 data.blocks = 1;
840 data.flags = MMC_DATA_READ;
841
842 return mmc_send_cmd(mmc, &cmd, &data);
843}
844
845
fdbb873e 846static int sd_change_freq(struct mmc *mmc)
272cc70b
AF		 847{
848 int err;
849 struct mmc_cmd cmd;
f781dd38
A		 850 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
851 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF		 852 struct mmc_data data;
853 int timeout;
854
855 mmc->card_caps = 0;
856
d52ebf10
TC		 857 if (mmc_host_is_spi(mmc))
858 return 0;
859
272cc70b
AF		 860 /* Read the SCR to find out if this card supports higher speeds */
861 cmd.cmdidx = MMC_CMD_APP_CMD;
862 cmd.resp_type = MMC_RSP_R1;
863 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 864
865 err = mmc_send_cmd(mmc, &cmd, NULL);
866
867 if (err)
868 return err;
869
870 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
871 cmd.resp_type = MMC_RSP_R1;
872 cmd.cmdarg = 0;
272cc70b
AF		 873
874 timeout = 3;
875
876retry_scr:
f781dd38 877 data.dest = (char *)scr;
272cc70b
AF		 878 data.blocksize = 8;
879 data.blocks = 1;
880 data.flags = MMC_DATA_READ;
881
882 err = mmc_send_cmd(mmc, &cmd, &data);
883
884 if (err) {
885 if (timeout--)
886 goto retry_scr;
887
888 return err;
889 }
890
4e3d89ba
YK		 891 mmc->scr[0] = __be32_to_cpu(scr[0]);
892 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 893
894 switch ((mmc->scr[0] >> 24) & 0xf) {
895 case 0:
896 mmc->version = SD_VERSION_1_0;
897 break;
898 case 1:
899 mmc->version = SD_VERSION_1_10;
900 break;
901 case 2:
902 mmc->version = SD_VERSION_2;
1741c64d
JC		 903 if ((mmc->scr[0] >> 15) & 0x1)
904 mmc->version = SD_VERSION_3;
272cc70b
AF		 905 break;
906 default:
907 mmc->version = SD_VERSION_1_0;
908 break;
909 }
910
b44c7083
AS		 911 if (mmc->scr[0] & SD_DATA_4BIT)
912 mmc->card_caps |= MMC_MODE_4BIT;
913
272cc70b
AF		 914 /* Version 1.0 doesn't support switching */
915 if (mmc->version == SD_VERSION_1_0)
916 return 0;
917
918 timeout = 4;
919 while (timeout--) {
920 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 921 (u8 *)switch_status);
272cc70b
AF		 922
923 if (err)
924 return err;
925
926 /* The high-speed function is busy. Try again */
4e3d89ba 927 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 928 break;
929 }
930
272cc70b 931 /* If high-speed isn't supported, we return */
4e3d89ba 932 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF		 933 return 0;
934
2c3fbf4c
ML		 935 /*
936 * If the host doesn't support SD_HIGHSPEED, do not switch card to
937 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
938 * This can avoid furthur problem when the card runs in different
939 * mode between the host.
940 */
93bfd616
PA		 941 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
942 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML		 943 return 0;
944
f781dd38 945 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF		 946
947 if (err)
948 return err;
949
4e3d89ba 950 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF		 951 mmc->card_caps |= MMC_MODE_HS;
952
953 return 0;
954}
955
956/* frequency bases */
957/* divided by 10 to be nice to platforms without floating point */
5f837c2c 958static const int fbase[] = {
272cc70b
AF		 959 10000,
960 100000,
961 1000000,
962 10000000,
963};
964
965/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
966 * to platforms without floating point.
967 */
5f837c2c 968static const int multipliers[] = {
272cc70b
AF		 969 0, /* reserved */
970 10,
971 12,
972 13,
973 15,
974 20,
975 25,
976 30,
977 35,
978 40,
979 45,
980 50,
981 55,
982 60,
983 70,
984 80,
985};
986
fdbb873e 987static void mmc_set_ios(struct mmc *mmc)
272cc70b 988{
93bfd616
PA		 989 if (mmc->cfg->ops->set_ios)
990 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF		 991}
992
993void mmc_set_clock(struct mmc *mmc, uint clock)
994{
93bfd616
PA		 995 if (clock > mmc->cfg->f_max)
996 clock = mmc->cfg->f_max;
272cc70b 997
93bfd616
PA		 998 if (clock < mmc->cfg->f_min)
999 clock = mmc->cfg->f_min;
272cc70b
AF		 1000
1001 mmc->clock = clock;
1002
1003 mmc_set_ios(mmc);
1004}
1005
fdbb873e 1006static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1007{
1008 mmc->bus_width = width;
1009
1010 mmc_set_ios(mmc);
1011}
1012
fdbb873e 1013static int mmc_startup(struct mmc *mmc)
272cc70b 1014{
f866a46d 1015 int err, i;
272cc70b 1016 uint mult, freq;
639b7827 1017 u64 cmult, csize, capacity;
272cc70b 1018 struct mmc_cmd cmd;
8bfa195e
SG		 1019 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1020 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 1021 int timeout = 1000;
0c453bb7 1022 bool has_parts = false;
8a0cf490 1023 bool part_completed;
272cc70b 1024
d52ebf10
TC		 1025#ifdef CONFIG_MMC_SPI_CRC_ON
1026 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1027 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1028 cmd.resp_type = MMC_RSP_R1;
1029 cmd.cmdarg = 1;
d52ebf10
TC		 1030 err = mmc_send_cmd(mmc, &cmd, NULL);
1031
1032 if (err)
1033 return err;
1034 }
1035#endif
1036
272cc70b 1037 /* Put the Card in Identify Mode */
d52ebf10
TC		 1038 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1039 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1040 cmd.resp_type = MMC_RSP_R2;
1041 cmd.cmdarg = 0;
272cc70b
AF		 1042
1043 err = mmc_send_cmd(mmc, &cmd, NULL);
1044
1045 if (err)
1046 return err;
1047
1048 memcpy(mmc->cid, cmd.response, 16);
1049
1050 /*
1051 * For MMC cards, set the Relative Address.
1052 * For SD cards, get the Relatvie Address.
1053 * This also puts the cards into Standby State
1054 */
d52ebf10
TC		 1055 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1056 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1057 cmd.cmdarg = mmc->rca << 16;
1058 cmd.resp_type = MMC_RSP_R6;
272cc70b 1059
d52ebf10 1060 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1061
d52ebf10
TC		 1062 if (err)
1063 return err;
272cc70b 1064
d52ebf10
TC		 1065 if (IS_SD(mmc))
1066 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1067 }
272cc70b
AF		 1068
1069 /* Get the Card-Specific Data */
1070 cmd.cmdidx = MMC_CMD_SEND_CSD;
1071 cmd.resp_type = MMC_RSP_R2;
1072 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1073
1074 err = mmc_send_cmd(mmc, &cmd, NULL);
1075
5d4fc8d9
RR		 1076 /* Waiting for the ready status */
1077 mmc_send_status(mmc, timeout);
1078
272cc70b
AF		 1079 if (err)
1080 return err;
1081
998be3dd
RV		 1082 mmc->csd[0] = cmd.response[0];
1083 mmc->csd[1] = cmd.response[1];
1084 mmc->csd[2] = cmd.response[2];
1085 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1086
1087 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1088 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1089
1090 switch (version) {
1091 case 0:
1092 mmc->version = MMC_VERSION_1_2;
1093 break;
1094 case 1:
1095 mmc->version = MMC_VERSION_1_4;
1096 break;
1097 case 2:
1098 mmc->version = MMC_VERSION_2_2;
1099 break;
1100 case 3:
1101 mmc->version = MMC_VERSION_3;
1102 break;
1103 case 4:
1104 mmc->version = MMC_VERSION_4;
1105 break;
1106 default:
1107 mmc->version = MMC_VERSION_1_2;
1108 break;
1109 }
1110 }
1111
1112 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1113 freq = fbase[(cmd.response[0] & 0x7)];
1114 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF		 1115
1116 mmc->tran_speed = freq * mult;
1117
ab71188c 1118 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1119 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 1120
1121 if (IS_SD(mmc))
1122 mmc->write_bl_len = mmc->read_bl_len;
1123 else
998be3dd 1124 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 1125
1126 if (mmc->high_capacity) {
1127 csize = (mmc->csd[1] & 0x3f) << 16
1128 | (mmc->csd[2] & 0xffff0000) >> 16;
1129 cmult = 8;
1130 } else {
1131 csize = (mmc->csd[1] & 0x3ff) << 2
1132 | (mmc->csd[2] & 0xc0000000) >> 30;
1133 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1134 }
1135
f866a46d
SW		 1136 mmc->capacity_user = (csize + 1) << (cmult + 2);
1137 mmc->capacity_user *= mmc->read_bl_len;
1138 mmc->capacity_boot = 0;
1139 mmc->capacity_rpmb = 0;
1140 for (i = 0; i < 4; i++)
1141 mmc->capacity_gp[i] = 0;
272cc70b 1142
8bfa195e
SG		 1143 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1144 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1145
8bfa195e
SG		 1146 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1147 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1148
ab71188c
MN		 1149 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1150 cmd.cmdidx = MMC_CMD_SET_DSR;
1151 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1152 cmd.resp_type = MMC_RSP_NONE;
1153 if (mmc_send_cmd(mmc, &cmd, NULL))
1154 printf("MMC: SET_DSR failed\n");
1155 }
1156
272cc70b 1157 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 1158 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1159 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1160 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1161 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1162 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1163
d52ebf10
TC		 1164 if (err)
1165 return err;
1166 }
272cc70b 1167
e6f99a56
LW		 1168 /*
1169 * For SD, its erase group is always one sector
1170 */
1171 mmc->erase_grp_size = 1;
bc897b1d 1172 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG		 1173 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1174 /* check ext_csd version and capacity */
1175 err = mmc_send_ext_csd(mmc, ext_csd);
9cf199eb
DSC		 1176 if (err)
1177 return err;
1178 if (ext_csd[EXT_CSD_REV] >= 2) {
639b7827
YS		 1179 /*
1180 * According to the JEDEC Standard, the value of
1181 * ext_csd's capacity is valid if the value is more
1182 * than 2GB
1183 */
0560db18
LW		 1184 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1185 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1186 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1187 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 1188 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 1189 if ((capacity >> 20) > 2 * 1024)
f866a46d 1190 mmc->capacity_user = capacity;
d23e2c09 1191 }
bc897b1d 1192
64f4a619
JC		 1193 switch (ext_csd[EXT_CSD_REV]) {
1194 case 1:
1195 mmc->version = MMC_VERSION_4_1;
1196 break;
1197 case 2:
1198 mmc->version = MMC_VERSION_4_2;
1199 break;
1200 case 3:
1201 mmc->version = MMC_VERSION_4_3;
1202 break;
1203 case 5:
1204 mmc->version = MMC_VERSION_4_41;
1205 break;
1206 case 6:
1207 mmc->version = MMC_VERSION_4_5;
1208 break;
edab723b
MN		 1209 case 7:
1210 mmc->version = MMC_VERSION_5_0;
1211 break;
64f4a619
JC		 1212 }
1213
8a0cf490
DSC		 1214 /* The partition data may be non-zero but it is only
1215 * effective if PARTITION_SETTING_COMPLETED is set in
1216 * EXT_CSD, so ignore any data if this bit is not set,
1217 * except for enabling the high-capacity group size
1218 * definition (see below). */
1219 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1220 EXT_CSD_PARTITION_SETTING_COMPLETED);
1221
0c453bb7
DSC		 1222 /* store the partition info of emmc */
1223 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1224 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1225 ext_csd[EXT_CSD_BOOT_MULT])
1226 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
8a0cf490
DSC		 1227 if (part_completed &&
1228 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
0c453bb7
DSC		 1229 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1230
1231 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1232
1233 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1234
1235 for (i = 0; i < 4; i++) {
1236 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
8a0cf490 1237 uint mult = (ext_csd[idx + 2] << 16) +
0c453bb7 1238 (ext_csd[idx + 1] << 8) + ext_csd[idx];
8a0cf490
DSC		 1239 if (mult)
1240 has_parts = true;
1241 if (!part_completed)
1242 continue;
1243 mmc->capacity_gp[i] = mult;
0c453bb7
DSC		 1244 mmc->capacity_gp[i] *=
1245 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1246 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
f8e89d67 1247 mmc->capacity_gp[i] <<= 19;
0c453bb7
DSC		 1248 }
1249
8a0cf490
DSC		 1250 if (part_completed) {
1251 mmc->enh_user_size =
1252 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1253 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1254 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1255 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1256 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1257 mmc->enh_user_size <<= 19;
1258 mmc->enh_user_start =
1259 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1260 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1261 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1262 ext_csd[EXT_CSD_ENH_START_ADDR];
1263 if (mmc->high_capacity)
1264 mmc->enh_user_start <<= 9;
1265 }
a7f852b6 1266
e6f99a56 1267 /*
1937e5aa
OM		 1268 * Host needs to enable ERASE_GRP_DEF bit if device is
1269 * partitioned. This bit will be lost every time after a reset
1270 * or power off. This will affect erase size.
e6f99a56 1271 */
8a0cf490 1272 if (part_completed)
0c453bb7 1273 has_parts = true;
1937e5aa 1274 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC		 1275 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1276 has_parts = true;
1277 if (has_parts) {
1937e5aa
OM		 1278 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1279 EXT_CSD_ERASE_GROUP_DEF, 1);
1280
1281 if (err)
1282 return err;
021a8055
HP		 1283 else
1284 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
037dc0ab 1285 }
1937e5aa 1286
037dc0ab 1287 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1937e5aa 1288 /* Read out group size from ext_csd */
0560db18 1289 mmc->erase_grp_size =
a4ff9f83 1290 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
d7b29129
MN		 1291 /*
1292 * if high capacity and partition setting completed
1293 * SEC_COUNT is valid even if it is smaller than 2 GiB
1294 * JEDEC Standard JESD84-B45, 6.2.4
1295 */
8a0cf490 1296 if (mmc->high_capacity && part_completed) {
d7b29129
MN		 1297 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1298 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1299 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1300 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1301 capacity *= MMC_MAX_BLOCK_LEN;
1302 mmc->capacity_user = capacity;
1303 }
8bfa195e 1304 } else {
1937e5aa 1305 /* Calculate the group size from the csd value. */
e6f99a56
LW		 1306 int erase_gsz, erase_gmul;
1307 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1308 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1309 mmc->erase_grp_size = (erase_gsz + 1)
1310 * (erase_gmul + 1);
1311 }
037dc0ab
DSC		 1312
1313 mmc->hc_wp_grp_size = 1024
1314 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1315 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
9e41a00b
DSC		 1316
1317 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
d23e2c09
SG		 1318 }
1319
f866a46d
SW		 1320 err = mmc_set_capacity(mmc, mmc->part_num);
1321 if (err)
1322 return err;
1323
272cc70b
AF		 1324 if (IS_SD(mmc))
1325 err = sd_change_freq(mmc);
1326 else
1327 err = mmc_change_freq(mmc);
1328
1329 if (err)
1330 return err;
1331
1332 /* Restrict card's capabilities by what the host can do */
93bfd616 1333 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF		 1334
1335 if (IS_SD(mmc)) {
1336 if (mmc->card_caps & MMC_MODE_4BIT) {
1337 cmd.cmdidx = MMC_CMD_APP_CMD;
1338 cmd.resp_type = MMC_RSP_R1;
1339 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1340
1341 err = mmc_send_cmd(mmc, &cmd, NULL);
1342 if (err)
1343 return err;
1344
1345 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1346 cmd.resp_type = MMC_RSP_R1;
1347 cmd.cmdarg = 2;
272cc70b
AF		 1348 err = mmc_send_cmd(mmc, &cmd, NULL);
1349 if (err)
1350 return err;
1351
1352 mmc_set_bus_width(mmc, 4);
1353 }
1354
1355 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1356 mmc->tran_speed = 50000000;
272cc70b 1357 else
ad5fd922 1358 mmc->tran_speed = 25000000;
fc5b32fb
AG		 1359 } else if (mmc->version >= MMC_VERSION_4) {
1360 /* Only version 4 of MMC supports wider bus widths */
7798f6db
AF		 1361 int idx;
1362
1363 /* An array of possible bus widths in order of preference */
1364 static unsigned ext_csd_bits[] = {
d22e3d46
JC		 1365 EXT_CSD_DDR_BUS_WIDTH_8,
1366 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF		 1367 EXT_CSD_BUS_WIDTH_8,
1368 EXT_CSD_BUS_WIDTH_4,
1369 EXT_CSD_BUS_WIDTH_1,
1370 };
1371
1372 /* An array to map CSD bus widths to host cap bits */
1373 static unsigned ext_to_hostcaps[] = {
786e8f81
AG		 1374 [EXT_CSD_DDR_BUS_WIDTH_4] =
1375 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1376 [EXT_CSD_DDR_BUS_WIDTH_8] =
1377 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF		 1378 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1379 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1380 };
1381
1382 /* An array to map chosen bus width to an integer */
1383 static unsigned widths[] = {
d22e3d46 1384 8, 4, 8, 4, 1,
7798f6db
AF		 1385 };
1386
1387 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1388 unsigned int extw = ext_csd_bits[idx];
786e8f81 1389 unsigned int caps = ext_to_hostcaps[extw];
7798f6db 1390
bf477073
AG		 1391 /*
1392 * If the bus width is still not changed,
1393 * don't try to set the default again.
1394 * Otherwise, recover from switch attempts
1395 * by switching to 1-bit bus width.
1396 */
1397 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1398 mmc->bus_width == 1) {
1399 err = 0;
1400 break;
1401 }
1402
7798f6db 1403 /*
786e8f81
AG		 1404 * Check to make sure the card and controller support
1405 * these capabilities
7798f6db 1406 */
786e8f81 1407 if ((mmc->card_caps & caps) != caps)
7798f6db
AF		 1408 continue;
1409
272cc70b 1410 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1411 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF		 1412
1413 if (err)
4137894e 1414 continue;
272cc70b 1415
786e8f81 1416 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1417 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW		 1418
1419 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG		 1420
1421 if (err)
1422 continue;
1423
786a27b7 1424 /* Only compare read only fields */
786e8f81
AG		 1425 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1426 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1427 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1428 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1429 ext_csd[EXT_CSD_REV]
1430 == test_csd[EXT_CSD_REV] &&
1431 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1432 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1433 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1434 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1435 break;
786e8f81
AG		 1436 else
1437 err = SWITCH_ERR;
272cc70b
AF		 1438 }
1439
786e8f81
AG		 1440 if (err)
1441 return err;
1442
272cc70b
AF		 1443 if (mmc->card_caps & MMC_MODE_HS) {
1444 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1445 mmc->tran_speed = 52000000;
272cc70b 1446 else
ad5fd922
JC		 1447 mmc->tran_speed = 26000000;
1448 }
272cc70b
AF		 1449 }
1450
ad5fd922
JC		 1451 mmc_set_clock(mmc, mmc->tran_speed);
1452
5af8f45c
AG		 1453 /* Fix the block length for DDR mode */
1454 if (mmc->ddr_mode) {
1455 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1456 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1457 }
1458
272cc70b
AF		 1459 /* fill in device description */
1460 mmc->block_dev.lun = 0;
1461 mmc->block_dev.type = 0;
1462 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1463 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1464 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1465#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH		 1466 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1467 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1468 (mmc->cid[3] >> 16) & 0xffff);
1469 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1470 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1471 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1472 (mmc->cid[2] >> 24) & 0xff);
1473 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1474 (mmc->cid[2] >> 16) & 0xf);
56196826
PB		 1475#else
1476 mmc->block_dev.vendor[0] = 0;
1477 mmc->block_dev.product[0] = 0;
1478 mmc->block_dev.revision[0] = 0;
1479#endif
122efd43 1480#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1481 init_part(&mmc->block_dev);
122efd43 1482#endif
272cc70b
AF		 1483
1484 return 0;
1485}
1486
fdbb873e 1487static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 1488{
1489 struct mmc_cmd cmd;
1490 int err;
1491
1492 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1493 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1494 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1495 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 1496
1497 err = mmc_send_cmd(mmc, &cmd, NULL);
1498
1499 if (err)
1500 return err;
1501
998be3dd 1502 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF		 1503 return UNUSABLE_ERR;
1504 else
1505 mmc->version = SD_VERSION_2;
1506
1507 return 0;
1508}
1509
93bfd616
PA		 1510/* not used any more */
1511int __deprecated mmc_register(struct mmc *mmc)
1512{
1513#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1514 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1515#endif
1516 return -1;
1517}
1518
1519struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1520{
93bfd616
PA		 1521 struct mmc *mmc;
1522
1523 /* quick validation */
1524 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1525 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1526 return NULL;
1527
1528 mmc = calloc(1, sizeof(*mmc));
1529 if (mmc == NULL)
1530 return NULL;
1531
1532 mmc->cfg = cfg;
1533 mmc->priv = priv;
1534
1535 /* the following chunk was mmc_register() */
1536
ab71188c
MN		 1537 /* Setup dsr related values */
1538 mmc->dsr_imp = 0;
1539 mmc->dsr = 0xffffffff;
272cc70b
AF		 1540 /* Setup the universal parts of the block interface just once */
1541 mmc->block_dev.if_type = IF_TYPE_MMC;
1542 mmc->block_dev.dev = cur_dev_num++;
1543 mmc->block_dev.removable = 1;
1544 mmc->block_dev.block_read = mmc_bread;
1545 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1546 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1547
93bfd616
PA		 1548 /* setup initial part type */
1549 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1550
93bfd616 1551 INIT_LIST_HEAD(&mmc->link);
272cc70b 1552
93bfd616
PA		 1553 list_add_tail(&mmc->link, &mmc_devices);
1554
1555 return mmc;
1556}
1557
1558void mmc_destroy(struct mmc *mmc)
1559{
1560 /* only freeing memory for now */
1561 free(mmc);
272cc70b
AF		 1562}
1563
df3fc526 1564#ifdef CONFIG_PARTITIONS
272cc70b
AF		 1565block_dev_desc_t *mmc_get_dev(int dev)
1566{
1567 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1568 if (!mmc || mmc_init(mmc))
40242bc3 1569 return NULL;
272cc70b 1570
40242bc3 1571 return &mmc->block_dev;
272cc70b 1572}
df3fc526 1573#endif
272cc70b 1574
95de9ab2
PK		 1575/* board-specific MMC power initializations. */
1576__weak void board_mmc_power_init(void)
1577{
1578}
1579
e9550449 1580int mmc_start_init(struct mmc *mmc)
272cc70b 1581{
afd5932b 1582 int err;
272cc70b 1583
ab769f22 1584 /* we pretend there's no card when init is NULL */
93bfd616 1585 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1586 mmc->has_init = 0;
56196826 1587#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1588 printf("MMC: no card present\n");
56196826 1589#endif
48972d90
TR		 1590 return NO_CARD_ERR;
1591 }
1592
bc897b1d
LW		 1593 if (mmc->has_init)
1594 return 0;
1595
5a8dbdc6
YL		 1596#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1597 mmc_adapter_card_type_ident();
1598#endif
95de9ab2
PK		 1599 board_mmc_power_init();
1600
ab769f22 1601 /* made sure it's not NULL earlier */
93bfd616 1602 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 1603
1604 if (err)
1605 return err;
1606
786e8f81 1607 mmc->ddr_mode = 0;
b86b85e2
IY		 1608 mmc_set_bus_width(mmc, 1);
1609 mmc_set_clock(mmc, 1);
1610
272cc70b
AF		 1611 /* Reset the Card */
1612 err = mmc_go_idle(mmc);
1613
1614 if (err)
1615 return err;
1616
bc897b1d
LW		 1617 /* The internal partition reset to user partition(0) at every CMD0*/
1618 mmc->part_num = 0;
1619
272cc70b 1620 /* Test for SD version 2 */
afd5932b 1621 err = mmc_send_if_cond(mmc);
272cc70b 1622
272cc70b
AF		 1623 /* Now try to get the SD card's operating condition */
1624 err = sd_send_op_cond(mmc);
1625
1626 /* If the command timed out, we check for an MMC card */
1627 if (err == TIMEOUT) {
1628 err = mmc_send_op_cond(mmc);
1629
bd47c135 1630 if (err) {
56196826 1631#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1632 printf("Card did not respond to voltage select!\n");
56196826 1633#endif
272cc70b
AF		 1634 return UNUSABLE_ERR;
1635 }
1636 }
1637
bd47c135 1638 if (!err)
e9550449
CLC		 1639 mmc->init_in_progress = 1;
1640
1641 return err;
1642}
1643
1644static int mmc_complete_init(struct mmc *mmc)
1645{
1646 int err = 0;
1647
bd47c135 1648 mmc->init_in_progress = 0;
e9550449
CLC		 1649 if (mmc->op_cond_pending)
1650 err = mmc_complete_op_cond(mmc);
1651
1652 if (!err)
1653 err = mmc_startup(mmc);
bc897b1d
LW		 1654 if (err)
1655 mmc->has_init = 0;
1656 else
1657 mmc->has_init = 1;
e9550449
CLC		 1658 return err;
1659}
1660
1661int mmc_init(struct mmc *mmc)
1662{
bd47c135 1663 int err = 0;
d803fea5 1664 unsigned start;
e9550449
CLC		 1665
1666 if (mmc->has_init)
1667 return 0;
d803fea5
MZ		 1668
1669 start = get_timer(0);
1670
e9550449
CLC		 1671 if (!mmc->init_in_progress)
1672 err = mmc_start_init(mmc);
1673
bd47c135 1674 if (!err)
e9550449
CLC		 1675 err = mmc_complete_init(mmc);
1676 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1677 return err;
272cc70b
AF		 1678}
1679
ab71188c
MN		 1680int mmc_set_dsr(struct mmc *mmc, u16 val)
1681{
1682 mmc->dsr = val;
1683 return 0;
1684}
1685
cee9ab7c
JH		 1686/* CPU-specific MMC initializations */
1687__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 1688{
1689 return -1;
1690}
1691
cee9ab7c
JH		 1692/* board-specific MMC initializations. */
1693__weak int board_mmc_init(bd_t *bis)
1694{
1695 return -1;
1696}
272cc70b 1697
56196826
PB		 1698#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1699
272cc70b
AF		 1700void print_mmc_devices(char separator)
1701{
1702 struct mmc *m;
1703 struct list_head *entry;
34dd9284 1704 char *mmc_type;
272cc70b
AF		 1705
1706 list_for_each(entry, &mmc_devices) {
1707 m = list_entry(entry, struct mmc, link);
1708
34dd9284
PM		 1709 if (m->has_init)
1710 mmc_type = IS_SD(m) ? "SD" : "eMMC";
1711 else
1712 mmc_type = NULL;
1713
93bfd616 1714 printf("%s: %d", m->cfg->name, m->block_dev.dev);
34dd9284
PM		 1715 if (mmc_type)
1716 printf(" (%s)", mmc_type);
272cc70b 1717
e75eaf10
LP		 1718 if (entry->next != &mmc_devices) {
1719 printf("%c", separator);
1720 if (separator != '\n')
1721 puts (" ");
1722 }
272cc70b
AF		 1723 }
1724
1725 printf("\n");
1726}
1727
56196826
PB		 1728#else
1729void print_mmc_devices(char separator) { }
1730#endif
1731
ea6ebe21
LW		 1732int get_mmc_num(void)
1733{
1734 return cur_dev_num;
1735}
1736
e9550449
CLC		 1737void mmc_set_preinit(struct mmc *mmc, int preinit)
1738{
1739 mmc->preinit = preinit;
1740}
1741
1742static void do_preinit(void)
1743{
1744 struct mmc *m;
1745 struct list_head *entry;
1746
1747 list_for_each(entry, &mmc_devices) {
1748 m = list_entry(entry, struct mmc, link);
1749
5a8dbdc6
YL		 1750#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1751 mmc_set_preinit(m, 1);
1752#endif
e9550449
CLC		 1753 if (m->preinit)
1754 mmc_start_init(m);
1755 }
1756}
1757
1758
272cc70b
AF		 1759int mmc_initialize(bd_t *bis)
1760{
1761 INIT_LIST_HEAD (&mmc_devices);
1762 cur_dev_num = 0;
1763
e7ecf7cb 1764#ifndef CONFIG_DM_MMC
272cc70b
AF		 1765 if (board_mmc_init(bis) < 0)
1766 cpu_mmc_init(bis);
e7ecf7cb 1767#endif
272cc70b 1768
bb0dc108 1769#ifndef CONFIG_SPL_BUILD
272cc70b 1770 print_mmc_devices(',');
bb0dc108 1771#endif
272cc70b 1772
e9550449 1773 do_preinit();
272cc70b
AF		 1774 return 0;
1775}
3690d6d6
A		 1776
1777#ifdef CONFIG_SUPPORT_EMMC_BOOT
1778/*
1779 * This function changes the size of boot partition and the size of rpmb
1780 * partition present on EMMC devices.
1781 *
1782 * Input Parameters:
1783 * struct *mmc: pointer for the mmc device strcuture
1784 * bootsize: size of boot partition
1785 * rpmbsize: size of rpmb partition
1786 *
1787 * Returns 0 on success.
1788 */
1789
1790int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1791 unsigned long rpmbsize)
1792{
1793 int err;
1794 struct mmc_cmd cmd;
1795
1796 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1797 cmd.cmdidx = MMC_CMD_RES_MAN;
1798 cmd.resp_type = MMC_RSP_R1b;
1799 cmd.cmdarg = MMC_CMD62_ARG1;
1800
1801 err = mmc_send_cmd(mmc, &cmd, NULL);
1802 if (err) {
1803 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1804 return err;
1805 }
1806
1807 /* Boot partition changing mode */
1808 cmd.cmdidx = MMC_CMD_RES_MAN;
1809 cmd.resp_type = MMC_RSP_R1b;
1810 cmd.cmdarg = MMC_CMD62_ARG2;
1811
1812 err = mmc_send_cmd(mmc, &cmd, NULL);
1813 if (err) {
1814 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1815 return err;
1816 }
1817 /* boot partition size is multiple of 128KB */
1818 bootsize = (bootsize * 1024) / 128;
1819
1820 /* Arg: boot partition size */
1821 cmd.cmdidx = MMC_CMD_RES_MAN;
1822 cmd.resp_type = MMC_RSP_R1b;
1823 cmd.cmdarg = bootsize;
1824
1825 err = mmc_send_cmd(mmc, &cmd, NULL);
1826 if (err) {
1827 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1828 return err;
1829 }
1830 /* RPMB partition size is multiple of 128KB */
1831 rpmbsize = (rpmbsize * 1024) / 128;
1832 /* Arg: RPMB partition size */
1833 cmd.cmdidx = MMC_CMD_RES_MAN;
1834 cmd.resp_type = MMC_RSP_R1b;
1835 cmd.cmdarg = rpmbsize;
1836
1837 err = mmc_send_cmd(mmc, &cmd, NULL);
1838 if (err) {
1839 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1840 return err;
1841 }
1842 return 0;
1843}
1844
5a99b9de
TR		 1845/*
1846 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1847 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1848 * and BOOT_MODE.
1849 *
1850 * Returns 0 on success.
1851 */
1852int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1853{
1854 int err;
1855
1856 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1857 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1858 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1859 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1860
1861 if (err)
1862 return err;
1863 return 0;
1864}
1865
792970b0
TR		 1866/*
1867 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1868 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1869 * PARTITION_ACCESS.
1870 *
1871 * Returns 0 on success.
1872 */
1873int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1874{
1875 int err;
1876
1877 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1878 EXT_CSD_BOOT_ACK(ack) |
1879 EXT_CSD_BOOT_PART_NUM(part_num) |
1880 EXT_CSD_PARTITION_ACCESS(access));
1881
1882 if (err)
1883 return err;
1884 return 0;
1885}
33ace362
TR		 1886
1887/*
1888 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1889 * for enable. Note that this is a write-once field for non-zero values.
1890 *
1891 * Returns 0 on success.
1892 */
1893int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1894{
1895 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1896 enable);
1897}
3690d6d6 1898#endif
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