[people/ms/u-boot.git] / drivers / mmc / mxcmmc.c

/*
 *  This is a driver for the SDHC controller found in Freescale MX2/MX3
 *  SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
 *  Unlike the hardware found on MX1, this hardware just works and does
 *  not need all the quirks found in imxmmc.c, hence the seperate driver.
 *
 *  Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
 *  Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
 *
 *  derived from pxamci.c by Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>

#define DRIVER_NAME "mxc-mmc"

struct mxcmci_regs {
	u32 str_stp_clk;
	u32 status;
	u32 clk_rate;
	u32 cmd_dat_cont;
	u32 res_to;
	u32 read_to;
	u32 blk_len;
	u32 nob;
	u32 rev_no;
	u32 int_cntr;
	u32 cmd;
	u32 arg;
	u32 pad;
	u32 res_fifo;
	u32 buffer_access;
};

#define STR_STP_CLK_RESET               (1 << 3)
#define STR_STP_CLK_START_CLK           (1 << 1)
#define STR_STP_CLK_STOP_CLK            (1 << 0)

#define STATUS_CARD_INSERTION		(1 << 31)
#define STATUS_CARD_REMOVAL		(1 << 30)
#define STATUS_YBUF_EMPTY		(1 << 29)
#define STATUS_XBUF_EMPTY		(1 << 28)
#define STATUS_YBUF_FULL		(1 << 27)
#define STATUS_XBUF_FULL		(1 << 26)
#define STATUS_BUF_UND_RUN		(1 << 25)
#define STATUS_BUF_OVFL			(1 << 24)
#define STATUS_SDIO_INT_ACTIVE		(1 << 14)
#define STATUS_END_CMD_RESP		(1 << 13)
#define STATUS_WRITE_OP_DONE		(1 << 12)
#define STATUS_DATA_TRANS_DONE		(1 << 11)
#define STATUS_READ_OP_DONE		(1 << 11)
#define STATUS_WR_CRC_ERROR_CODE_MASK	(3 << 10)
#define STATUS_CARD_BUS_CLK_RUN		(1 << 8)
#define STATUS_BUF_READ_RDY		(1 << 7)
#define STATUS_BUF_WRITE_RDY		(1 << 6)
#define STATUS_RESP_CRC_ERR		(1 << 5)
#define STATUS_CRC_READ_ERR		(1 << 3)
#define STATUS_CRC_WRITE_ERR		(1 << 2)
#define STATUS_TIME_OUT_RESP		(1 << 1)
#define STATUS_TIME_OUT_READ		(1 << 0)
#define STATUS_ERR_MASK			0x2f

#define CMD_DAT_CONT_CMD_RESP_LONG_OFF	(1 << 12)
#define CMD_DAT_CONT_STOP_READWAIT	(1 << 11)
#define CMD_DAT_CONT_START_READWAIT	(1 << 10)
#define CMD_DAT_CONT_BUS_WIDTH_4	(2 << 8)
#define CMD_DAT_CONT_INIT		(1 << 7)
#define CMD_DAT_CONT_WRITE		(1 << 4)
#define CMD_DAT_CONT_DATA_ENABLE	(1 << 3)
#define CMD_DAT_CONT_RESPONSE_48BIT_CRC	(1 << 0)
#define CMD_DAT_CONT_RESPONSE_136BIT	(2 << 0)
#define CMD_DAT_CONT_RESPONSE_48BIT	(3 << 0)

#define INT_SDIO_INT_WKP_EN		(1 << 18)
#define INT_CARD_INSERTION_WKP_EN	(1 << 17)
#define INT_CARD_REMOVAL_WKP_EN		(1 << 16)
#define INT_CARD_INSERTION_EN		(1 << 15)
#define INT_CARD_REMOVAL_EN		(1 << 14)
#define INT_SDIO_IRQ_EN			(1 << 13)
#define INT_DAT0_EN			(1 << 12)
#define INT_BUF_READ_EN			(1 << 4)
#define INT_BUF_WRITE_EN		(1 << 3)
#define INT_END_CMD_RES_EN		(1 << 2)
#define INT_WRITE_OP_DONE_EN		(1 << 1)
#define INT_READ_OP_EN			(1 << 0)

struct mxcmci_host {
	struct mmc		*mmc;
	struct mxcmci_regs	*base;
	int			irq;
	int			detect_irq;
	int			dma;
	int			do_dma;
	unsigned int		power_mode;

	struct mmc_cmd		*cmd;
	struct mmc_data		*data;

	unsigned int		dma_nents;
	unsigned int		datasize;
	unsigned int		dma_dir;

	u16			rev_no;
	unsigned int		cmdat;

	int			clock;
};

static struct mxcmci_host mxcmci_host;

/* maintainer note: do we really want to have a global host pointer? */
static struct mxcmci_host *host = &mxcmci_host;

static inline int mxcmci_use_dma(struct mxcmci_host *host)
{
	return host->do_dma;
}

static void mxcmci_softreset(struct mxcmci_host *host)
{
	int i;

	/* reset sequence */
	writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
	writel(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
			&host->base->str_stp_clk);

	for (i = 0; i < 8; i++)
		writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);

	writel(0xff, &host->base->res_to);
}

static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
{
	unsigned int nob = data->blocks;
	unsigned int blksz = data->blocksize;
	unsigned int datasize = nob * blksz;

	host->data = data;

	writel(nob, &host->base->nob);
	writel(blksz, &host->base->blk_len);
	host->datasize = datasize;
}

static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd,
		unsigned int cmdat)
{
	if (host->cmd != NULL)
		printf("mxcmci: error!\n");
	host->cmd = cmd;

	switch (cmd->resp_type) {
	case MMC_RSP_R1: /* short CRC, OPCODE */
	case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
		cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
		break;
	case MMC_RSP_R2: /* long 136 bit + CRC */
		cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
		break;
	case MMC_RSP_R3: /* short */
		cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
		break;
	case MMC_RSP_NONE:
		break;
	default:
		printf("mxcmci: unhandled response type 0x%x\n",
				cmd->resp_type);
		return -EINVAL;
	}

	writel(cmd->cmdidx, &host->base->cmd);
	writel(cmd->cmdarg, &host->base->arg);
	writel(cmdat, &host->base->cmd_dat_cont);

	return 0;
}

static void mxcmci_finish_request(struct mxcmci_host *host,
		struct mmc_cmd *cmd, struct mmc_data *data)
{
	host->cmd = NULL;
	host->data = NULL;
}

static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
{
	int data_error = 0;

	if (stat & STATUS_ERR_MASK) {
		printf("request failed. status: 0x%08x\n",
				stat);
		if (stat & STATUS_CRC_READ_ERR) {
			data_error = -EILSEQ;
		} else if (stat & STATUS_CRC_WRITE_ERR) {
			u32 err_code = (stat >> 9) & 0x3;
			if (err_code == 2) /* No CRC response */
				data_error = -ETIMEDOUT;
			else
				data_error = -EILSEQ;
		} else if (stat & STATUS_TIME_OUT_READ) {
			data_error = -ETIMEDOUT;
		} else {
			data_error = -EIO;
		}
	}

	host->data = NULL;

	return data_error;
}

static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
{
	struct mmc_cmd *cmd = host->cmd;
	int i;
	u32 a, b, c;
	u32 *resp = (u32 *)cmd->response;

	if (!cmd)
		return 0;

	if (stat & STATUS_TIME_OUT_RESP) {
		printf("CMD TIMEOUT\n");
		return -ETIMEDOUT;
	} else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
		printf("cmd crc error\n");
		return -EILSEQ;
	}

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136) {
			for (i = 0; i < 4; i++) {
				a = readl(&host->base->res_fifo) & 0xFFFF;
				b = readl(&host->base->res_fifo) & 0xFFFF;
				resp[i] = a << 16 | b;
			}
		} else {
			a = readl(&host->base->res_fifo) & 0xFFFF;
			b = readl(&host->base->res_fifo) & 0xFFFF;
			c = readl(&host->base->res_fifo) & 0xFFFF;
			resp[0] = a << 24 | b << 8 | c >> 8;
		}
	}
	return 0;
}

static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
{
	u32 stat;
	unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;

	do {
		stat = readl(&host->base->status);
		if (stat & STATUS_ERR_MASK)
			return stat;
		if (timeout < get_ticks())
			return STATUS_TIME_OUT_READ;
		if (stat & mask)
			return 0;
	} while (1);
}

static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
{
	unsigned int stat;
	u32 *buf = _buf;

	while (bytes > 3) {
		stat = mxcmci_poll_status(host,
				STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
		if (stat)
			return stat;
		*buf++ = readl(&host->base->buffer_access);
		bytes -= 4;
	}

	if (bytes) {
		u8 *b = (u8 *)buf;
		u32 tmp;

		stat = mxcmci_poll_status(host,
				STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
		if (stat)
			return stat;
		tmp = readl(&host->base->buffer_access);
		memcpy(b, &tmp, bytes);
	}

	return 0;
}

static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes)
{
	unsigned int stat;
	const u32 *buf = _buf;

	while (bytes > 3) {
		stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
		if (stat)
			return stat;
		writel(*buf++, &host->base->buffer_access);
		bytes -= 4;
	}

	if (bytes) {
		const u8 *b = (u8 *)buf;
		u32 tmp;

		stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
		if (stat)
			return stat;

		memcpy(&tmp, b, bytes);
		writel(tmp, &host->base->buffer_access);
	}

	stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
	if (stat)
		return stat;

	return 0;
}

static int mxcmci_transfer_data(struct mxcmci_host *host)
{
	struct mmc_data *data = host->data;
	int stat;
	unsigned long length;

	length = data->blocks * data->blocksize;
	host->datasize = 0;

	if (data->flags & MMC_DATA_READ) {
		stat = mxcmci_pull(host, data->dest, length);
		if (stat)
			return stat;
		host->datasize += length;
	} else {
		stat = mxcmci_push(host, (const void *)(data->src), length);
		if (stat)
			return stat;
		host->datasize += length;
		stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
		if (stat)
			return stat;
	}
	return 0;
}

static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
{
	int datastat;
	int ret;

	ret = mxcmci_read_response(host, stat);

	if (ret) {
		mxcmci_finish_request(host, host->cmd, host->data);
		return ret;
	}

	if (!host->data) {
		mxcmci_finish_request(host, host->cmd, host->data);
		return 0;
	}

	datastat = mxcmci_transfer_data(host);
	ret = mxcmci_finish_data(host, datastat);
	mxcmci_finish_request(host, host->cmd, host->data);
	return ret;
}

static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
	struct mxcmci_host *host = mmc->priv;
	unsigned int cmdat = host->cmdat;
	u32 stat;
	int ret;

	host->cmdat &= ~CMD_DAT_CONT_INIT;
	if (data) {
		mxcmci_setup_data(host, data);

		cmdat |= CMD_DAT_CONT_DATA_ENABLE;

		if (data->flags & MMC_DATA_WRITE)
			cmdat |= CMD_DAT_CONT_WRITE;
	}

	if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
		mxcmci_finish_request(host, cmd, data);
		return ret;
	}

	do {
		stat = readl(&host->base->status);
		writel(stat, &host->base->status);
	} while (!(stat & STATUS_END_CMD_RESP));

	return mxcmci_cmd_done(host, stat);
}

static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
{
	unsigned int divider;
	int prescaler = 0;
	unsigned long clk_in = mxc_get_clock(MXC_ESDHC_CLK);

	while (prescaler <= 0x800) {
		for (divider = 1; divider <= 0xF; divider++) {
			int x;

			x = (clk_in / (divider + 1));

			if (prescaler)
				x /= (prescaler * 2);

			if (x <= clk_ios)
				break;
		}
		if (divider < 0x10)
			break;

		if (prescaler == 0)
			prescaler = 1;
		else
			prescaler <<= 1;
	}

	writel((prescaler << 4) | divider, &host->base->clk_rate);
}

static int mxcmci_set_ios(struct mmc *mmc)
{
	struct mxcmci_host *host = mmc->priv;
	if (mmc->bus_width == 4)
		host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
	else
		host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;

	if (mmc->clock) {
		mxcmci_set_clk_rate(host, mmc->clock);
		writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
	} else {
		writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
	}

	host->clock = mmc->clock;

	return 0;
}

static int mxcmci_init(struct mmc *mmc)
{
	struct mxcmci_host *host = mmc->priv;

	mxcmci_softreset(host);

	host->rev_no = readl(&host->base->rev_no);
	if (host->rev_no != 0x400) {
		printf("wrong rev.no. 0x%08x. aborting.\n",
			host->rev_no);
		return -ENODEV;
	}

	/* recommended in data sheet */
	writel(0x2db4, &host->base->read_to);

	writel(0, &host->base->int_cntr);

	return 0;
}

static const struct mmc_ops mxcmci_ops = {
	.send_cmd	= mxcmci_request,
	.set_ios	= mxcmci_set_ios,
	.init		= mxcmci_init,
};

static struct mmc_config mxcmci_cfg = {
	.name		= "MXC MCI",
	.ops		= &mxcmci_ops,
	.host_caps	= MMC_MODE_4BIT,
	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
};

static int mxcmci_initialize(bd_t *bis)
{
	host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;

	mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
	mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;

	host->mmc = mmc_create(&mxcmci_cfg, host);
	if (host->mmc == NULL)
		return -1;

	return 0;
}

int mxc_mmc_init(bd_t *bis)
{
	return mxcmci_initialize(bis);
}
Commit	Line	Data
ba3dbaf2 IY	1	/*
	2	* This is a driver for the SDHC controller found in Freescale MX2/MX3
	3	* SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
	4	* Unlike the hardware found on MX1, this hardware just works and does
	5	* not need all the quirks found in imxmmc.c, hence the seperate driver.
	6	*
	7	* Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
	8	* Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	9	* Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
	10	*
	11	* derived from pxamci.c by Russell King
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*
	17	*/
	18
	19	#include <config.h>
	20	#include <common.h>
	21	#include <command.h>
	22	#include <mmc.h>
	23	#include <part.h>
	24	#include <malloc.h>
	25	#include <mmc.h>
1221ce45	26	#include <linux/errno.h>
ba3dbaf2	27	#include <asm/io.h>
ba3dbaf2	28	#include <asm/arch/clock.h>
ba3dbaf2 IY	29
	30	#define DRIVER_NAME "mxc-mmc"
	31
	32	struct mxcmci_regs {
	33	u32 str_stp_clk;
	34	u32 status;
	35	u32 clk_rate;
	36	u32 cmd_dat_cont;
	37	u32 res_to;
	38	u32 read_to;
	39	u32 blk_len;
	40	u32 nob;
	41	u32 rev_no;
	42	u32 int_cntr;
	43	u32 cmd;
	44	u32 arg;
	45	u32 pad;
	46	u32 res_fifo;
	47	u32 buffer_access;
	48	};
	49
	50	#define STR_STP_CLK_RESET (1 << 3)
	51	#define STR_STP_CLK_START_CLK (1 << 1)
	52	#define STR_STP_CLK_STOP_CLK (1 << 0)
	53
	54	#define STATUS_CARD_INSERTION (1 << 31)
	55	#define STATUS_CARD_REMOVAL (1 << 30)
	56	#define STATUS_YBUF_EMPTY (1 << 29)
	57	#define STATUS_XBUF_EMPTY (1 << 28)
	58	#define STATUS_YBUF_FULL (1 << 27)
	59	#define STATUS_XBUF_FULL (1 << 26)
	60	#define STATUS_BUF_UND_RUN (1 << 25)
	61	#define STATUS_BUF_OVFL (1 << 24)
	62	#define STATUS_SDIO_INT_ACTIVE (1 << 14)
	63	#define STATUS_END_CMD_RESP (1 << 13)
	64	#define STATUS_WRITE_OP_DONE (1 << 12)
	65	#define STATUS_DATA_TRANS_DONE (1 << 11)
	66	#define STATUS_READ_OP_DONE (1 << 11)
	67	#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
	68	#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
	69	#define STATUS_BUF_READ_RDY (1 << 7)
	70	#define STATUS_BUF_WRITE_RDY (1 << 6)
	71	#define STATUS_RESP_CRC_ERR (1 << 5)
	72	#define STATUS_CRC_READ_ERR (1 << 3)
	73	#define STATUS_CRC_WRITE_ERR (1 << 2)
	74	#define STATUS_TIME_OUT_RESP (1 << 1)
	75	#define STATUS_TIME_OUT_READ (1 << 0)
	76	#define STATUS_ERR_MASK 0x2f
	77
	78	#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
	79	#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
	80	#define CMD_DAT_CONT_START_READWAIT (1 << 10)
	81	#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
	82	#define CMD_DAT_CONT_INIT (1 << 7)
	83	#define CMD_DAT_CONT_WRITE (1 << 4)
	84	#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
	85	#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
	86	#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
	87	#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
	88
	89	#define INT_SDIO_INT_WKP_EN (1 << 18)
	90	#define INT_CARD_INSERTION_WKP_EN (1 << 17)
	91	#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
	92	#define INT_CARD_INSERTION_EN (1 << 15)
93	#define INT_CARD_REMOVAL_EN (1 << 14)
94	#define INT_SDIO_IRQ_EN (1 << 13)
95	#define INT_DAT0_EN (1 << 12)
96	#define INT_BUF_READ_EN (1 << 4)
97	#define INT_BUF_WRITE_EN (1 << 3)
98	#define INT_END_CMD_RES_EN (1 << 2)
99	#define INT_WRITE_OP_DONE_EN (1 << 1)
100	#define INT_READ_OP_EN (1 << 0)
101
102	struct mxcmci_host {
103	struct mmc *mmc;
104	struct mxcmci_regs *base;
105	int irq;
106	int detect_irq;
107	int dma;
108	int do_dma;
109	unsigned int power_mode;
110
111	struct mmc_cmd *cmd;
112	struct mmc_data *data;
113
114	unsigned int dma_nents;
115	unsigned int datasize;
116	unsigned int dma_dir;
117
118	u16 rev_no;
119	unsigned int cmdat;
120
121	int clock;
122	};
123
124	static struct mxcmci_host mxcmci_host;
93bfd616 PA	125
93bfd616 PA	126	/* maintainer note: do we really want to have a global host pointer? */
ba3dbaf2 IY	127	static struct mxcmci_host *host = &mxcmci_host;
	128
	129	static inline int mxcmci_use_dma(struct mxcmci_host *host)
	130	{
	131	return host->do_dma;
	132	}
	133
	134	static void mxcmci_softreset(struct mxcmci_host *host)
	135	{
	136	int i;
	137
	138	/* reset sequence */
99c006a3 SB	139	writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
99c006a3 SB	140	writel(STR_STP_CLK_RESET \| STR_STP_CLK_START_CLK,
ba3dbaf2 IY	141	&host->base->str_stp_clk);
	142
	143	for (i = 0; i < 8; i++)
99c006a3	144	writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
ba3dbaf2	145
99c006a3	146	writel(0xff, &host->base->res_to);
ba3dbaf2 IY	147	}
	148
	149	static void mxcmci_setup_data(struct mxcmci_host host, struct mmc_data data)
	150	{
	151	unsigned int nob = data->blocks;
	152	unsigned int blksz = data->blocksize;
	153	unsigned int datasize = nob * blksz;
	154
	155	host->data = data;
	156
99c006a3 SB	157	writel(nob, &host->base->nob);
99c006a3 SB	158	writel(blksz, &host->base->blk_len);
ba3dbaf2 IY	159	host->datasize = datasize;
	160	}
	161
	162	static int mxcmci_start_cmd(struct mxcmci_host host, struct mmc_cmd cmd,
	163	unsigned int cmdat)
	164	{
	165	if (host->cmd != NULL)
	166	printf("mxcmci: error!\n");
	167	host->cmd = cmd;
	168
	169	switch (cmd->resp_type) {
	170	case MMC_RSP_R1: /* short CRC, OPCODE */
	171	case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
	172	cmdat \|= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
	173	break;
	174	case MMC_RSP_R2: /* long 136 bit + CRC */
	175	cmdat \|= CMD_DAT_CONT_RESPONSE_136BIT;
	176	break;
	177	case MMC_RSP_R3: /* short */
	178	cmdat \|= CMD_DAT_CONT_RESPONSE_48BIT;
	179	break;
	180	case MMC_RSP_NONE:
	181	break;
	182	default:
	183	printf("mxcmci: unhandled response type 0x%x\n",
	184	cmd->resp_type);
	185	return -EINVAL;
	186	}
	187
99c006a3	188	writel(cmd->cmdidx, &host->base->cmd);
ba3dbaf2	189	writel(cmd->cmdarg, &host->base->arg);
99c006a3	190	writel(cmdat, &host->base->cmd_dat_cont);
ba3dbaf2 IY	191
	192	return 0;
	193	}
	194
	195	static void mxcmci_finish_request(struct mxcmci_host *host,
	196	struct mmc_cmd cmd, struct mmc_data data)
	197	{
	198	host->cmd = NULL;
	199	host->data = NULL;
	200	}
	201
	202	static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
	203	{
	204	int data_error = 0;
	205
	206	if (stat & STATUS_ERR_MASK) {
	207	printf("request failed. status: 0x%08x\n",
	208	stat);
	209	if (stat & STATUS_CRC_READ_ERR) {
	210	data_error = -EILSEQ;
	211	} else if (stat & STATUS_CRC_WRITE_ERR) {
	212	u32 err_code = (stat >> 9) & 0x3;
	213	if (err_code == 2) /* No CRC response */
915ffa52	214	data_error = -ETIMEDOUT;
ba3dbaf2 IY	215	else
	216	data_error = -EILSEQ;
	217	} else if (stat & STATUS_TIME_OUT_READ) {
915ffa52	218	data_error = -ETIMEDOUT;
ba3dbaf2 IY	219	} else {
	220	data_error = -EIO;
	221	}
	222	}
	223
	224	host->data = NULL;
	225
	226	return data_error;
	227	}
	228
	229	static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
	230	{
	231	struct mmc_cmd *cmd = host->cmd;
	232	int i;
	233	u32 a, b, c;
	234	u32 resp = (u32 )cmd->response;
	235
	236	if (!cmd)
	237	return 0;
	238
	239	if (stat & STATUS_TIME_OUT_RESP) {
	240	printf("CMD TIMEOUT\n");
915ffa52	241	return -ETIMEDOUT;
ba3dbaf2 IY	242	} else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
	243	printf("cmd crc error\n");
	244	return -EILSEQ;
	245	}
	246
	247	if (cmd->resp_type & MMC_RSP_PRESENT) {
	248	if (cmd->resp_type & MMC_RSP_136) {
	249	for (i = 0; i < 4; i++) {
99c006a3 SB	250	a = readl(&host->base->res_fifo) & 0xFFFF;
99c006a3 SB	251	b = readl(&host->base->res_fifo) & 0xFFFF;
ba3dbaf2 IY	252	resp[i] = a << 16 \| b;
	253	}
	254	} else {
99c006a3 SB	255	a = readl(&host->base->res_fifo) & 0xFFFF;
	256	b = readl(&host->base->res_fifo) & 0xFFFF;
	257	c = readl(&host->base->res_fifo) & 0xFFFF;
ba3dbaf2 IY	258	resp[0] = a << 24 \| b << 8 \| c >> 8;
	259	}
	260	}
	261	return 0;
	262	}
	263
	264	static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
	265	{
	266	u32 stat;
	267	unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;
	268
	269	do {
	270	stat = readl(&host->base->status);
	271	if (stat & STATUS_ERR_MASK)
	272	return stat;
	273	if (timeout < get_ticks())
	274	return STATUS_TIME_OUT_READ;
	275	if (stat & mask)
	276	return 0;
	277	} while (1);
	278	}
	279
	280	static int mxcmci_pull(struct mxcmci_host host, void _buf, int bytes)
	281	{
	282	unsigned int stat;
	283	u32 *buf = _buf;
	284
	285	while (bytes > 3) {
	286	stat = mxcmci_poll_status(host,
	287	STATUS_BUF_READ_RDY \| STATUS_READ_OP_DONE);
	288	if (stat)
	289	return stat;
	290	*buf++ = readl(&host->base->buffer_access);
	291	bytes -= 4;
	292	}
	293
	294	if (bytes) {
	295	u8 b = (u8 )buf;
	296	u32 tmp;
	297
	298	stat = mxcmci_poll_status(host,
	299	STATUS_BUF_READ_RDY \| STATUS_READ_OP_DONE);
	300	if (stat)
	301	return stat;
	302	tmp = readl(&host->base->buffer_access);
	303	memcpy(b, &tmp, bytes);
	304	}
	305
	306	return 0;
	307	}
	308
	309	static int mxcmci_push(struct mxcmci_host host, const void _buf, int bytes)
	310	{
	311	unsigned int stat;
	312	const u32 *buf = _buf;
	313
	314	while (bytes > 3) {
	315	stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
	316	if (stat)
	317	return stat;
	318	writel(*buf++, &host->base->buffer_access);
	319	bytes -= 4;
	320	}
	321
322	if (bytes) {
323	const u8 b = (u8 )buf;
324	u32 tmp;
325
326	stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
327	if (stat)
328	return stat;
329
330	memcpy(&tmp, b, bytes);
331	writel(tmp, &host->base->buffer_access);
332	}
333
334	stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
335	if (stat)
336	return stat;
337
338	return 0;
339	}
340
341	static int mxcmci_transfer_data(struct mxcmci_host *host)
342	{
343	struct mmc_data *data = host->data;
344	int stat;
345	unsigned long length;
346
347	length = data->blocks * data->blocksize;
348	host->datasize = 0;
349
350	if (data->flags & MMC_DATA_READ) {
351	stat = mxcmci_pull(host, data->dest, length);
352	if (stat)
353	return stat;
354	host->datasize += length;
355	} else {
356	stat = mxcmci_push(host, (const void *)(data->src), length);
357	if (stat)
358	return stat;
359	host->datasize += length;
360	stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
361	if (stat)
362	return stat;
363	}
364	return 0;
365	}
366
367	static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
368	{
369	int datastat;
370	int ret;
371
372	ret = mxcmci_read_response(host, stat);
373
374	if (ret) {
375	mxcmci_finish_request(host, host->cmd, host->data);
376	return ret;
377	}
378
379	if (!host->data) {
380	mxcmci_finish_request(host, host->cmd, host->data);
381	return 0;
382	}
383
384	datastat = mxcmci_transfer_data(host);
385	ret = mxcmci_finish_data(host, datastat);
386	mxcmci_finish_request(host, host->cmd, host->data);
387	return ret;
388	}
389
390	static int mxcmci_request(struct mmc mmc, struct mmc_cmd cmd,
391	struct mmc_data *data)
392	{
393	struct mxcmci_host *host = mmc->priv;
394	unsigned int cmdat = host->cmdat;
395	u32 stat;
396	int ret;
397
398	host->cmdat &= ~CMD_DAT_CONT_INIT;
399	if (data) {
400	mxcmci_setup_data(host, data);
401
402	cmdat \|= CMD_DAT_CONT_DATA_ENABLE;
403
404	if (data->flags & MMC_DATA_WRITE)
405	cmdat \|= CMD_DAT_CONT_WRITE;
406	}
407
408	if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
409	mxcmci_finish_request(host, cmd, data);
410	return ret;
411	}
412
413	do {
414	stat = readl(&host->base->status);
415	writel(stat, &host->base->status);
416	} while (!(stat & STATUS_END_CMD_RESP));
417
418	return mxcmci_cmd_done(host, stat);
419	}
420
421	static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
422	{
423	unsigned int divider;
424	int prescaler = 0;
fa47a286	425	unsigned long clk_in = mxc_get_clock(MXC_ESDHC_CLK);
ba3dbaf2 IY	426
	427	while (prescaler <= 0x800) {
	428	for (divider = 1; divider <= 0xF; divider++) {
	429	int x;
	430
	431	x = (clk_in / (divider + 1));
	432
	433	if (prescaler)
	434	x /= (prescaler * 2);
	435
	436	if (x <= clk_ios)
	437	break;
	438	}
	439	if (divider < 0x10)
	440	break;
	441
	442	if (prescaler == 0)
	443	prescaler = 1;
	444	else
	445	prescaler <<= 1;
	446	}
	447
99c006a3	448	writel((prescaler << 4) \| divider, &host->base->clk_rate);
ba3dbaf2 IY	449	}
ba3dbaf2 IY	450
07b0b9c0	451	static int mxcmci_set_ios(struct mmc *mmc)
ba3dbaf2 IY	452	{
	453	struct mxcmci_host *host = mmc->priv;
	454	if (mmc->bus_width == 4)
	455	host->cmdat \|= CMD_DAT_CONT_BUS_WIDTH_4;
	456	else
	457	host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
	458
	459	if (mmc->clock) {
	460	mxcmci_set_clk_rate(host, mmc->clock);
99c006a3	461	writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
ba3dbaf2	462	} else {
99c006a3	463	writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
ba3dbaf2 IY	464	}
	465
	466	host->clock = mmc->clock;
07b0b9c0 JC	467
07b0b9c0 JC	468	return 0;
ba3dbaf2 IY	469	}
	470
	471	static int mxcmci_init(struct mmc *mmc)
	472	{
	473	struct mxcmci_host *host = mmc->priv;
	474
	475	mxcmci_softreset(host);
	476
99c006a3	477	host->rev_no = readl(&host->base->rev_no);
ba3dbaf2 IY	478	if (host->rev_no != 0x400) {
	479	printf("wrong rev.no. 0x%08x. aborting.\n",
	480	host->rev_no);
	481	return -ENODEV;
	482	}
	483
	484	/* recommended in data sheet */
99c006a3	485	writel(0x2db4, &host->base->read_to);
ba3dbaf2 IY	486
	487	writel(0, &host->base->int_cntr);
	488
	489	return 0;
	490	}
	491
ab769f22 PA	492	static const struct mmc_ops mxcmci_ops = {
	493	.send_cmd = mxcmci_request,
	494	.set_ios = mxcmci_set_ios,
	495	.init = mxcmci_init,
	496	};
	497
93bfd616 PA	498	static struct mmc_config mxcmci_cfg = {
	499	.name = "MXC MCI",
	500	.ops = &mxcmci_ops,
	501	.host_caps = MMC_MODE_4BIT,
	502	.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,
	503	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
	504	};
	505
ba3dbaf2 IY	506	static int mxcmci_initialize(bd_t *bis)
ba3dbaf2 IY	507	{
ba3dbaf2	508	host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
ba3dbaf2	509
93bfd616 PA	510	mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
93bfd616 PA	511	mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
8feafcc4	512
93bfd616 PA	513	host->mmc = mmc_create(&mxcmci_cfg, host);
	514	if (host->mmc == NULL)
	515	return -1;
ba3dbaf2 IY	516
	517	return 0;
	518	}
	519
	520	int mxc_mmc_init(bd_t *bis)
	521	{
	522	return mxcmci_initialize(bis);
	523	}