[people/ms/u-boot.git] / drivers / mmc / mxsmmc.c

/*
 * Freescale i.MX28 SSP MMC driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * Based on code from LTIB:
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 * Terry Lv
 *
 * Copyright 2007, Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based vaguely on the pxa mmc code:
 * (C) Copyright 2003
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/dma.h>
#include <bouncebuf.h>

struct mxsmmc_priv {
	int			id;
	struct mxs_ssp_regs	*regs;
	uint32_t		buswidth;
	int			(*mmc_is_wp)(int);
	int			(*mmc_cd)(int);
	struct mxs_dma_desc	*desc;
	struct mmc_config	cfg;	/* mmc configuration */
};

#define	MXSMMC_MAX_TIMEOUT	10000
#define MXSMMC_SMALL_TRANSFER	512

static int mxsmmc_cd(struct mxsmmc_priv *priv)
{
	struct mxs_ssp_regs *ssp_regs = priv->regs;

	if (priv->mmc_cd)
		return priv->mmc_cd(priv->id);

	return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
}

static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
{
	struct mxs_ssp_regs *ssp_regs = priv->regs;
	uint32_t *data_ptr;
	int timeout = MXSMMC_MAX_TIMEOUT;
	uint32_t reg;
	uint32_t data_count = data->blocksize * data->blocks;

	if (data->flags & MMC_DATA_READ) {
		data_ptr = (uint32_t *)data->dest;
		while (data_count && --timeout) {
			reg = readl(&ssp_regs->hw_ssp_status);
			if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
				*data_ptr++ = readl(&ssp_regs->hw_ssp_data);
				data_count -= 4;
				timeout = MXSMMC_MAX_TIMEOUT;
			} else
				udelay(1000);
		}
	} else {
		data_ptr = (uint32_t *)data->src;
		timeout *= 100;
		while (data_count && --timeout) {
			reg = readl(&ssp_regs->hw_ssp_status);
			if (!(reg & SSP_STATUS_FIFO_FULL)) {
				writel(*data_ptr++, &ssp_regs->hw_ssp_data);
				data_count -= 4;
				timeout = MXSMMC_MAX_TIMEOUT;
			} else
				udelay(1000);
		}
	}

	return timeout ? 0 : COMM_ERR;
}

static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
{
	uint32_t data_count = data->blocksize * data->blocks;
	int dmach;
	struct mxs_dma_desc *desc = priv->desc;
	void *addr;
	unsigned int flags;
	struct bounce_buffer bbstate;

	memset(desc, 0, sizeof(struct mxs_dma_desc));
	desc->address = (dma_addr_t)desc;

	if (data->flags & MMC_DATA_READ) {
		priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
		addr = data->dest;
		flags = GEN_BB_WRITE;
	} else {
		priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
		addr = (void *)data->src;
		flags = GEN_BB_READ;
	}

	bounce_buffer_start(&bbstate, addr, data_count, flags);

	priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;

	priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
				(data_count << MXS_DMA_DESC_BYTES_OFFSET);

	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
	mxs_dma_desc_append(dmach, priv->desc);
	if (mxs_dma_go(dmach)) {
		bounce_buffer_stop(&bbstate);
		return COMM_ERR;
	}

	bounce_buffer_stop(&bbstate);

	return 0;
}

/*
 * Sends a command out on the bus.  Takes the mmc pointer,
 * a command pointer, and an optional data pointer.
 */
static int
mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	struct mxsmmc_priv *priv = mmc->priv;
	struct mxs_ssp_regs *ssp_regs = priv->regs;
	uint32_t reg;
	int timeout;
	uint32_t ctrl0;
	int ret;

	debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);

	/* Check bus busy */
	timeout = MXSMMC_MAX_TIMEOUT;
	while (--timeout) {
		udelay(1000);
		reg = readl(&ssp_regs->hw_ssp_status);
		if (!(reg &
			(SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
			SSP_STATUS_CMD_BUSY))) {
			break;
		}
	}

	if (!timeout) {
		printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
		return TIMEOUT;
	}

	/* See if card is present */
	if (!mxsmmc_cd(priv)) {
		printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
		return NO_CARD_ERR;
	}

	/* Start building CTRL0 contents */
	ctrl0 = priv->buswidth;

	/* Set up command */
	if (!(cmd->resp_type & MMC_RSP_CRC))
		ctrl0 |= SSP_CTRL0_IGNORE_CRC;
	if (cmd->resp_type & MMC_RSP_PRESENT)	/* Need to get response */
		ctrl0 |= SSP_CTRL0_GET_RESP;
	if (cmd->resp_type & MMC_RSP_136)	/* It's a 136 bits response */
		ctrl0 |= SSP_CTRL0_LONG_RESP;

	if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
	else
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);

	/* Command index */
	reg = readl(&ssp_regs->hw_ssp_cmd0);
	reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
	reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		reg |= SSP_CMD0_APPEND_8CYC;
	writel(reg, &ssp_regs->hw_ssp_cmd0);

	/* Command argument */
	writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);

	/* Set up data */
	if (data) {
		/* READ or WRITE */
		if (data->flags & MMC_DATA_READ) {
			ctrl0 |= SSP_CTRL0_READ;
		} else if (priv->mmc_is_wp &&
			priv->mmc_is_wp(mmc->block_dev.dev)) {
			printf("MMC%d: Can not write a locked card!\n",
				mmc->block_dev.dev);
			return UNUSABLE_ERR;
		}

		ctrl0 |= SSP_CTRL0_DATA_XFER;

		reg = data->blocksize * data->blocks;
#if defined(CONFIG_MX23)
		ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;

		clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
			SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
			((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
			((ffs(data->blocksize) - 1) <<
				SSP_CMD0_BLOCK_SIZE_OFFSET));
#elif defined(CONFIG_MX28)
		writel(reg, &ssp_regs->hw_ssp_xfer_size);

		reg = ((data->blocks - 1) <<
			SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
			((ffs(data->blocksize) - 1) <<
			SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
		writel(reg, &ssp_regs->hw_ssp_block_size);
#endif
	}

	/* Kick off the command */
	ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
	writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);

	/* Wait for the command to complete */
	timeout = MXSMMC_MAX_TIMEOUT;
	while (--timeout) {
		udelay(1000);
		reg = readl(&ssp_regs->hw_ssp_status);
		if (!(reg & SSP_STATUS_CMD_BUSY))
			break;
	}

	if (!timeout) {
		printf("MMC%d: Command %d busy\n",
			mmc->block_dev.dev, cmd->cmdidx);
		return TIMEOUT;
	}

	/* Check command timeout */
	if (reg & SSP_STATUS_RESP_TIMEOUT) {
		printf("MMC%d: Command %d timeout (status 0x%08x)\n",
			mmc->block_dev.dev, cmd->cmdidx, reg);
		return TIMEOUT;
	}

	/* Check command errors */
	if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
		printf("MMC%d: Command %d error (status 0x%08x)!\n",
			mmc->block_dev.dev, cmd->cmdidx, reg);
		return COMM_ERR;
	}

	/* Copy response to response buffer */
	if (cmd->resp_type & MMC_RSP_136) {
		cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
		cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
		cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
		cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
	} else
		cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);

	/* Return if no data to process */
	if (!data)
		return 0;

	if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
		ret = mxsmmc_send_cmd_pio(priv, data);
		if (ret) {
			printf("MMC%d: Data timeout with command %d "
				"(status 0x%08x)!\n",
				mmc->block_dev.dev, cmd->cmdidx, reg);
			return ret;
		}
	} else {
		ret = mxsmmc_send_cmd_dma(priv, data);
		if (ret) {
			printf("MMC%d: DMA transfer failed\n",
				mmc->block_dev.dev);
			return ret;
		}
	}

	/* Check data errors */
	reg = readl(&ssp_regs->hw_ssp_status);
	if (reg &
		(SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
		SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
		printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
			mmc->block_dev.dev, cmd->cmdidx, reg);
		return COMM_ERR;
	}

	return 0;
}

static void mxsmmc_set_ios(struct mmc *mmc)
{
	struct mxsmmc_priv *priv = mmc->priv;
	struct mxs_ssp_regs *ssp_regs = priv->regs;

	/* Set the clock speed */
	if (mmc->clock)
		mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);

	switch (mmc->bus_width) {
	case 1:
		priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
		break;
	case 4:
		priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
		break;
	case 8:
		priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
		break;
	}

	/* Set the bus width */
	clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
			SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);

	debug("MMC%d: Set %d bits bus width\n",
		mmc->block_dev.dev, mmc->bus_width);
}

static int mxsmmc_init(struct mmc *mmc)
{
	struct mxsmmc_priv *priv = mmc->priv;
	struct mxs_ssp_regs *ssp_regs = priv->regs;

	/* Reset SSP */
	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);

	/* Reconfigure the SSP block for MMC operation */
	writel(SSP_CTRL1_SSP_MODE_SD_MMC |
		SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
		SSP_CTRL1_DMA_ENABLE |
		SSP_CTRL1_POLARITY |
		SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
		SSP_CTRL1_DATA_CRC_IRQ_EN |
		SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
		SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
		SSP_CTRL1_RESP_ERR_IRQ_EN,
		&ssp_regs->hw_ssp_ctrl1_set);

	/* Set initial bit clock 400 KHz */
	mxs_set_ssp_busclock(priv->id, 400);

	/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
	udelay(200);
	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);

	return 0;
}

static const struct mmc_ops mxsmmc_ops = {
	.send_cmd	= mxsmmc_send_cmd,
	.set_ios	= mxsmmc_set_ios,
	.init		= mxsmmc_init,
};

int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
{
	struct mmc *mmc = NULL;
	struct mxsmmc_priv *priv = NULL;
	int ret;
	const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);

	if (!mxs_ssp_bus_id_valid(id))
		return -ENODEV;

	priv = malloc(sizeof(struct mxsmmc_priv));
	if (!priv)
		return -ENOMEM;

	priv->desc = mxs_dma_desc_alloc();
	if (!priv->desc) {
		free(priv);
		return -ENOMEM;
	}

	ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
	if (ret)
		return ret;

	priv->mmc_is_wp = wp;
	priv->mmc_cd = cd;
	priv->id = id;
	priv->regs = mxs_ssp_regs_by_bus(id);

	priv->cfg.name = "MXS MMC";
	priv->cfg.ops = &mxsmmc_ops;

	priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;

	priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
			 MMC_MODE_HS_52MHz | MMC_MODE_HS |
			 MMC_MODE_HC;

	/*
	 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
	 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
	 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
	 * CLOCK_RATE could be any integer from 0 to 255.
	 */
	priv->cfg.f_min = 400000;
	priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
	priv->cfg.b_max = 0x20;

	mmc = mmc_create(&priv->cfg, priv);
	if (mmc == NULL) {
		mxs_dma_desc_free(priv->desc);
		free(priv);
		return -ENOMEM;
	}
	return 0;
}
Commit	Line	Data
71a758e1 MV	1	/*
	2	* Freescale i.MX28 SSP MMC driver
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
	7	* Based on code from LTIB:
	8	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	9	* Terry Lv
	10	*
	11	* Copyright 2007, Freescale Semiconductor, Inc
	12	* Andy Fleming
	13	*
	14	* Based vaguely on the pxa mmc code:
	15	* (C) Copyright 2003
	16	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	17	*
1a459660	18	* SPDX-License-Identifier: GPL-2.0+
71a758e1 MV	19	*/
	20	#include <common.h>
	21	#include <malloc.h>
	22	#include <mmc.h>
	23	#include <asm/errno.h>
	24	#include <asm/io.h>
	25	#include <asm/arch/clock.h>
	26	#include <asm/arch/imx-regs.h>
	27	#include <asm/arch/sys_proto.h>
0499218d	28	#include <asm/imx-common/dma.h>
4e6d81d1	29	#include <bouncebuf.h>
71a758e1 MV	30
	31	struct mxsmmc_priv {
	32	int id;
9c471142	33	struct mxs_ssp_regs *regs;
71a758e1 MV	34	uint32_t buswidth;
71a758e1 MV	35	int (*mmc_is_wp)(int);
90bc2bf2	36	int (*mmc_cd)(int);
3687c415	37	struct mxs_dma_desc *desc;
93bfd616	38	struct mmc_config cfg; /* mmc configuration */
71a758e1 MV	39	};
	40
	41	#define MXSMMC_MAX_TIMEOUT 10000
20255900	42	#define MXSMMC_SMALL_TRANSFER 512
71a758e1	43
90bc2bf2 MV	44	static int mxsmmc_cd(struct mxsmmc_priv *priv)
	45	{
	46	struct mxs_ssp_regs *ssp_regs = priv->regs;
	47
	48	if (priv->mmc_cd)
	49	return priv->mmc_cd(priv->id);
	50
	51	return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
	52	}
	53
86983328 MV	54	static int mxsmmc_send_cmd_pio(struct mxsmmc_priv priv, struct mmc_data data)
	55	{
	56	struct mxs_ssp_regs *ssp_regs = priv->regs;
	57	uint32_t *data_ptr;
	58	int timeout = MXSMMC_MAX_TIMEOUT;
	59	uint32_t reg;
	60	uint32_t data_count = data->blocksize * data->blocks;
	61
	62	if (data->flags & MMC_DATA_READ) {
	63	data_ptr = (uint32_t *)data->dest;
	64	while (data_count && --timeout) {
	65	reg = readl(&ssp_regs->hw_ssp_status);
	66	if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
	67	*data_ptr++ = readl(&ssp_regs->hw_ssp_data);
	68	data_count -= 4;
	69	timeout = MXSMMC_MAX_TIMEOUT;
	70	} else
	71	udelay(1000);
	72	}
	73	} else {
	74	data_ptr = (uint32_t *)data->src;
	75	timeout *= 100;
	76	while (data_count && --timeout) {
	77	reg = readl(&ssp_regs->hw_ssp_status);
	78	if (!(reg & SSP_STATUS_FIFO_FULL)) {
	79	writel(*data_ptr++, &ssp_regs->hw_ssp_data);
	80	data_count -= 4;
	81	timeout = MXSMMC_MAX_TIMEOUT;
	82	} else
	83	udelay(1000);
	84	}
	85	}
	86
	87	return timeout ? 0 : COMM_ERR;
	88	}
20255900	89
86983328 MV	90	static int mxsmmc_send_cmd_dma(struct mxsmmc_priv priv, struct mmc_data data)
	91	{
	92	uint32_t data_count = data->blocksize * data->blocks;
86983328	93	int dmach;
abb85be7	94	struct mxs_dma_desc *desc = priv->desc;
84d35b28 SW	95	void *addr;
	96	unsigned int flags;
	97	struct bounce_buffer bbstate;
abb85be7 MV	98
	99	memset(desc, 0, sizeof(struct mxs_dma_desc));
	100	desc->address = (dma_addr_t)desc;
86983328	101
86983328 MV	102	if (data->flags & MMC_DATA_READ) {
86983328 MV	103	priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
4e6d81d1 MV	104	addr = data->dest;
4e6d81d1 MV	105	flags = GEN_BB_WRITE;
86983328 MV	106	} else {
86983328 MV	107	priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
4e6d81d1 MV	108	addr = (void *)data->src;
	109	flags = GEN_BB_READ;
	110	}
	111
84d35b28	112	bounce_buffer_start(&bbstate, addr, data_count, flags);
4e6d81d1	113
84d35b28	114	priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
97ed12ce	115
86983328 MV	116	priv->desc->cmd.data \|= MXS_DMA_DESC_IRQ \| MXS_DMA_DESC_DEC_SEM \|
	117	(data_count << MXS_DMA_DESC_BYTES_OFFSET);
	118
3430e0bd	119	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
86983328	120	mxs_dma_desc_append(dmach, priv->desc);
4e6d81d1	121	if (mxs_dma_go(dmach)) {
84d35b28	122	bounce_buffer_stop(&bbstate);
86983328	123	return COMM_ERR;
4e6d81d1	124	}
86983328	125
84d35b28	126	bounce_buffer_stop(&bbstate);
4e6d81d1	127
86983328 MV	128	return 0;
86983328 MV	129	}
86983328	130
71a758e1 MV	131	/*
	132	* Sends a command out on the bus. Takes the mmc pointer,
	133	* a command pointer, and an optional data pointer.
	134	*/
	135	static int
	136	mxsmmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
	137	{
93bfd616	138	struct mxsmmc_priv *priv = mmc->priv;
9c471142	139	struct mxs_ssp_regs *ssp_regs = priv->regs;
71a758e1 MV	140	uint32_t reg;
71a758e1 MV	141	int timeout;
71a758e1	142	uint32_t ctrl0;
86983328	143	int ret;
71a758e1 MV	144
	145	debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
	146
	147	/* Check bus busy */
	148	timeout = MXSMMC_MAX_TIMEOUT;
	149	while (--timeout) {
	150	udelay(1000);
	151	reg = readl(&ssp_regs->hw_ssp_status);
	152	if (!(reg &
	153	(SSP_STATUS_BUSY \| SSP_STATUS_DATA_BUSY \|
	154	SSP_STATUS_CMD_BUSY))) {
	155	break;
	156	}
	157	}
	158
	159	if (!timeout) {
	160	printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
	161	return TIMEOUT;
	162	}
	163
	164	/* See if card is present */
90bc2bf2	165	if (!mxsmmc_cd(priv)) {
71a758e1 MV	166	printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
	167	return NO_CARD_ERR;
	168	}
	169
	170	/* Start building CTRL0 contents */
	171	ctrl0 = priv->buswidth;
	172
	173	/* Set up command */
	174	if (!(cmd->resp_type & MMC_RSP_CRC))
	175	ctrl0 \|= SSP_CTRL0_IGNORE_CRC;
	176	if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
	177	ctrl0 \|= SSP_CTRL0_GET_RESP;
	178	if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
	179	ctrl0 \|= SSP_CTRL0_LONG_RESP;
	180
abb85be7 MV	181	if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
	182	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
	183	else
	184	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
	185
71a758e1 MV	186	/* Command index */
	187	reg = readl(&ssp_regs->hw_ssp_cmd0);
	188	reg &= ~(SSP_CMD0_CMD_MASK \| SSP_CMD0_APPEND_8CYC);
	189	reg \|= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
	190	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	191	reg \|= SSP_CMD0_APPEND_8CYC;
	192	writel(reg, &ssp_regs->hw_ssp_cmd0);
	193
	194	/* Command argument */
	195	writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
	196
	197	/* Set up data */
	198	if (data) {
	199	/* READ or WRITE */
	200	if (data->flags & MMC_DATA_READ) {
	201	ctrl0 \|= SSP_CTRL0_READ;
c7527b70 MV	202	} else if (priv->mmc_is_wp &&
c7527b70 MV	203	priv->mmc_is_wp(mmc->block_dev.dev)) {
71a758e1 MV	204	printf("MMC%d: Can not write a locked card!\n",
	205	mmc->block_dev.dev);
	206	return UNUSABLE_ERR;
	207	}
	208
	209	ctrl0 \|= SSP_CTRL0_DATA_XFER;
e5b380ac MV	210
	211	reg = data->blocksize * data->blocks;
	212	#if defined(CONFIG_MX23)
	213	ctrl0 \|= reg & SSP_CTRL0_XFER_COUNT_MASK;
	214
	215	clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
	216	SSP_CMD0_BLOCK_SIZE_MASK \| SSP_CMD0_BLOCK_COUNT_MASK,
	217	((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) \|
	218	((ffs(data->blocksize) - 1) <<
	219	SSP_CMD0_BLOCK_SIZE_OFFSET));
	220	#elif defined(CONFIG_MX28)
	221	writel(reg, &ssp_regs->hw_ssp_xfer_size);
	222
71a758e1 MV	223	reg = ((data->blocks - 1) <<
	224	SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) \|
	225	((ffs(data->blocksize) - 1) <<
	226	SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
	227	writel(reg, &ssp_regs->hw_ssp_block_size);
e5b380ac	228	#endif
71a758e1 MV	229	}
	230
	231	/* Kick off the command */
	232	ctrl0 \|= SSP_CTRL0_WAIT_FOR_IRQ \| SSP_CTRL0_ENABLE \| SSP_CTRL0_RUN;
	233	writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
	234
	235	/* Wait for the command to complete */
	236	timeout = MXSMMC_MAX_TIMEOUT;
	237	while (--timeout) {
	238	udelay(1000);
	239	reg = readl(&ssp_regs->hw_ssp_status);
	240	if (!(reg & SSP_STATUS_CMD_BUSY))
	241	break;
	242	}
	243
	244	if (!timeout) {
	245	printf("MMC%d: Command %d busy\n",
	246	mmc->block_dev.dev, cmd->cmdidx);
	247	return TIMEOUT;
	248	}
	249
	250	/* Check command timeout */
	251	if (reg & SSP_STATUS_RESP_TIMEOUT) {
	252	printf("MMC%d: Command %d timeout (status 0x%08x)\n",
	253	mmc->block_dev.dev, cmd->cmdidx, reg);
	254	return TIMEOUT;
	255	}
	256
	257	/* Check command errors */
	258	if (reg & (SSP_STATUS_RESP_CRC_ERR \| SSP_STATUS_RESP_ERR)) {
	259	printf("MMC%d: Command %d error (status 0x%08x)!\n",
	260	mmc->block_dev.dev, cmd->cmdidx, reg);
	261	return COMM_ERR;
	262	}
	263
	264	/* Copy response to response buffer */
	265	if (cmd->resp_type & MMC_RSP_136) {
	266	cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
	267	cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
	268	cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
	269	cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
	270	} else
	271	cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
	272
	273	/* Return if no data to process */
	274	if (!data)
	275	return 0;
	276
20255900	277	if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
20255900 MV	278	ret = mxsmmc_send_cmd_pio(priv, data);
	279	if (ret) {
	280	printf("MMC%d: Data timeout with command %d "
	281	"(status 0x%08x)!\n",
	282	mmc->block_dev.dev, cmd->cmdidx, reg);
	283	return ret;
	284	}
abb85be7 MV	285	} else {
	286	ret = mxsmmc_send_cmd_dma(priv, data);
	287	if (ret) {
	288	printf("MMC%d: DMA transfer failed\n",
	289	mmc->block_dev.dev);
	290	return ret;
	291	}
4cc76c60	292	}
3687c415	293
71a758e1 MV	294	/* Check data errors */
	295	reg = readl(&ssp_regs->hw_ssp_status);
	296	if (reg &
	297	(SSP_STATUS_TIMEOUT \| SSP_STATUS_DATA_CRC_ERR \|
	298	SSP_STATUS_FIFO_OVRFLW \| SSP_STATUS_FIFO_UNDRFLW)) {
	299	printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
	300	mmc->block_dev.dev, cmd->cmdidx, reg);
	301	return COMM_ERR;
	302	}
	303
	304	return 0;
	305	}
	306
	307	static void mxsmmc_set_ios(struct mmc *mmc)
	308	{
93bfd616	309	struct mxsmmc_priv *priv = mmc->priv;
9c471142	310	struct mxs_ssp_regs *ssp_regs = priv->regs;
71a758e1 MV	311
	312	/* Set the clock speed */
	313	if (mmc->clock)
bf48fcb6	314	mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
71a758e1 MV	315
	316	switch (mmc->bus_width) {
	317	case 1:
	318	priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
	319	break;
	320	case 4:
	321	priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
	322	break;
	323	case 8:
	324	priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
	325	break;
	326	}
	327
	328	/* Set the bus width */
	329	clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
	330	SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
	331
	332	debug("MMC%d: Set %d bits bus width\n",
	333	mmc->block_dev.dev, mmc->bus_width);
	334	}
	335
	336	static int mxsmmc_init(struct mmc *mmc)
	337	{
93bfd616	338	struct mxsmmc_priv *priv = mmc->priv;
9c471142	339	struct mxs_ssp_regs *ssp_regs = priv->regs;
71a758e1 MV	340
71a758e1 MV	341	/* Reset SSP */
fa7a51cb	342	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
71a758e1	343
8000d8a8 OS	344	/* Reconfigure the SSP block for MMC operation */
	345	writel(SSP_CTRL1_SSP_MODE_SD_MMC \|
	346	SSP_CTRL1_WORD_LENGTH_EIGHT_BITS \|
	347	SSP_CTRL1_DMA_ENABLE \|
	348	SSP_CTRL1_POLARITY \|
	349	SSP_CTRL1_RECV_TIMEOUT_IRQ_EN \|
	350	SSP_CTRL1_DATA_CRC_IRQ_EN \|
	351	SSP_CTRL1_DATA_TIMEOUT_IRQ_EN \|
	352	SSP_CTRL1_RESP_TIMEOUT_IRQ_EN \|
	353	SSP_CTRL1_RESP_ERR_IRQ_EN,
	354	&ssp_regs->hw_ssp_ctrl1_set);
71a758e1 MV	355
71a758e1 MV	356	/* Set initial bit clock 400 KHz */
bf48fcb6	357	mxs_set_ssp_busclock(priv->id, 400);
71a758e1 MV	358
	359	/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
	360	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
	361	udelay(200);
	362	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
	363
	364	return 0;
	365	}
	366
ab769f22 PA	367	static const struct mmc_ops mxsmmc_ops = {
	368	.send_cmd = mxsmmc_send_cmd,
	369	.set_ios = mxsmmc_set_ios,
	370	.init = mxsmmc_init,
	371	};
	372
90bc2bf2	373	int mxsmmc_initialize(bd_t bis, int id, int (wp)(int), int (*cd)(int))
71a758e1	374	{
71a758e1 MV	375	struct mmc *mmc = NULL;
71a758e1 MV	376	struct mxsmmc_priv *priv = NULL;
96666a39	377	int ret;
3430e0bd	378	const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
1a3c5ffe	379
3430e0bd	380	if (!mxs_ssp_bus_id_valid(id))
1a3c5ffe	381	return -ENODEV;
71a758e1	382
71a758e1	383	priv = malloc(sizeof(struct mxsmmc_priv));
93bfd616	384	if (!priv)
71a758e1	385	return -ENOMEM;
71a758e1	386
3687c415 MV	387	priv->desc = mxs_dma_desc_alloc();
	388	if (!priv->desc) {
	389	free(priv);
3687c415 MV	390	return -ENOMEM;
	391	}
	392
3430e0bd	393	ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
96666a39 MV	394	if (ret)
	395	return ret;
	396
71a758e1	397	priv->mmc_is_wp = wp;
90bc2bf2	398	priv->mmc_cd = cd;
71a758e1	399	priv->id = id;
14e26bcf	400	priv->regs = mxs_ssp_regs_by_bus(id);
71a758e1	401
93bfd616 PA	402	priv->cfg.name = "MXS MMC";
93bfd616 PA	403	priv->cfg.ops = &mxsmmc_ops;
71a758e1	404
93bfd616	405	priv->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
71a758e1	406
93bfd616	407	priv->cfg.host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT \|
49b0415a AP	408	MMC_MODE_HS_52MHz \| MMC_MODE_HS \|
49b0415a AP	409	MMC_MODE_HC;
71a758e1 MV	410
	411	/*
	412	* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
	413	* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
	414	* CLOCK_DIVIDE has to be an even value from 2 to 254, and
	415	* CLOCK_RATE could be any integer from 0 to 255.
	416	*/
93bfd616 PA	417	priv->cfg.f_min = 400000;
	418	priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
	419	priv->cfg.b_max = 0x20;
71a758e1	420
93bfd616 PA	421	mmc = mmc_create(&priv->cfg, priv);
	422	if (mmc == NULL) {
	423	mxs_dma_desc_free(priv->desc);
	424	free(priv);
	425	return -ENOMEM;
	426	}
71a758e1 MV	427	return 0;
71a758e1 MV	428	}