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mmc: omap_hsmmc: Add tuning support
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
CommitLineData
de941241
SG		 1/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
93bfd616 27#include <malloc.h>
f0d53e88 28#include <memalign.h>
de941241
SG		 29#include <mmc.h>
30#include <part.h>
31#include <i2c.h>
339d5789 32#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
cb199102 33#include <palmas.h>
339d5789 34#endif
de941241
SG		 35#include <asm/io.h>
36#include <asm/arch/mmc_host_def.h>
3b68939f
RQ		 37#if !defined(CONFIG_SOC_KEYSTONE)
38#include <asm/gpio.h>
96e0e7b3 39#include <asm/arch/sys_proto.h>
3b68939f 40#endif
2a48b3a2
TR		 41#ifdef CONFIG_MMC_OMAP36XX_PINS
42#include <asm/arch/mux.h>
43#endif
a9d6a7e2
M		 44#include <dm.h>
45
46DECLARE_GLOBAL_DATA_PTR;
de941241 47
ab769f22
PA		 48/* simplify defines to OMAP_HSMMC_USE_GPIO */
49#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51#define OMAP_HSMMC_USE_GPIO
52#else
53#undef OMAP_HSMMC_USE_GPIO
54#endif
55
25c719e2
GI		 56/* common definitions for all OMAPs */
57#define SYSCTL_SRC (1 << 25)
58#define SYSCTL_SRD (1 << 26)
59
cc22b0c0
NK		 60struct omap_hsmmc_data {
61 struct hsmmc *base_addr;
c4d660d4 62#if !CONFIG_IS_ENABLED(DM_MMC)
93bfd616 63 struct mmc_config cfg;
3d673ffc 64#endif
48a2f114 65 uint bus_width;
5baf543e 66 uint clock;
ab769f22 67#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 68#if CONFIG_IS_ENABLED(DM_MMC)
a9d6a7e2
M		 69 struct gpio_desc cd_gpio; /* Change Detect GPIO */
70 struct gpio_desc wp_gpio; /* Write Protect GPIO */
71 bool cd_inverted;
72#else
e874d5b0 73 int cd_gpio;
e3913f56 74 int wp_gpio;
ab769f22 75#endif
b5944817
KVA		 76#endif
77#if CONFIG_IS_ENABLED(DM_MMC)
78 uint iov;
8fc238bf 79 enum bus_mode mode;
a9d6a7e2 80#endif
f0d53e88
KVA		 81 u8 controller_flags;
82#ifndef CONFIG_OMAP34XX
83 struct omap_hsmmc_adma_desc *adma_desc_table;
84 uint desc_slot;
85#endif
86};
87
88#ifndef CONFIG_OMAP34XX
89struct omap_hsmmc_adma_desc {
90 u8 attr;
91 u8 reserved;
92 u16 len;
93 u32 addr;
cc22b0c0
NK		 94};
95
f0d53e88
KVA		 96#define ADMA_MAX_LEN 63488
97
98/* Decriptor table defines */
99#define ADMA_DESC_ATTR_VALID BIT(0)
100#define ADMA_DESC_ATTR_END BIT(1)
101#define ADMA_DESC_ATTR_INT BIT(2)
102#define ADMA_DESC_ATTR_ACT1 BIT(4)
103#define ADMA_DESC_ATTR_ACT2 BIT(5)
104
105#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
106#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
107#endif
108
eb9a28f6
NM		 109/* If we fail after 1 second wait, something is really bad */
110#define MAX_RETRY_MS 1000
111
f0d53e88
KVA		 112/* DMA transfers can take a long time if a lot a data is transferred.
113 * The timeout must take in account the amount of data. Let's assume
114 * that the time will never exceed 333 ms per MB (in other word we assume
115 * that the bandwidth is always above 3MB/s).
116 */
117#define DMA_TIMEOUT_PER_MB 333
b5944817
KVA		 118#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
119#define OMAP_HSMMC_NO_1_8_V BIT(1)
f0d53e88
KVA		 120#define OMAP_HSMMC_USE_ADMA BIT(2)
121
933efe64
S		 122static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
123static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
124 unsigned int siz);
5baf543e
JJH		 125static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
126static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
14761cae 127static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
14fa2dd0 128
ae000e23
JJH		 129static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
130{
c4d660d4 131#if CONFIG_IS_ENABLED(DM_MMC)
ae000e23
JJH		 132 return dev_get_priv(mmc->dev);
133#else
134 return (struct omap_hsmmc_data *)mmc->priv;
135#endif
3d673ffc
JJH		 136}
137static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
138{
c4d660d4 139#if CONFIG_IS_ENABLED(DM_MMC)
3d673ffc
JJH		 140 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
141 return &plat->cfg;
142#else
143 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
144#endif
ae000e23
JJH		 145}
146
c4d660d4 147#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
e874d5b0
NK		 148static int omap_mmc_setup_gpio_in(int gpio, const char *label)
149{
5915a2ad 150 int ret;
e874d5b0 151
5915a2ad
SG		 152#ifndef CONFIG_DM_GPIO
153 if (!gpio_is_valid(gpio))
e874d5b0 154 return -1;
5915a2ad
SG		 155#endif
156 ret = gpio_request(gpio, label);
157 if (ret)
158 return ret;
e874d5b0 159
5915a2ad
SG		 160 ret = gpio_direction_input(gpio);
161 if (ret)
162 return ret;
e874d5b0
NK		 163
164 return gpio;
165}
e874d5b0
NK		 166#endif
167
750121c3 168static unsigned char mmc_board_init(struct mmc *mmc)
de941241 169{
de941241 170#if defined(CONFIG_OMAP34XX)
3d673ffc 171 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
de941241
SG		 172 t2_t *t2_base = (t2_t *)T2_BASE;
173 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
b1e725f2 174 u32 pbias_lite;
6aca17c9
AF		 175#ifdef CONFIG_MMC_OMAP36XX_PINS
176 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
177#endif
de941241 178
b1e725f2
GI		 179 pbias_lite = readl(&t2_base->pbias_lite);
180 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
5bfdd1fc
AA		 181#ifdef CONFIG_TARGET_OMAP3_CAIRO
182 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
183 pbias_lite &= ~PBIASLITEVMODE0;
6aca17c9
AF		 184#endif
185#ifdef CONFIG_MMC_OMAP36XX_PINS
186 if (get_cpu_family() == CPU_OMAP36XX) {
187 /* Disable extended drain IO before changing PBIAS */
188 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
189 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
190 }
5bfdd1fc 191#endif
b1e725f2 192 writel(pbias_lite, &t2_base->pbias_lite);
aac5450e 193
b1e725f2 194 writel(pbias_lite | PBIASLITEPWRDNZ1 |
de941241
SG		 195 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
196 &t2_base->pbias_lite);
197
6aca17c9
AF		 198#ifdef CONFIG_MMC_OMAP36XX_PINS
199 if (get_cpu_family() == CPU_OMAP36XX)
200 /* Enable extended drain IO after changing PBIAS */
201 writel(wkup_ctrl |
202 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
203 OMAP34XX_CTRL_WKUP_CTRL);
204#endif
de941241
SG		 205 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
206 &t2_base->devconf0);
207
208 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
209 &t2_base->devconf1);
210
bbbc1ae9 211 /* Change from default of 52MHz to 26MHz if necessary */
3d673ffc 212 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
bbbc1ae9
JS		 213 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
214 &t2_base->ctl_prog_io1);
215
de941241
SG		 216 writel(readl(&prcm_base->fclken1_core) |
217 EN_MMC1 | EN_MMC2 | EN_MMC3,
218 &prcm_base->fclken1_core);
219
220 writel(readl(&prcm_base->iclken1_core) |
221 EN_MMC1 | EN_MMC2 | EN_MMC3,
222 &prcm_base->iclken1_core);
223#endif
224
b4b06006 225#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
14fa2dd0 226 /* PBIAS config needed for MMC1 only */
dc09127a 227 if (mmc_get_blk_desc(mmc)->devnum == 0)
b4b06006 228 vmmc_pbias_config(LDO_VOLT_3V0);
dd23e59d 229#endif
de941241
SG		 230
231 return 0;
232}
233
933efe64 234void mmc_init_stream(struct hsmmc *mmc_base)
de941241 235{
eb9a28f6 236 ulong start;
de941241
SG		 237
238 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
239
240 writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6
NM		 241 start = get_timer(0);
242 while (!(readl(&mmc_base->stat) & CC_MASK)) {
243 if (get_timer(0) - start > MAX_RETRY_MS) {
244 printf("%s: timedout waiting for cc!\n", __func__);
245 return;
246 }
247 }
de941241
SG		 248 writel(CC_MASK, &mmc_base->stat)
249 ;
250 writel(MMC_CMD0, &mmc_base->cmd)
251 ;
eb9a28f6
NM		 252 start = get_timer(0);
253 while (!(readl(&mmc_base->stat) & CC_MASK)) {
254 if (get_timer(0) - start > MAX_RETRY_MS) {
255 printf("%s: timedout waiting for cc2!\n", __func__);
256 return;
257 }
258 }
de941241
SG		 259 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
260}
261
b5944817 262#if CONFIG_IS_ENABLED(DM_MMC)
8fc238bf
JJH		 263static void omap_hsmmc_set_timing(struct mmc *mmc)
264{
265 u32 val;
266 struct hsmmc *mmc_base;
267 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
268
269 mmc_base = priv->base_addr;
270
271 val = readl(&mmc_base->ac12);
272 val &= ~AC12_UHSMC_MASK;
273 priv->mode = mmc->selected_mode;
274
9b3fc218
KVA		 275 if (mmc_is_mode_ddr(priv->mode))
276 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
277 else
278 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
279
8fc238bf
JJH		 280 switch (priv->mode) {
281 case MMC_HS_200:
282 case UHS_SDR104:
283 val |= AC12_UHSMC_SDR104;
284 break;
285 case UHS_SDR50:
286 val |= AC12_UHSMC_SDR50;
287 break;
288 case MMC_DDR_52:
289 case UHS_DDR50:
290 val |= AC12_UHSMC_DDR50;
291 break;
292 case SD_HS:
293 case MMC_HS_52:
294 case UHS_SDR25:
295 val |= AC12_UHSMC_SDR25;
296 break;
297 case MMC_LEGACY:
298 case MMC_HS:
299 case SD_LEGACY:
300 case UHS_SDR12:
301 val |= AC12_UHSMC_SDR12;
302 break;
303 default:
304 val |= AC12_UHSMC_RES;
305 break;
306 }
307 writel(val, &mmc_base->ac12);
308}
309
b5944817
KVA		 310static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
311{
312 struct hsmmc *mmc_base;
313 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
314 u32 val;
315
316 mmc_base = priv->base_addr;
317
318 val = readl(&mmc_base->hctl) & ~SDVS_MASK;
319
320 switch (priv->iov) {
321 case IOV_3V3:
322 val |= SDVS_3V3;
323 break;
324 case IOV_3V0:
325 val |= SDVS_3V0;
326 break;
327 case IOV_1V8:
328 val |= SDVS_1V8;
329 break;
330 }
331
332 writel(val, &mmc_base->hctl);
333}
334
335static void omap_hsmmc_set_capabilities(struct mmc *mmc)
336{
337 struct hsmmc *mmc_base;
338 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
339 u32 val;
340
341 mmc_base = priv->base_addr;
342 val = readl(&mmc_base->capa);
343
344 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
345 val |= (VS30_3V0SUP | VS18_1V8SUP);
346 priv->iov = IOV_3V0;
347 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
348 val |= VS30_3V0SUP;
349 val &= ~VS18_1V8SUP;
350 priv->iov = IOV_3V0;
351 } else {
352 val |= VS18_1V8SUP;
353 val &= ~VS30_3V0SUP;
354 priv->iov = IOV_1V8;
355 }
356
357 writel(val, &mmc_base->capa);
358}
14761cae
JJH		 359
360#ifdef MMC_SUPPORTS_TUNING
361static void omap_hsmmc_disable_tuning(struct mmc *mmc)
362{
363 struct hsmmc *mmc_base;
364 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
365 u32 val;
366
367 mmc_base = priv->base_addr;
368 val = readl(&mmc_base->ac12);
369 val &= ~(AC12_SCLK_SEL);
370 writel(val, &mmc_base->ac12);
371
372 val = readl(&mmc_base->dll);
373 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
374 writel(val, &mmc_base->dll);
375}
376
377static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
378{
379 int i;
380 struct hsmmc *mmc_base;
381 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
382 u32 val;
383
384 mmc_base = priv->base_addr;
385 val = readl(&mmc_base->dll);
386 val |= DLL_FORCE_VALUE;
387 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
388 val |= (count << DLL_FORCE_SR_C_SHIFT);
389 writel(val, &mmc_base->dll);
390
391 val |= DLL_CALIB;
392 writel(val, &mmc_base->dll);
393 for (i = 0; i < 1000; i++) {
394 if (readl(&mmc_base->dll) & DLL_CALIB)
395 break;
396 }
397 val &= ~DLL_CALIB;
398 writel(val, &mmc_base->dll);
399}
400
401static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
402{
403 struct omap_hsmmc_data *priv = dev_get_priv(dev);
404 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
405 struct mmc *mmc = upriv->mmc;
406 struct hsmmc *mmc_base;
407 u32 val;
408 u8 cur_match, prev_match = 0;
409 int ret;
410 u32 phase_delay = 0;
411 u32 start_window = 0, max_window = 0;
412 u32 length = 0, max_len = 0;
413
414 mmc_base = priv->base_addr;
415 val = readl(&mmc_base->capa2);
416
417 /* clock tuning is not needed for upto 52MHz */
418 if (!((mmc->selected_mode == MMC_HS_200) ||
419 (mmc->selected_mode == UHS_SDR104) ||
420 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
421 return 0;
422
423 val = readl(&mmc_base->dll);
424 val |= DLL_SWT;
425 writel(val, &mmc_base->dll);
426 while (phase_delay <= MAX_PHASE_DELAY) {
427 omap_hsmmc_set_dll(mmc, phase_delay);
428
429 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
430
431 if (cur_match) {
432 if (prev_match) {
433 length++;
434 } else {
435 start_window = phase_delay;
436 length = 1;
437 }
438 }
439
440 if (length > max_len) {
441 max_window = start_window;
442 max_len = length;
443 }
444
445 prev_match = cur_match;
446 phase_delay += 4;
447 }
448
449 if (!max_len) {
450 ret = -EIO;
451 goto tuning_error;
452 }
453
454 val = readl(&mmc_base->ac12);
455 if (!(val & AC12_SCLK_SEL)) {
456 ret = -EIO;
457 goto tuning_error;
458 }
459
460 phase_delay = max_window + 4 * ((3 * max_len) >> 2);
461 omap_hsmmc_set_dll(mmc, phase_delay);
462
463 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
464 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
465
466 return 0;
467
468tuning_error:
469
470 omap_hsmmc_disable_tuning(mmc);
471 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
472 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
473
474 return ret;
475}
476#endif
b5944817
KVA		 477#endif
478
ab769f22 479static int omap_hsmmc_init_setup(struct mmc *mmc)
de941241 480{
ae000e23 481 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
cc22b0c0 482 struct hsmmc *mmc_base;
de941241
SG		 483 unsigned int reg_val;
484 unsigned int dsor;
eb9a28f6 485 ulong start;
de941241 486
ae000e23 487 mmc_base = priv->base_addr;
14fa2dd0 488 mmc_board_init(mmc);
de941241
SG		 489
490 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
491 &mmc_base->sysconfig);
eb9a28f6
NM		 492 start = get_timer(0);
493 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
494 if (get_timer(0) - start > MAX_RETRY_MS) {
495 printf("%s: timedout waiting for cc2!\n", __func__);
915ffa52 496 return -ETIMEDOUT;
eb9a28f6
NM		 497 }
498 }
de941241 499 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6
NM		 500 start = get_timer(0);
501 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
502 if (get_timer(0) - start > MAX_RETRY_MS) {
503 printf("%s: timedout waiting for softresetall!\n",
504 __func__);
915ffa52 505 return -ETIMEDOUT;
eb9a28f6
NM		 506 }
507 }
f0d53e88
KVA		 508#ifndef CONFIG_OMAP34XX
509 reg_val = readl(&mmc_base->hl_hwinfo);
510 if (reg_val & MADMA_EN)
511 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
512#endif
b5944817
KVA		 513
514#if CONFIG_IS_ENABLED(DM_MMC)
515 omap_hsmmc_set_capabilities(mmc);
516 omap_hsmmc_conf_bus_power(mmc);
517#else
de941241
SG		 518 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
519 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
520 &mmc_base->capa);
b5944817 521#endif
de941241
SG		 522
523 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
524
525 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
526 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
527 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
528
529 dsor = 240;
530 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
29171dcf 531 (ICE_STOP | DTO_15THDTO));
de941241
SG		 532 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
533 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
eb9a28f6
NM		 534 start = get_timer(0);
535 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
536 if (get_timer(0) - start > MAX_RETRY_MS) {
537 printf("%s: timedout waiting for ics!\n", __func__);
915ffa52 538 return -ETIMEDOUT;
eb9a28f6
NM		 539 }
540 }
de941241
SG		 541 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
542
543 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
544
545 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
f0d53e88
KVA		 546 IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
547 IE_CC, &mmc_base->ie);
de941241
SG		 548
549 mmc_init_stream(mmc_base);
550
551 return 0;
552}
553
25c719e2
GI		 554/*
555 * MMC controller internal finite state machine reset
556 *
557 * Used to reset command or data internal state machines, using respectively
558 * SRC or SRD bit of SYSCTL register
559 */
560static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
561{
562 ulong start;
563
564 mmc_reg_out(&mmc_base->sysctl, bit, bit);
565
61a6cc27
OT		 566 /*
567 * CMD(DAT) lines reset procedures are slightly different
568 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
569 * According to OMAP3 TRM:
570 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
571 * returns to 0x0.
572 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
573 * procedure steps must be as follows:
574 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
575 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
576 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
577 * 3. Wait until the SRC (SRD) bit returns to 0x0
578 * (reset procedure is completed).
579 */
580#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
dce55b93 581 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
61a6cc27
OT		 582 if (!(readl(&mmc_base->sysctl) & bit)) {
583 start = get_timer(0);
584 while (!(readl(&mmc_base->sysctl) & bit)) {
585 if (get_timer(0) - start > MAX_RETRY_MS)
586 return;
587 }
588 }
589#endif
25c719e2
GI		 590 start = get_timer(0);
591 while ((readl(&mmc_base->sysctl) & bit) != 0) {
592 if (get_timer(0) - start > MAX_RETRY_MS) {
593 printf("%s: timedout waiting for sysctl %x to clear\n",
594 __func__, bit);
595 return;
596 }
597 }
598}
f0d53e88
KVA		 599
600#ifndef CONFIG_OMAP34XX
601static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
602{
603 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
604 struct omap_hsmmc_adma_desc *desc;
605 u8 attr;
606
607 desc = &priv->adma_desc_table[priv->desc_slot];
608
609 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
610 if (!end)
611 priv->desc_slot++;
612 else
613 attr |= ADMA_DESC_ATTR_END;
614
615 desc->len = len;
616 desc->addr = (u32)buf;
617 desc->reserved = 0;
618 desc->attr = attr;
619}
620
621static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
622 struct mmc_data *data)
623{
624 uint total_len = data->blocksize * data->blocks;
625 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
626 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
627 int i = desc_count;
628 char *buf;
629
630 priv->desc_slot = 0;
631 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
632 memalign(ARCH_DMA_MINALIGN, desc_count *
633 sizeof(struct omap_hsmmc_adma_desc));
634
635 if (data->flags & MMC_DATA_READ)
636 buf = data->dest;
637 else
638 buf = (char *)data->src;
639
640 while (--i) {
641 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
642 buf += ADMA_MAX_LEN;
643 total_len -= ADMA_MAX_LEN;
644 }
645
646 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
647
648 flush_dcache_range((long)priv->adma_desc_table,
649 (long)priv->adma_desc_table +
650 ROUND(desc_count *
651 sizeof(struct omap_hsmmc_adma_desc),
652 ARCH_DMA_MINALIGN));
653}
654
655static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
656{
657 struct hsmmc *mmc_base;
658 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
659 u32 val;
660 char *buf;
661
662 mmc_base = priv->base_addr;
663 omap_hsmmc_prepare_adma_table(mmc, data);
664
665 if (data->flags & MMC_DATA_READ)
666 buf = data->dest;
667 else
668 buf = (char *)data->src;
669
670 val = readl(&mmc_base->hctl);
671 val |= DMA_SELECT;
672 writel(val, &mmc_base->hctl);
673
674 val = readl(&mmc_base->con);
675 val |= DMA_MASTER;
676 writel(val, &mmc_base->con);
677
678 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
679
680 flush_dcache_range((u32)buf,
681 (u32)buf +
682 ROUND(data->blocksize * data->blocks,
683 ARCH_DMA_MINALIGN));
684}
685
686static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
687{
688 struct hsmmc *mmc_base;
689 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
690 u32 val;
691
692 mmc_base = priv->base_addr;
693
694 val = readl(&mmc_base->con);
695 val &= ~DMA_MASTER;
696 writel(val, &mmc_base->con);
697
698 val = readl(&mmc_base->hctl);
699 val &= ~DMA_SELECT;
700 writel(val, &mmc_base->hctl);
701
702 kfree(priv->adma_desc_table);
703}
704#else
705#define omap_hsmmc_adma_desc
706#define omap_hsmmc_prepare_adma_table
707#define omap_hsmmc_prepare_data
708#define omap_hsmmc_dma_cleanup
709#endif
710
c4d660d4 711#if !CONFIG_IS_ENABLED(DM_MMC)
ab769f22 712static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
de941241
SG		 713 struct mmc_data *data)
714{
ae000e23 715 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
b5511d6c
JJH		 716#else
717static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
718 struct mmc_data *data)
719{
720 struct omap_hsmmc_data *priv = dev_get_priv(dev);
f0d53e88
KVA		 721#ifndef CONFIG_OMAP34XX
722 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
723 struct mmc *mmc = upriv->mmc;
724#endif
b5511d6c 725#endif
cc22b0c0 726 struct hsmmc *mmc_base;
de941241 727 unsigned int flags, mmc_stat;
eb9a28f6 728 ulong start;
de941241 729
ae000e23 730 mmc_base = priv->base_addr;
866bb984
KVA		 731
732 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
733 return 0;
734
eb9a28f6 735 start = get_timer(0);
a7778f8f 736 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
eb9a28f6 737 if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f
TR		 738 printf("%s: timedout waiting on cmd inhibit to clear\n",
739 __func__);
915ffa52 740 return -ETIMEDOUT;
eb9a28f6
NM		 741 }
742 }
de941241 743 writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6
NM		 744 start = get_timer(0);
745 while (readl(&mmc_base->stat)) {
746 if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de
GI		 747 printf("%s: timedout waiting for STAT (%x) to clear\n",
748 __func__, readl(&mmc_base->stat));
915ffa52 749 return -ETIMEDOUT;
eb9a28f6
NM		 750 }
751 }
de941241
SG		 752 /*
753 * CMDREG
754 * CMDIDX[13:8] : Command index
755 * DATAPRNT[5] : Data Present Select
756 * ENCMDIDX[4] : Command Index Check Enable
757 * ENCMDCRC[3] : Command CRC Check Enable
758 * RSPTYP[1:0]
759 * 00 = No Response
760 * 01 = Length 136
761 * 10 = Length 48
762 * 11 = Length 48 Check busy after response
763 */
764 /* Delay added before checking the status of frq change
765 * retry not supported by mmc.c(core file)
766 */
767 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
768 udelay(50000); /* wait 50 ms */
769
770 if (!(cmd->resp_type & MMC_RSP_PRESENT))
771 flags = 0;
772 else if (cmd->resp_type & MMC_RSP_136)
773 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
774 else if (cmd->resp_type & MMC_RSP_BUSY)
775 flags = RSP_TYPE_LGHT48B;
776 else
777 flags = RSP_TYPE_LGHT48;
778
779 /* enable default flags */
780 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
29171dcf
KVA		 781 MSBS_SGLEBLK);
782 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
de941241
SG		 783
784 if (cmd->resp_type & MMC_RSP_CRC)
785 flags |= CCCE_CHECK;
786 if (cmd->resp_type & MMC_RSP_OPCODE)
787 flags |= CICE_CHECK;
788
789 if (data) {
790 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
791 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
866bb984 792 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
de941241
SG		 793 data->blocksize = 512;
794 writel(data->blocksize | (data->blocks << 16),
795 &mmc_base->blk);
796 } else
797 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
798
799 if (data->flags & MMC_DATA_READ)
800 flags |= (DP_DATA | DDIR_READ);
801 else
802 flags |= (DP_DATA | DDIR_WRITE);
f0d53e88
KVA		 803
804#ifndef CONFIG_OMAP34XX
805 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
806 !mmc_is_tuning_cmd(cmd->cmdidx)) {
807 omap_hsmmc_prepare_data(mmc, data);
808 flags |= DE_ENABLE;
809 }
810#endif
de941241
SG		 811 }
812
813 writel(cmd->cmdarg, &mmc_base->arg);
152ba363 814 udelay(20); /* To fix "No status update" error on eMMC */
de941241
SG		 815 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
816
eb9a28f6 817 start = get_timer(0);
de941241
SG		 818 do {
819 mmc_stat = readl(&mmc_base->stat);
f0d53e88 820 if (get_timer(start) > MAX_RETRY_MS) {
eb9a28f6 821 printf("%s : timeout: No status update\n", __func__);
915ffa52 822 return -ETIMEDOUT;
eb9a28f6
NM		 823 }
824 } while (!mmc_stat);
de941241 825
25c719e2
GI		 826 if ((mmc_stat & IE_CTO) != 0) {
827 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
915ffa52 828 return -ETIMEDOUT;
25c719e2 829 } else if ((mmc_stat & ERRI_MASK) != 0)
de941241
SG		 830 return -1;
831
832 if (mmc_stat & CC_MASK) {
833 writel(CC_MASK, &mmc_base->stat);
834 if (cmd->resp_type & MMC_RSP_PRESENT) {
835 if (cmd->resp_type & MMC_RSP_136) {
836 /* response type 2 */
837 cmd->response[3] = readl(&mmc_base->rsp10);
838 cmd->response[2] = readl(&mmc_base->rsp32);
839 cmd->response[1] = readl(&mmc_base->rsp54);
840 cmd->response[0] = readl(&mmc_base->rsp76);
841 } else
842 /* response types 1, 1b, 3, 4, 5, 6 */
843 cmd->response[0] = readl(&mmc_base->rsp10);
844 }
845 }
846
f0d53e88
KVA		 847#ifndef CONFIG_OMAP34XX
848 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
849 !mmc_is_tuning_cmd(cmd->cmdidx)) {
850 u32 sz_mb, timeout;
851
852 if (mmc_stat & IE_ADMAE) {
853 omap_hsmmc_dma_cleanup(mmc);
854 return -EIO;
855 }
856
857 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
858 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
859 if (timeout < MAX_RETRY_MS)
860 timeout = MAX_RETRY_MS;
861
862 start = get_timer(0);
863 do {
864 mmc_stat = readl(&mmc_base->stat);
865 if (mmc_stat & TC_MASK) {
866 writel(readl(&mmc_base->stat) | TC_MASK,
867 &mmc_base->stat);
868 break;
869 }
870 if (get_timer(start) > timeout) {
871 printf("%s : DMA timeout: No status update\n",
872 __func__);
873 return -ETIMEDOUT;
874 }
875 } while (1);
876
877 omap_hsmmc_dma_cleanup(mmc);
878 return 0;
879 }
880#endif
881
de941241
SG		 882 if (data && (data->flags & MMC_DATA_READ)) {
883 mmc_read_data(mmc_base, data->dest,
884 data->blocksize * data->blocks);
885 } else if (data && (data->flags & MMC_DATA_WRITE)) {
886 mmc_write_data(mmc_base, data->src,
887 data->blocksize * data->blocks);
888 }
889 return 0;
890}
891
933efe64 892static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
de941241
SG		 893{
894 unsigned int *output_buf = (unsigned int *)buf;
895 unsigned int mmc_stat;
896 unsigned int count;
897
898 /*
899 * Start Polled Read
900 */
901 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
902 count /= 4;
903
904 while (size) {
eb9a28f6 905 ulong start = get_timer(0);
de941241
SG		 906 do {
907 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 908 if (get_timer(0) - start > MAX_RETRY_MS) {
909 printf("%s: timedout waiting for status!\n",
910 __func__);
915ffa52 911 return -ETIMEDOUT;
eb9a28f6 912 }
de941241
SG		 913 } while (mmc_stat == 0);
914
25c719e2
GI		 915 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
916 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
917
de941241
SG		 918 if ((mmc_stat & ERRI_MASK) != 0)
919 return 1;
920
921 if (mmc_stat & BRR_MASK) {
922 unsigned int k;
923
924 writel(readl(&mmc_base->stat) | BRR_MASK,
925 &mmc_base->stat);
926 for (k = 0; k < count; k++) {
927 *output_buf = readl(&mmc_base->data);
928 output_buf++;
929 }
930 size -= (count*4);
931 }
932
933 if (mmc_stat & BWR_MASK)
934 writel(readl(&mmc_base->stat) | BWR_MASK,
935 &mmc_base->stat);
936
937 if (mmc_stat & TC_MASK) {
938 writel(readl(&mmc_base->stat) | TC_MASK,
939 &mmc_base->stat);
940 break;
941 }
942 }
943 return 0;
944}
945
933efe64
S		 946static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
947 unsigned int size)
de941241
SG		 948{
949 unsigned int *input_buf = (unsigned int *)buf;
950 unsigned int mmc_stat;
951 unsigned int count;
952
953 /*
152ba363 954 * Start Polled Write
de941241
SG		 955 */
956 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
957 count /= 4;
958
959 while (size) {
eb9a28f6 960 ulong start = get_timer(0);
de941241
SG		 961 do {
962 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 963 if (get_timer(0) - start > MAX_RETRY_MS) {
964 printf("%s: timedout waiting for status!\n",
965 __func__);
915ffa52 966 return -ETIMEDOUT;
eb9a28f6 967 }
de941241
SG		 968 } while (mmc_stat == 0);
969
25c719e2
GI		 970 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
971 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
972
de941241
SG		 973 if ((mmc_stat & ERRI_MASK) != 0)
974 return 1;
975
976 if (mmc_stat & BWR_MASK) {
977 unsigned int k;
978
979 writel(readl(&mmc_base->stat) | BWR_MASK,
980 &mmc_base->stat);
981 for (k = 0; k < count; k++) {
982 writel(*input_buf, &mmc_base->data);
983 input_buf++;
984 }
985 size -= (count*4);
986 }
987
988 if (mmc_stat & BRR_MASK)
989 writel(readl(&mmc_base->stat) | BRR_MASK,
990 &mmc_base->stat);
991
992 if (mmc_stat & TC_MASK) {
993 writel(readl(&mmc_base->stat) | TC_MASK,
994 &mmc_base->stat);
995 break;
996 }
997 }
998 return 0;
999}
1000
5baf543e
JJH		 1001static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1002{
1003 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1004}
1005
1006static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1007{
1008 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1009}
1010
1011static void omap_hsmmc_set_clock(struct mmc *mmc)
1012{
1013 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1014 struct hsmmc *mmc_base;
1015 unsigned int dsor = 0;
1016 ulong start;
1017
1018 mmc_base = priv->base_addr;
1019 omap_hsmmc_stop_clock(mmc_base);
1020
1021 /* TODO: Is setting DTO required here? */
1022 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1023 (ICE_STOP | DTO_15THDTO));
1024
1025 if (mmc->clock != 0) {
1026 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1027 if (dsor > CLKD_MAX)
1028 dsor = CLKD_MAX;
1029 } else {
1030 dsor = CLKD_MAX;
1031 }
1032
1033 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1034 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1035
1036 start = get_timer(0);
1037 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1038 if (get_timer(0) - start > MAX_RETRY_MS) {
1039 printf("%s: timedout waiting for ics!\n", __func__);
1040 return;
1041 }
1042 }
1043
1044 priv->clock = mmc->clock;
1045 omap_hsmmc_start_clock(mmc_base);
1046}
1047
48a2f114 1048static void omap_hsmmc_set_bus_width(struct mmc *mmc)
de941241 1049{
ae000e23 1050 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
cc22b0c0 1051 struct hsmmc *mmc_base;
de941241 1052
ae000e23 1053 mmc_base = priv->base_addr;
de941241
SG		 1054 /* configue bus width */
1055 switch (mmc->bus_width) {
1056 case 8:
1057 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1058 &mmc_base->con);
1059 break;
1060
1061 case 4:
1062 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1063 &mmc_base->con);
1064 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1065 &mmc_base->hctl);
1066 break;
1067
1068 case 1:
1069 default:
1070 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1071 &mmc_base->con);
1072 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1073 &mmc_base->hctl);
1074 break;
1075 }
1076
48a2f114
KVA		 1077 priv->bus_width = mmc->bus_width;
1078}
1079
1080#if !CONFIG_IS_ENABLED(DM_MMC)
1081static int omap_hsmmc_set_ios(struct mmc *mmc)
1082{
1083 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1084#else
1085static int omap_hsmmc_set_ios(struct udevice *dev)
1086{
1087 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1088 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1089 struct mmc *mmc = upriv->mmc;
1090#endif
1091
1092 if (priv->bus_width != mmc->bus_width)
1093 omap_hsmmc_set_bus_width(mmc);
1094
5baf543e
JJH		 1095 if (priv->clock != mmc->clock)
1096 omap_hsmmc_set_clock(mmc);
07b0b9c0 1097
8fc238bf
JJH		 1098#if CONFIG_IS_ENABLED(DM_MMC)
1099 if (priv->mode != mmc->selected_mode)
1100 omap_hsmmc_set_timing(mmc);
1101#endif
07b0b9c0 1102 return 0;
de941241
SG		 1103}
1104
ab769f22 1105#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 1106#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c 1107static int omap_hsmmc_getcd(struct udevice *dev)
a9d6a7e2 1108{
b5511d6c 1109 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 1110 int value;
1111
1112 value = dm_gpio_get_value(&priv->cd_gpio);
1113 /* if no CD return as 1 */
1114 if (value < 0)
1115 return 1;
1116
1117 if (priv->cd_inverted)
1118 return !value;
1119 return value;
1120}
1121
b5511d6c 1122static int omap_hsmmc_getwp(struct udevice *dev)
a9d6a7e2 1123{
b5511d6c 1124 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 1125 int value;
1126
1127 value = dm_gpio_get_value(&priv->wp_gpio);
1128 /* if no WP return as 0 */
1129 if (value < 0)
1130 return 0;
1131 return value;
1132}
1133#else
ab769f22
PA		 1134static int omap_hsmmc_getcd(struct mmc *mmc)
1135{
ae000e23 1136 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 1137 int cd_gpio;
1138
1139 /* if no CD return as 1 */
ae000e23 1140 cd_gpio = priv->cd_gpio;
ab769f22
PA		 1141 if (cd_gpio < 0)
1142 return 1;
1143
0b03a931
IG		 1144 /* NOTE: assumes card detect signal is active-low */
1145 return !gpio_get_value(cd_gpio);
ab769f22
PA		 1146}
1147
1148static int omap_hsmmc_getwp(struct mmc *mmc)
1149{
ae000e23 1150 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 1151 int wp_gpio;
1152
1153 /* if no WP return as 0 */
ae000e23 1154 wp_gpio = priv->wp_gpio;
ab769f22
PA		 1155 if (wp_gpio < 0)
1156 return 0;
1157
0b03a931 1158 /* NOTE: assumes write protect signal is active-high */
ab769f22
PA		 1159 return gpio_get_value(wp_gpio);
1160}
1161#endif
a9d6a7e2 1162#endif
ab769f22 1163
c4d660d4 1164#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c
JJH		 1165static const struct dm_mmc_ops omap_hsmmc_ops = {
1166 .send_cmd = omap_hsmmc_send_cmd,
1167 .set_ios = omap_hsmmc_set_ios,
1168#ifdef OMAP_HSMMC_USE_GPIO
1169 .get_cd = omap_hsmmc_getcd,
1170 .get_wp = omap_hsmmc_getwp,
1171#endif
14761cae
JJH		 1172#ifdef MMC_SUPPORTS_TUNING
1173 .execute_tuning = omap_hsmmc_execute_tuning,
1174#endif
b5511d6c
JJH		 1175};
1176#else
ab769f22
PA		 1177static const struct mmc_ops omap_hsmmc_ops = {
1178 .send_cmd = omap_hsmmc_send_cmd,
1179 .set_ios = omap_hsmmc_set_ios,
1180 .init = omap_hsmmc_init_setup,
1181#ifdef OMAP_HSMMC_USE_GPIO
1182 .getcd = omap_hsmmc_getcd,
1183 .getwp = omap_hsmmc_getwp,
1184#endif
1185};
b5511d6c 1186#endif
ab769f22 1187
c4d660d4 1188#if !CONFIG_IS_ENABLED(DM_MMC)
e3913f56
NK		 1189int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1190 int wp_gpio)
de941241 1191{
93bfd616 1192 struct mmc *mmc;
ae000e23 1193 struct omap_hsmmc_data *priv;
93bfd616
PA		 1194 struct mmc_config *cfg;
1195 uint host_caps_val;
1196
ae000e23
JJH		 1197 priv = malloc(sizeof(*priv));
1198 if (priv == NULL)
93bfd616 1199 return -1;
de941241 1200
5a20397b 1201 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
de941241
SG		 1202
1203 switch (dev_index) {
1204 case 0:
ae000e23 1205 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 1206 break;
1037d585 1207#ifdef OMAP_HSMMC2_BASE
de941241 1208 case 1:
ae000e23 1209 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
152ba363 1210#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
3891a54f 1211 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
3b68939f
RQ		 1212 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1213 defined(CONFIG_HSMMC2_8BIT)
152ba363
LP		 1214 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1215 host_caps_val |= MMC_MODE_8BIT;
1216#endif
de941241 1217 break;
1037d585
TR		 1218#endif
1219#ifdef OMAP_HSMMC3_BASE
de941241 1220 case 2:
ae000e23 1221 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
3891a54f 1222#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
152ba363
LP		 1223 /* Enable 8-bit interface for eMMC on DRA7XX */
1224 host_caps_val |= MMC_MODE_8BIT;
1225#endif
de941241 1226 break;
1037d585 1227#endif
de941241 1228 default:
ae000e23 1229 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241
SG		 1230 return 1;
1231 }
ab769f22
PA		 1232#ifdef OMAP_HSMMC_USE_GPIO
1233 /* on error gpio values are set to -1, which is what we want */
ae000e23
JJH		 1234 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1235 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
ab769f22 1236#endif
173ddc5b 1237
ae000e23 1238 cfg = &priv->cfg;
de941241 1239
93bfd616
PA		 1240 cfg->name = "OMAP SD/MMC";
1241 cfg->ops = &omap_hsmmc_ops;
1242
1243 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1244 cfg->host_caps = host_caps_val & ~host_caps_mask;
1245
1246 cfg->f_min = 400000;
bbbc1ae9
JS		 1247
1248 if (f_max != 0)
93bfd616 1249 cfg->f_max = f_max;
bbbc1ae9 1250 else {
93bfd616
PA		 1251 if (cfg->host_caps & MMC_MODE_HS) {
1252 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1253 cfg->f_max = 52000000;
bbbc1ae9 1254 else
93bfd616 1255 cfg->f_max = 26000000;
bbbc1ae9 1256 } else
93bfd616 1257 cfg->f_max = 20000000;
bbbc1ae9 1258 }
de941241 1259
93bfd616 1260 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
8feafcc4 1261
4ca9244d
JR		 1262#if defined(CONFIG_OMAP34XX)
1263 /*
1264 * Silicon revs 2.1 and older do not support multiblock transfers.
1265 */
1266 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
93bfd616 1267 cfg->b_max = 1;
4ca9244d 1268#endif
ae000e23 1269 mmc = mmc_create(cfg, priv);
93bfd616
PA		 1270 if (mmc == NULL)
1271 return -1;
de941241
SG		 1272
1273 return 0;
1274}
a9d6a7e2 1275#else
2558c049 1276#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 1277static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1278{
3d673ffc
JJH		 1279 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1280 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2 1281 const void *fdt = gd->fdt_blob;
e160f7d4 1282 int node = dev_of_offset(dev);
a9d6a7e2
M		 1283 int val;
1284
a821c4af
SG		 1285 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1286 sizeof(struct hsmmc *),
741726ae 1287 MAP_NOCACHE);
a9d6a7e2
M		 1288
1289 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1290 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1291 if (val < 0) {
1292 printf("error: bus-width property missing\n");
1293 return -ENOENT;
1294 }
1295
1296 switch (val) {
1297 case 0x8:
1298 cfg->host_caps |= MMC_MODE_8BIT;
1299 case 0x4:
1300 cfg->host_caps |= MMC_MODE_4BIT;
1301 break;
1302 default:
1303 printf("error: invalid bus-width property\n");
1304 return -ENOENT;
1305 }
1306
1307 cfg->f_min = 400000;
1308 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1309 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1310 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
b5944817
KVA		 1311 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1312 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1313 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1314 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
a9d6a7e2 1315
4de2de51 1316#ifdef OMAP_HSMMC_USE_GPIO
2558c049 1317 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
4de2de51 1318#endif
a9d6a7e2
M		 1319
1320 return 0;
1321}
2558c049 1322#endif
a9d6a7e2 1323
17c9a1c1
JJH		 1324#ifdef CONFIG_BLK
1325
1326static int omap_hsmmc_bind(struct udevice *dev)
1327{
1328 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1329
1330 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1331}
1332#endif
a9d6a7e2
M		 1333static int omap_hsmmc_probe(struct udevice *dev)
1334{
3d673ffc 1335 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
a9d6a7e2
M		 1336 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1337 struct omap_hsmmc_data *priv = dev_get_priv(dev);
3d673ffc 1338 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2
M		 1339 struct mmc *mmc;
1340
a9d6a7e2 1341 cfg->name = "OMAP SD/MMC";
2558c049
LV		 1342 priv->base_addr = plat->base_addr;
1343#ifdef OMAP_HSMMC_USE_GPIO
1344 priv->cd_inverted = plat->cd_inverted;
1345#endif
a9d6a7e2 1346
17c9a1c1
JJH		 1347#ifdef CONFIG_BLK
1348 mmc = &plat->mmc;
1349#else
a9d6a7e2
M		 1350 mmc = mmc_create(cfg, priv);
1351 if (mmc == NULL)
1352 return -1;
17c9a1c1 1353#endif
a9d6a7e2 1354
2558c049 1355#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
5cc6a245
M		 1356 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1357 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1358#endif
1359
cffe5d86 1360 mmc->dev = dev;
a9d6a7e2
M		 1361 upriv->mmc = mmc;
1362
b5511d6c 1363 return omap_hsmmc_init_setup(mmc);
a9d6a7e2
M		 1364}
1365
2558c049 1366#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2 1367static const struct udevice_id omap_hsmmc_ids[] = {
741726ae
JJH		 1368 { .compatible = "ti,omap3-hsmmc" },
1369 { .compatible = "ti,omap4-hsmmc" },
1370 { .compatible = "ti,am33xx-hsmmc" },
a9d6a7e2
M		 1371 { }
1372};
2558c049 1373#endif
a9d6a7e2
M		 1374
1375U_BOOT_DRIVER(omap_hsmmc) = {
1376 .name = "omap_hsmmc",
1377 .id = UCLASS_MMC,
2558c049 1378#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 1379 .of_match = omap_hsmmc_ids,
1380 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2558c049
LV		 1381 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1382#endif
17c9a1c1
JJH		 1383#ifdef CONFIG_BLK
1384 .bind = omap_hsmmc_bind,
1385#endif
b5511d6c 1386 .ops = &omap_hsmmc_ops,
a9d6a7e2
M		 1387 .probe = omap_hsmmc_probe,
1388 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
cbcb1701 1389 .flags = DM_FLAG_PRE_RELOC,
a9d6a7e2
M		 1390};
1391#endif
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