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mmc: omap_hsmmc: cleanup omap_hsmmc_set_ios
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
CommitLineData
de941241
SG		 1/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
93bfd616 27#include <malloc.h>
f0d53e88 28#include <memalign.h>
de941241
SG		 29#include <mmc.h>
30#include <part.h>
31#include <i2c.h>
339d5789 32#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
cb199102 33#include <palmas.h>
339d5789 34#endif
de941241
SG		 35#include <asm/io.h>
36#include <asm/arch/mmc_host_def.h>
3b68939f
RQ		 37#if !defined(CONFIG_SOC_KEYSTONE)
38#include <asm/gpio.h>
96e0e7b3 39#include <asm/arch/sys_proto.h>
3b68939f 40#endif
2a48b3a2
TR		 41#ifdef CONFIG_MMC_OMAP36XX_PINS
42#include <asm/arch/mux.h>
43#endif
a9d6a7e2
M		 44#include <dm.h>
45
46DECLARE_GLOBAL_DATA_PTR;
de941241 47
ab769f22
PA		 48/* simplify defines to OMAP_HSMMC_USE_GPIO */
49#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51#define OMAP_HSMMC_USE_GPIO
52#else
53#undef OMAP_HSMMC_USE_GPIO
54#endif
55
25c719e2
GI		 56/* common definitions for all OMAPs */
57#define SYSCTL_SRC (1 << 25)
58#define SYSCTL_SRD (1 << 26)
59
cc22b0c0
NK		 60struct omap_hsmmc_data {
61 struct hsmmc *base_addr;
c4d660d4 62#if !CONFIG_IS_ENABLED(DM_MMC)
93bfd616 63 struct mmc_config cfg;
3d673ffc 64#endif
48a2f114 65 uint bus_width;
5baf543e 66 uint clock;
ab769f22 67#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 68#if CONFIG_IS_ENABLED(DM_MMC)
a9d6a7e2
M		 69 struct gpio_desc cd_gpio; /* Change Detect GPIO */
70 struct gpio_desc wp_gpio; /* Write Protect GPIO */
71 bool cd_inverted;
72#else
e874d5b0 73 int cd_gpio;
e3913f56 74 int wp_gpio;
ab769f22 75#endif
a9d6a7e2 76#endif
f0d53e88
KVA		 77 u8 controller_flags;
78#ifndef CONFIG_OMAP34XX
79 struct omap_hsmmc_adma_desc *adma_desc_table;
80 uint desc_slot;
81#endif
82};
83
84#ifndef CONFIG_OMAP34XX
85struct omap_hsmmc_adma_desc {
86 u8 attr;
87 u8 reserved;
88 u16 len;
89 u32 addr;
cc22b0c0
NK		 90};
91
f0d53e88
KVA		 92#define ADMA_MAX_LEN 63488
93
94/* Decriptor table defines */
95#define ADMA_DESC_ATTR_VALID BIT(0)
96#define ADMA_DESC_ATTR_END BIT(1)
97#define ADMA_DESC_ATTR_INT BIT(2)
98#define ADMA_DESC_ATTR_ACT1 BIT(4)
99#define ADMA_DESC_ATTR_ACT2 BIT(5)
100
101#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
102#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
103#endif
104
eb9a28f6
NM		 105/* If we fail after 1 second wait, something is really bad */
106#define MAX_RETRY_MS 1000
107
f0d53e88
KVA		 108/* DMA transfers can take a long time if a lot a data is transferred.
109 * The timeout must take in account the amount of data. Let's assume
110 * that the time will never exceed 333 ms per MB (in other word we assume
111 * that the bandwidth is always above 3MB/s).
112 */
113#define DMA_TIMEOUT_PER_MB 333
114#define OMAP_HSMMC_USE_ADMA BIT(2)
115
933efe64
S		 116static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
117static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
118 unsigned int siz);
5baf543e
JJH		 119static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
120static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
14fa2dd0 121
ae000e23
JJH		 122static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
123{
c4d660d4 124#if CONFIG_IS_ENABLED(DM_MMC)
ae000e23
JJH		 125 return dev_get_priv(mmc->dev);
126#else
127 return (struct omap_hsmmc_data *)mmc->priv;
128#endif
3d673ffc
JJH		 129}
130static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
131{
c4d660d4 132#if CONFIG_IS_ENABLED(DM_MMC)
3d673ffc
JJH		 133 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
134 return &plat->cfg;
135#else
136 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
137#endif
ae000e23
JJH		 138}
139
c4d660d4 140#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
e874d5b0
NK		 141static int omap_mmc_setup_gpio_in(int gpio, const char *label)
142{
5915a2ad 143 int ret;
e874d5b0 144
5915a2ad
SG		 145#ifndef CONFIG_DM_GPIO
146 if (!gpio_is_valid(gpio))
e874d5b0 147 return -1;
5915a2ad
SG		 148#endif
149 ret = gpio_request(gpio, label);
150 if (ret)
151 return ret;
e874d5b0 152
5915a2ad
SG		 153 ret = gpio_direction_input(gpio);
154 if (ret)
155 return ret;
e874d5b0
NK		 156
157 return gpio;
158}
e874d5b0
NK		 159#endif
160
750121c3 161static unsigned char mmc_board_init(struct mmc *mmc)
de941241 162{
de941241 163#if defined(CONFIG_OMAP34XX)
3d673ffc 164 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
de941241
SG		 165 t2_t *t2_base = (t2_t *)T2_BASE;
166 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
b1e725f2 167 u32 pbias_lite;
6aca17c9
AF		 168#ifdef CONFIG_MMC_OMAP36XX_PINS
169 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
170#endif
de941241 171
b1e725f2
GI		 172 pbias_lite = readl(&t2_base->pbias_lite);
173 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
5bfdd1fc
AA		 174#ifdef CONFIG_TARGET_OMAP3_CAIRO
175 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
176 pbias_lite &= ~PBIASLITEVMODE0;
6aca17c9
AF		 177#endif
178#ifdef CONFIG_MMC_OMAP36XX_PINS
179 if (get_cpu_family() == CPU_OMAP36XX) {
180 /* Disable extended drain IO before changing PBIAS */
181 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
182 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
183 }
5bfdd1fc 184#endif
b1e725f2 185 writel(pbias_lite, &t2_base->pbias_lite);
aac5450e 186
b1e725f2 187 writel(pbias_lite | PBIASLITEPWRDNZ1 |
de941241
SG		 188 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
189 &t2_base->pbias_lite);
190
6aca17c9
AF		 191#ifdef CONFIG_MMC_OMAP36XX_PINS
192 if (get_cpu_family() == CPU_OMAP36XX)
193 /* Enable extended drain IO after changing PBIAS */
194 writel(wkup_ctrl |
195 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
196 OMAP34XX_CTRL_WKUP_CTRL);
197#endif
de941241
SG		 198 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
199 &t2_base->devconf0);
200
201 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
202 &t2_base->devconf1);
203
bbbc1ae9 204 /* Change from default of 52MHz to 26MHz if necessary */
3d673ffc 205 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
bbbc1ae9
JS		 206 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
207 &t2_base->ctl_prog_io1);
208
de941241
SG		 209 writel(readl(&prcm_base->fclken1_core) |
210 EN_MMC1 | EN_MMC2 | EN_MMC3,
211 &prcm_base->fclken1_core);
212
213 writel(readl(&prcm_base->iclken1_core) |
214 EN_MMC1 | EN_MMC2 | EN_MMC3,
215 &prcm_base->iclken1_core);
216#endif
217
b4b06006 218#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
14fa2dd0 219 /* PBIAS config needed for MMC1 only */
dc09127a 220 if (mmc_get_blk_desc(mmc)->devnum == 0)
b4b06006 221 vmmc_pbias_config(LDO_VOLT_3V0);
dd23e59d 222#endif
de941241
SG		 223
224 return 0;
225}
226
933efe64 227void mmc_init_stream(struct hsmmc *mmc_base)
de941241 228{
eb9a28f6 229 ulong start;
de941241
SG		 230
231 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
232
233 writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6
NM		 234 start = get_timer(0);
235 while (!(readl(&mmc_base->stat) & CC_MASK)) {
236 if (get_timer(0) - start > MAX_RETRY_MS) {
237 printf("%s: timedout waiting for cc!\n", __func__);
238 return;
239 }
240 }
de941241
SG		 241 writel(CC_MASK, &mmc_base->stat)
242 ;
243 writel(MMC_CMD0, &mmc_base->cmd)
244 ;
eb9a28f6
NM		 245 start = get_timer(0);
246 while (!(readl(&mmc_base->stat) & CC_MASK)) {
247 if (get_timer(0) - start > MAX_RETRY_MS) {
248 printf("%s: timedout waiting for cc2!\n", __func__);
249 return;
250 }
251 }
de941241
SG		 252 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
253}
254
ab769f22 255static int omap_hsmmc_init_setup(struct mmc *mmc)
de941241 256{
ae000e23 257 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
cc22b0c0 258 struct hsmmc *mmc_base;
de941241
SG		 259 unsigned int reg_val;
260 unsigned int dsor;
eb9a28f6 261 ulong start;
de941241 262
ae000e23 263 mmc_base = priv->base_addr;
14fa2dd0 264 mmc_board_init(mmc);
de941241
SG		 265
266 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
267 &mmc_base->sysconfig);
eb9a28f6
NM		 268 start = get_timer(0);
269 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
270 if (get_timer(0) - start > MAX_RETRY_MS) {
271 printf("%s: timedout waiting for cc2!\n", __func__);
915ffa52 272 return -ETIMEDOUT;
eb9a28f6
NM		 273 }
274 }
de941241 275 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6
NM		 276 start = get_timer(0);
277 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
278 if (get_timer(0) - start > MAX_RETRY_MS) {
279 printf("%s: timedout waiting for softresetall!\n",
280 __func__);
915ffa52 281 return -ETIMEDOUT;
eb9a28f6
NM		 282 }
283 }
f0d53e88
KVA		 284#ifndef CONFIG_OMAP34XX
285 reg_val = readl(&mmc_base->hl_hwinfo);
286 if (reg_val & MADMA_EN)
287 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
288#endif
de941241
SG		 289 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
290 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
291 &mmc_base->capa);
292
293 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
294
295 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
296 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
297 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
298
299 dsor = 240;
300 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
29171dcf 301 (ICE_STOP | DTO_15THDTO));
de941241
SG		 302 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
303 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
eb9a28f6
NM		 304 start = get_timer(0);
305 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
306 if (get_timer(0) - start > MAX_RETRY_MS) {
307 printf("%s: timedout waiting for ics!\n", __func__);
915ffa52 308 return -ETIMEDOUT;
eb9a28f6
NM		 309 }
310 }
de941241
SG		 311 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
312
313 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
314
315 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
f0d53e88
KVA		 316 IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
317 IE_CC, &mmc_base->ie);
de941241
SG		 318
319 mmc_init_stream(mmc_base);
320
321 return 0;
322}
323
25c719e2
GI		 324/*
325 * MMC controller internal finite state machine reset
326 *
327 * Used to reset command or data internal state machines, using respectively
328 * SRC or SRD bit of SYSCTL register
329 */
330static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
331{
332 ulong start;
333
334 mmc_reg_out(&mmc_base->sysctl, bit, bit);
335
61a6cc27
OT		 336 /*
337 * CMD(DAT) lines reset procedures are slightly different
338 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
339 * According to OMAP3 TRM:
340 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
341 * returns to 0x0.
342 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
343 * procedure steps must be as follows:
344 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
345 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
346 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
347 * 3. Wait until the SRC (SRD) bit returns to 0x0
348 * (reset procedure is completed).
349 */
350#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
dce55b93 351 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
61a6cc27
OT		 352 if (!(readl(&mmc_base->sysctl) & bit)) {
353 start = get_timer(0);
354 while (!(readl(&mmc_base->sysctl) & bit)) {
355 if (get_timer(0) - start > MAX_RETRY_MS)
356 return;
357 }
358 }
359#endif
25c719e2
GI		 360 start = get_timer(0);
361 while ((readl(&mmc_base->sysctl) & bit) != 0) {
362 if (get_timer(0) - start > MAX_RETRY_MS) {
363 printf("%s: timedout waiting for sysctl %x to clear\n",
364 __func__, bit);
365 return;
366 }
367 }
368}
f0d53e88
KVA		 369
370#ifndef CONFIG_OMAP34XX
371static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
372{
373 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
374 struct omap_hsmmc_adma_desc *desc;
375 u8 attr;
376
377 desc = &priv->adma_desc_table[priv->desc_slot];
378
379 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
380 if (!end)
381 priv->desc_slot++;
382 else
383 attr |= ADMA_DESC_ATTR_END;
384
385 desc->len = len;
386 desc->addr = (u32)buf;
387 desc->reserved = 0;
388 desc->attr = attr;
389}
390
391static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
392 struct mmc_data *data)
393{
394 uint total_len = data->blocksize * data->blocks;
395 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
396 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
397 int i = desc_count;
398 char *buf;
399
400 priv->desc_slot = 0;
401 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
402 memalign(ARCH_DMA_MINALIGN, desc_count *
403 sizeof(struct omap_hsmmc_adma_desc));
404
405 if (data->flags & MMC_DATA_READ)
406 buf = data->dest;
407 else
408 buf = (char *)data->src;
409
410 while (--i) {
411 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
412 buf += ADMA_MAX_LEN;
413 total_len -= ADMA_MAX_LEN;
414 }
415
416 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
417
418 flush_dcache_range((long)priv->adma_desc_table,
419 (long)priv->adma_desc_table +
420 ROUND(desc_count *
421 sizeof(struct omap_hsmmc_adma_desc),
422 ARCH_DMA_MINALIGN));
423}
424
425static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
426{
427 struct hsmmc *mmc_base;
428 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
429 u32 val;
430 char *buf;
431
432 mmc_base = priv->base_addr;
433 omap_hsmmc_prepare_adma_table(mmc, data);
434
435 if (data->flags & MMC_DATA_READ)
436 buf = data->dest;
437 else
438 buf = (char *)data->src;
439
440 val = readl(&mmc_base->hctl);
441 val |= DMA_SELECT;
442 writel(val, &mmc_base->hctl);
443
444 val = readl(&mmc_base->con);
445 val |= DMA_MASTER;
446 writel(val, &mmc_base->con);
447
448 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
449
450 flush_dcache_range((u32)buf,
451 (u32)buf +
452 ROUND(data->blocksize * data->blocks,
453 ARCH_DMA_MINALIGN));
454}
455
456static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
457{
458 struct hsmmc *mmc_base;
459 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
460 u32 val;
461
462 mmc_base = priv->base_addr;
463
464 val = readl(&mmc_base->con);
465 val &= ~DMA_MASTER;
466 writel(val, &mmc_base->con);
467
468 val = readl(&mmc_base->hctl);
469 val &= ~DMA_SELECT;
470 writel(val, &mmc_base->hctl);
471
472 kfree(priv->adma_desc_table);
473}
474#else
475#define omap_hsmmc_adma_desc
476#define omap_hsmmc_prepare_adma_table
477#define omap_hsmmc_prepare_data
478#define omap_hsmmc_dma_cleanup
479#endif
480
c4d660d4 481#if !CONFIG_IS_ENABLED(DM_MMC)
ab769f22 482static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
de941241
SG		 483 struct mmc_data *data)
484{
ae000e23 485 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
b5511d6c
JJH		 486#else
487static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
488 struct mmc_data *data)
489{
490 struct omap_hsmmc_data *priv = dev_get_priv(dev);
f0d53e88
KVA		 491#ifndef CONFIG_OMAP34XX
492 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
493 struct mmc *mmc = upriv->mmc;
494#endif
b5511d6c 495#endif
cc22b0c0 496 struct hsmmc *mmc_base;
de941241 497 unsigned int flags, mmc_stat;
eb9a28f6 498 ulong start;
de941241 499
ae000e23 500 mmc_base = priv->base_addr;
866bb984
KVA		 501
502 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
503 return 0;
504
eb9a28f6 505 start = get_timer(0);
a7778f8f 506 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
eb9a28f6 507 if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f
TR		 508 printf("%s: timedout waiting on cmd inhibit to clear\n",
509 __func__);
915ffa52 510 return -ETIMEDOUT;
eb9a28f6
NM		 511 }
512 }
de941241 513 writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6
NM		 514 start = get_timer(0);
515 while (readl(&mmc_base->stat)) {
516 if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de
GI		 517 printf("%s: timedout waiting for STAT (%x) to clear\n",
518 __func__, readl(&mmc_base->stat));
915ffa52 519 return -ETIMEDOUT;
eb9a28f6
NM		 520 }
521 }
de941241
SG		 522 /*
523 * CMDREG
524 * CMDIDX[13:8] : Command index
525 * DATAPRNT[5] : Data Present Select
526 * ENCMDIDX[4] : Command Index Check Enable
527 * ENCMDCRC[3] : Command CRC Check Enable
528 * RSPTYP[1:0]
529 * 00 = No Response
530 * 01 = Length 136
531 * 10 = Length 48
532 * 11 = Length 48 Check busy after response
533 */
534 /* Delay added before checking the status of frq change
535 * retry not supported by mmc.c(core file)
536 */
537 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
538 udelay(50000); /* wait 50 ms */
539
540 if (!(cmd->resp_type & MMC_RSP_PRESENT))
541 flags = 0;
542 else if (cmd->resp_type & MMC_RSP_136)
543 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
544 else if (cmd->resp_type & MMC_RSP_BUSY)
545 flags = RSP_TYPE_LGHT48B;
546 else
547 flags = RSP_TYPE_LGHT48;
548
549 /* enable default flags */
550 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
29171dcf
KVA		 551 MSBS_SGLEBLK);
552 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
de941241
SG		 553
554 if (cmd->resp_type & MMC_RSP_CRC)
555 flags |= CCCE_CHECK;
556 if (cmd->resp_type & MMC_RSP_OPCODE)
557 flags |= CICE_CHECK;
558
559 if (data) {
560 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
561 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
866bb984 562 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
de941241
SG		 563 data->blocksize = 512;
564 writel(data->blocksize | (data->blocks << 16),
565 &mmc_base->blk);
566 } else
567 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
568
569 if (data->flags & MMC_DATA_READ)
570 flags |= (DP_DATA | DDIR_READ);
571 else
572 flags |= (DP_DATA | DDIR_WRITE);
f0d53e88
KVA		 573
574#ifndef CONFIG_OMAP34XX
575 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
576 !mmc_is_tuning_cmd(cmd->cmdidx)) {
577 omap_hsmmc_prepare_data(mmc, data);
578 flags |= DE_ENABLE;
579 }
580#endif
de941241
SG		 581 }
582
583 writel(cmd->cmdarg, &mmc_base->arg);
152ba363 584 udelay(20); /* To fix "No status update" error on eMMC */
de941241
SG		 585 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
586
eb9a28f6 587 start = get_timer(0);
de941241
SG		 588 do {
589 mmc_stat = readl(&mmc_base->stat);
f0d53e88 590 if (get_timer(start) > MAX_RETRY_MS) {
eb9a28f6 591 printf("%s : timeout: No status update\n", __func__);
915ffa52 592 return -ETIMEDOUT;
eb9a28f6
NM		 593 }
594 } while (!mmc_stat);
de941241 595
25c719e2
GI		 596 if ((mmc_stat & IE_CTO) != 0) {
597 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
915ffa52 598 return -ETIMEDOUT;
25c719e2 599 } else if ((mmc_stat & ERRI_MASK) != 0)
de941241
SG		 600 return -1;
601
602 if (mmc_stat & CC_MASK) {
603 writel(CC_MASK, &mmc_base->stat);
604 if (cmd->resp_type & MMC_RSP_PRESENT) {
605 if (cmd->resp_type & MMC_RSP_136) {
606 /* response type 2 */
607 cmd->response[3] = readl(&mmc_base->rsp10);
608 cmd->response[2] = readl(&mmc_base->rsp32);
609 cmd->response[1] = readl(&mmc_base->rsp54);
610 cmd->response[0] = readl(&mmc_base->rsp76);
611 } else
612 /* response types 1, 1b, 3, 4, 5, 6 */
613 cmd->response[0] = readl(&mmc_base->rsp10);
614 }
615 }
616
f0d53e88
KVA		 617#ifndef CONFIG_OMAP34XX
618 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
619 !mmc_is_tuning_cmd(cmd->cmdidx)) {
620 u32 sz_mb, timeout;
621
622 if (mmc_stat & IE_ADMAE) {
623 omap_hsmmc_dma_cleanup(mmc);
624 return -EIO;
625 }
626
627 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
628 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
629 if (timeout < MAX_RETRY_MS)
630 timeout = MAX_RETRY_MS;
631
632 start = get_timer(0);
633 do {
634 mmc_stat = readl(&mmc_base->stat);
635 if (mmc_stat & TC_MASK) {
636 writel(readl(&mmc_base->stat) | TC_MASK,
637 &mmc_base->stat);
638 break;
639 }
640 if (get_timer(start) > timeout) {
641 printf("%s : DMA timeout: No status update\n",
642 __func__);
643 return -ETIMEDOUT;
644 }
645 } while (1);
646
647 omap_hsmmc_dma_cleanup(mmc);
648 return 0;
649 }
650#endif
651
de941241
SG		 652 if (data && (data->flags & MMC_DATA_READ)) {
653 mmc_read_data(mmc_base, data->dest,
654 data->blocksize * data->blocks);
655 } else if (data && (data->flags & MMC_DATA_WRITE)) {
656 mmc_write_data(mmc_base, data->src,
657 data->blocksize * data->blocks);
658 }
659 return 0;
660}
661
933efe64 662static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
de941241
SG		 663{
664 unsigned int *output_buf = (unsigned int *)buf;
665 unsigned int mmc_stat;
666 unsigned int count;
667
668 /*
669 * Start Polled Read
670 */
671 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
672 count /= 4;
673
674 while (size) {
eb9a28f6 675 ulong start = get_timer(0);
de941241
SG		 676 do {
677 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 678 if (get_timer(0) - start > MAX_RETRY_MS) {
679 printf("%s: timedout waiting for status!\n",
680 __func__);
915ffa52 681 return -ETIMEDOUT;
eb9a28f6 682 }
de941241
SG		 683 } while (mmc_stat == 0);
684
25c719e2
GI		 685 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
686 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
687
de941241
SG		 688 if ((mmc_stat & ERRI_MASK) != 0)
689 return 1;
690
691 if (mmc_stat & BRR_MASK) {
692 unsigned int k;
693
694 writel(readl(&mmc_base->stat) | BRR_MASK,
695 &mmc_base->stat);
696 for (k = 0; k < count; k++) {
697 *output_buf = readl(&mmc_base->data);
698 output_buf++;
699 }
700 size -= (count*4);
701 }
702
703 if (mmc_stat & BWR_MASK)
704 writel(readl(&mmc_base->stat) | BWR_MASK,
705 &mmc_base->stat);
706
707 if (mmc_stat & TC_MASK) {
708 writel(readl(&mmc_base->stat) | TC_MASK,
709 &mmc_base->stat);
710 break;
711 }
712 }
713 return 0;
714}
715
933efe64
S		 716static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
717 unsigned int size)
de941241
SG		 718{
719 unsigned int *input_buf = (unsigned int *)buf;
720 unsigned int mmc_stat;
721 unsigned int count;
722
723 /*
152ba363 724 * Start Polled Write
de941241
SG		 725 */
726 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
727 count /= 4;
728
729 while (size) {
eb9a28f6 730 ulong start = get_timer(0);
de941241
SG		 731 do {
732 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 733 if (get_timer(0) - start > MAX_RETRY_MS) {
734 printf("%s: timedout waiting for status!\n",
735 __func__);
915ffa52 736 return -ETIMEDOUT;
eb9a28f6 737 }
de941241
SG		 738 } while (mmc_stat == 0);
739
25c719e2
GI		 740 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
741 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
742
de941241
SG		 743 if ((mmc_stat & ERRI_MASK) != 0)
744 return 1;
745
746 if (mmc_stat & BWR_MASK) {
747 unsigned int k;
748
749 writel(readl(&mmc_base->stat) | BWR_MASK,
750 &mmc_base->stat);
751 for (k = 0; k < count; k++) {
752 writel(*input_buf, &mmc_base->data);
753 input_buf++;
754 }
755 size -= (count*4);
756 }
757
758 if (mmc_stat & BRR_MASK)
759 writel(readl(&mmc_base->stat) | BRR_MASK,
760 &mmc_base->stat);
761
762 if (mmc_stat & TC_MASK) {
763 writel(readl(&mmc_base->stat) | TC_MASK,
764 &mmc_base->stat);
765 break;
766 }
767 }
768 return 0;
769}
770
5baf543e
JJH		 771static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
772{
773 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
774}
775
776static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
777{
778 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
779}
780
781static void omap_hsmmc_set_clock(struct mmc *mmc)
782{
783 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
784 struct hsmmc *mmc_base;
785 unsigned int dsor = 0;
786 ulong start;
787
788 mmc_base = priv->base_addr;
789 omap_hsmmc_stop_clock(mmc_base);
790
791 /* TODO: Is setting DTO required here? */
792 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
793 (ICE_STOP | DTO_15THDTO));
794
795 if (mmc->clock != 0) {
796 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
797 if (dsor > CLKD_MAX)
798 dsor = CLKD_MAX;
799 } else {
800 dsor = CLKD_MAX;
801 }
802
803 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
804 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
805
806 start = get_timer(0);
807 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
808 if (get_timer(0) - start > MAX_RETRY_MS) {
809 printf("%s: timedout waiting for ics!\n", __func__);
810 return;
811 }
812 }
813
814 priv->clock = mmc->clock;
815 omap_hsmmc_start_clock(mmc_base);
816}
817
48a2f114 818static void omap_hsmmc_set_bus_width(struct mmc *mmc)
de941241 819{
ae000e23 820 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
cc22b0c0 821 struct hsmmc *mmc_base;
de941241 822
ae000e23 823 mmc_base = priv->base_addr;
de941241
SG		 824 /* configue bus width */
825 switch (mmc->bus_width) {
826 case 8:
827 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
828 &mmc_base->con);
829 break;
830
831 case 4:
832 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
833 &mmc_base->con);
834 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
835 &mmc_base->hctl);
836 break;
837
838 case 1:
839 default:
840 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
841 &mmc_base->con);
842 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
843 &mmc_base->hctl);
844 break;
845 }
846
48a2f114
KVA		 847 priv->bus_width = mmc->bus_width;
848}
849
850#if !CONFIG_IS_ENABLED(DM_MMC)
851static int omap_hsmmc_set_ios(struct mmc *mmc)
852{
853 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
854#else
855static int omap_hsmmc_set_ios(struct udevice *dev)
856{
857 struct omap_hsmmc_data *priv = dev_get_priv(dev);
858 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
859 struct mmc *mmc = upriv->mmc;
860#endif
861
862 if (priv->bus_width != mmc->bus_width)
863 omap_hsmmc_set_bus_width(mmc);
864
5baf543e
JJH		 865 if (priv->clock != mmc->clock)
866 omap_hsmmc_set_clock(mmc);
07b0b9c0
JC		 867
868 return 0;
de941241
SG		 869}
870
ab769f22 871#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 872#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c 873static int omap_hsmmc_getcd(struct udevice *dev)
a9d6a7e2 874{
b5511d6c 875 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 876 int value;
877
878 value = dm_gpio_get_value(&priv->cd_gpio);
879 /* if no CD return as 1 */
880 if (value < 0)
881 return 1;
882
883 if (priv->cd_inverted)
884 return !value;
885 return value;
886}
887
b5511d6c 888static int omap_hsmmc_getwp(struct udevice *dev)
a9d6a7e2 889{
b5511d6c 890 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 891 int value;
892
893 value = dm_gpio_get_value(&priv->wp_gpio);
894 /* if no WP return as 0 */
895 if (value < 0)
896 return 0;
897 return value;
898}
899#else
ab769f22
PA		 900static int omap_hsmmc_getcd(struct mmc *mmc)
901{
ae000e23 902 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 903 int cd_gpio;
904
905 /* if no CD return as 1 */
ae000e23 906 cd_gpio = priv->cd_gpio;
ab769f22
PA		 907 if (cd_gpio < 0)
908 return 1;
909
0b03a931
IG		 910 /* NOTE: assumes card detect signal is active-low */
911 return !gpio_get_value(cd_gpio);
ab769f22
PA		 912}
913
914static int omap_hsmmc_getwp(struct mmc *mmc)
915{
ae000e23 916 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 917 int wp_gpio;
918
919 /* if no WP return as 0 */
ae000e23 920 wp_gpio = priv->wp_gpio;
ab769f22
PA		 921 if (wp_gpio < 0)
922 return 0;
923
0b03a931 924 /* NOTE: assumes write protect signal is active-high */
ab769f22
PA		 925 return gpio_get_value(wp_gpio);
926}
927#endif
a9d6a7e2 928#endif
ab769f22 929
c4d660d4 930#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c
JJH		 931static const struct dm_mmc_ops omap_hsmmc_ops = {
932 .send_cmd = omap_hsmmc_send_cmd,
933 .set_ios = omap_hsmmc_set_ios,
934#ifdef OMAP_HSMMC_USE_GPIO
935 .get_cd = omap_hsmmc_getcd,
936 .get_wp = omap_hsmmc_getwp,
937#endif
938};
939#else
ab769f22
PA		 940static const struct mmc_ops omap_hsmmc_ops = {
941 .send_cmd = omap_hsmmc_send_cmd,
942 .set_ios = omap_hsmmc_set_ios,
943 .init = omap_hsmmc_init_setup,
944#ifdef OMAP_HSMMC_USE_GPIO
945 .getcd = omap_hsmmc_getcd,
946 .getwp = omap_hsmmc_getwp,
947#endif
948};
b5511d6c 949#endif
ab769f22 950
c4d660d4 951#if !CONFIG_IS_ENABLED(DM_MMC)
e3913f56
NK		 952int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
953 int wp_gpio)
de941241 954{
93bfd616 955 struct mmc *mmc;
ae000e23 956 struct omap_hsmmc_data *priv;
93bfd616
PA		 957 struct mmc_config *cfg;
958 uint host_caps_val;
959
ae000e23
JJH		 960 priv = malloc(sizeof(*priv));
961 if (priv == NULL)
93bfd616 962 return -1;
de941241 963
5a20397b 964 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
de941241
SG		 965
966 switch (dev_index) {
967 case 0:
ae000e23 968 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 969 break;
1037d585 970#ifdef OMAP_HSMMC2_BASE
de941241 971 case 1:
ae000e23 972 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
152ba363 973#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
3891a54f 974 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
3b68939f
RQ		 975 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
976 defined(CONFIG_HSMMC2_8BIT)
152ba363
LP		 977 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
978 host_caps_val |= MMC_MODE_8BIT;
979#endif
de941241 980 break;
1037d585
TR		 981#endif
982#ifdef OMAP_HSMMC3_BASE
de941241 983 case 2:
ae000e23 984 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
3891a54f 985#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
152ba363
LP		 986 /* Enable 8-bit interface for eMMC on DRA7XX */
987 host_caps_val |= MMC_MODE_8BIT;
988#endif
de941241 989 break;
1037d585 990#endif
de941241 991 default:
ae000e23 992 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241
SG		 993 return 1;
994 }
ab769f22
PA		 995#ifdef OMAP_HSMMC_USE_GPIO
996 /* on error gpio values are set to -1, which is what we want */
ae000e23
JJH		 997 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
998 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
ab769f22 999#endif
173ddc5b 1000
ae000e23 1001 cfg = &priv->cfg;
de941241 1002
93bfd616
PA		 1003 cfg->name = "OMAP SD/MMC";
1004 cfg->ops = &omap_hsmmc_ops;
1005
1006 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1007 cfg->host_caps = host_caps_val & ~host_caps_mask;
1008
1009 cfg->f_min = 400000;
bbbc1ae9
JS		 1010
1011 if (f_max != 0)
93bfd616 1012 cfg->f_max = f_max;
bbbc1ae9 1013 else {
93bfd616
PA		 1014 if (cfg->host_caps & MMC_MODE_HS) {
1015 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1016 cfg->f_max = 52000000;
bbbc1ae9 1017 else
93bfd616 1018 cfg->f_max = 26000000;
bbbc1ae9 1019 } else
93bfd616 1020 cfg->f_max = 20000000;
bbbc1ae9 1021 }
de941241 1022
93bfd616 1023 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
8feafcc4 1024
4ca9244d
JR		 1025#if defined(CONFIG_OMAP34XX)
1026 /*
1027 * Silicon revs 2.1 and older do not support multiblock transfers.
1028 */
1029 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
93bfd616 1030 cfg->b_max = 1;
4ca9244d 1031#endif
ae000e23 1032 mmc = mmc_create(cfg, priv);
93bfd616
PA		 1033 if (mmc == NULL)
1034 return -1;
de941241
SG		 1035
1036 return 0;
1037}
a9d6a7e2 1038#else
2558c049 1039#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 1040static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1041{
3d673ffc
JJH		 1042 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1043 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2 1044 const void *fdt = gd->fdt_blob;
e160f7d4 1045 int node = dev_of_offset(dev);
a9d6a7e2
M		 1046 int val;
1047
a821c4af
SG		 1048 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1049 sizeof(struct hsmmc *),
741726ae 1050 MAP_NOCACHE);
a9d6a7e2
M		 1051
1052 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1053 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1054 if (val < 0) {
1055 printf("error: bus-width property missing\n");
1056 return -ENOENT;
1057 }
1058
1059 switch (val) {
1060 case 0x8:
1061 cfg->host_caps |= MMC_MODE_8BIT;
1062 case 0x4:
1063 cfg->host_caps |= MMC_MODE_4BIT;
1064 break;
1065 default:
1066 printf("error: invalid bus-width property\n");
1067 return -ENOENT;
1068 }
1069
1070 cfg->f_min = 400000;
1071 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1072 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1073 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1074
4de2de51 1075#ifdef OMAP_HSMMC_USE_GPIO
2558c049 1076 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
4de2de51 1077#endif
a9d6a7e2
M		 1078
1079 return 0;
1080}
2558c049 1081#endif
a9d6a7e2 1082
17c9a1c1
JJH		 1083#ifdef CONFIG_BLK
1084
1085static int omap_hsmmc_bind(struct udevice *dev)
1086{
1087 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1088
1089 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1090}
1091#endif
a9d6a7e2
M		 1092static int omap_hsmmc_probe(struct udevice *dev)
1093{
3d673ffc 1094 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
a9d6a7e2
M		 1095 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1096 struct omap_hsmmc_data *priv = dev_get_priv(dev);
3d673ffc 1097 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2
M		 1098 struct mmc *mmc;
1099
a9d6a7e2 1100 cfg->name = "OMAP SD/MMC";
2558c049
LV		 1101 priv->base_addr = plat->base_addr;
1102#ifdef OMAP_HSMMC_USE_GPIO
1103 priv->cd_inverted = plat->cd_inverted;
1104#endif
a9d6a7e2 1105
17c9a1c1
JJH		 1106#ifdef CONFIG_BLK
1107 mmc = &plat->mmc;
1108#else
a9d6a7e2
M		 1109 mmc = mmc_create(cfg, priv);
1110 if (mmc == NULL)
1111 return -1;
17c9a1c1 1112#endif
a9d6a7e2 1113
2558c049 1114#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
5cc6a245
M		 1115 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1116 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1117#endif
1118
cffe5d86 1119 mmc->dev = dev;
a9d6a7e2
M		 1120 upriv->mmc = mmc;
1121
b5511d6c 1122 return omap_hsmmc_init_setup(mmc);
a9d6a7e2
M		 1123}
1124
2558c049 1125#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2 1126static const struct udevice_id omap_hsmmc_ids[] = {
741726ae
JJH		 1127 { .compatible = "ti,omap3-hsmmc" },
1128 { .compatible = "ti,omap4-hsmmc" },
1129 { .compatible = "ti,am33xx-hsmmc" },
a9d6a7e2
M		 1130 { }
1131};
2558c049 1132#endif
a9d6a7e2
M		 1133
1134U_BOOT_DRIVER(omap_hsmmc) = {
1135 .name = "omap_hsmmc",
1136 .id = UCLASS_MMC,
2558c049 1137#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 1138 .of_match = omap_hsmmc_ids,
1139 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2558c049
LV		 1140 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1141#endif
17c9a1c1
JJH		 1142#ifdef CONFIG_BLK
1143 .bind = omap_hsmmc_bind,
1144#endif
b5511d6c 1145 .ops = &omap_hsmmc_ops,
a9d6a7e2
M		 1146 .probe = omap_hsmmc_probe,
1147 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
cbcb1701 1148 .flags = DM_FLAG_PRE_RELOC,
a9d6a7e2
M		 1149};
1150#endif
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