[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 * Sukumar Ghorai <s-ghorai@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation's version 2 of
 * the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
#include <twl4030.h>
#include <twl6030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>

/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS	1000

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
			unsigned int siz);
static struct mmc hsmmc_dev[2];

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
	u32 value = 0;
	struct omap4_sys_ctrl_regs *const ctrl =
		(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;


	value = readl(&ctrl->control_pbiaslite);
	value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
	writel(value, &ctrl->control_pbiaslite);
	/* set VMMC to 3V */
	twl6030_power_mmc_init();
	value = readl(&ctrl->control_pbiaslite);
	value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
	writel(value, &ctrl->control_pbiaslite);
}
#endif

unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_TWL4030_POWER)
	twl4030_power_mmc_init();
#endif

#if defined(CONFIG_OMAP34XX)
	t2_t *t2_base = (t2_t *)T2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
		&t2_base->pbias_lite);

	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
		&t2_base->devconf0);

	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
		&t2_base->devconf1);

	writel(readl(&prcm_base->fclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->fclken1_core);

	writel(readl(&prcm_base->iclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->iclken1_core);
#endif

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	/* PBIAS config needed for MMC1 only */
	if (mmc->block_dev.dev == 0)
		omap4_vmmc_pbias_config(mmc);
#endif

	return 0;
}

void mmc_init_stream(struct hsmmc *mmc_base)
{
	ulong start;

	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);

	writel(MMC_CMD0, &mmc_base->cmd);
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc!\n", __func__);
			return;
		}
	}
	writel(CC_MASK, &mmc_base->stat)
		;
	writel(MMC_CMD0, &mmc_base->cmd)
		;
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}


static int mmc_init_setup(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int reg_val;
	unsigned int dsor;
	ulong start;

	mmc_board_init(mmc);

	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
		&mmc_base->sysconfig);
	start = get_timer(0);
	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for softresetall!\n",
				__func__);
			return TIMEOUT;
		}
	}
	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
		&mmc_base->capa);

	reg_val = readl(&mmc_base->con) & RESERVED_MASK;

	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);

	dsor = 240;
	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
		(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
		(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);

	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);

	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
		&mmc_base->ie);

	mmc_init_stream(mmc_base);

	return 0;
}


static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
			struct mmc_data *data)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int flags, mmc_stat;
	ulong start;

	start = get_timer(0);
	while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cmddis!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(0xFFFFFFFF, &mmc_base->stat);
	start = get_timer(0);
	while (readl(&mmc_base->stat)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for stat!\n", __func__);
			return TIMEOUT;
		}
	}
	/*
	 * CMDREG
	 * CMDIDX[13:8]	: Command index
	 * DATAPRNT[5]	: Data Present Select
	 * ENCMDIDX[4]	: Command Index Check Enable
	 * ENCMDCRC[3]	: Command CRC Check Enable
	 * RSPTYP[1:0]
	 *	00 = No Response
	 *	01 = Length 136
	 *	10 = Length 48
	 *	11 = Length 48 Check busy after response
	 */
	/* Delay added before checking the status of frq change
	 * retry not supported by mmc.c(core file)
	 */
	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
		udelay(50000); /* wait 50 ms */

	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = 0;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		flags = RSP_TYPE_LGHT48B;
	else
		flags = RSP_TYPE_LGHT48;

	/* enable default flags */
	flags =	flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
			MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= CCCE_CHECK;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= CICE_CHECK;

	if (data) {
		if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
			 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
			flags |= (MSBS_MULTIBLK | BCE_ENABLE);
			data->blocksize = 512;
			writel(data->blocksize | (data->blocks << 16),
							&mmc_base->blk);
		} else
			writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);

		if (data->flags & MMC_DATA_READ)
			flags |= (DP_DATA | DDIR_READ);
		else
			flags |= (DP_DATA | DDIR_WRITE);
	}

	writel(cmd->cmdarg, &mmc_base->arg);
	writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);

	start = get_timer(0);
	do {
		mmc_stat = readl(&mmc_base->stat);
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s : timeout: No status update\n", __func__);
			return TIMEOUT;
		}
	} while (!mmc_stat);

	if ((mmc_stat & IE_CTO) != 0)
		return TIMEOUT;
	else if ((mmc_stat & ERRI_MASK) != 0)
		return -1;

	if (mmc_stat & CC_MASK) {
		writel(CC_MASK, &mmc_base->stat);
		if (cmd->resp_type & MMC_RSP_PRESENT) {
			if (cmd->resp_type & MMC_RSP_136) {
				/* response type 2 */
				cmd->response[3] = readl(&mmc_base->rsp10);
				cmd->response[2] = readl(&mmc_base->rsp32);
				cmd->response[1] = readl(&mmc_base->rsp54);
				cmd->response[0] = readl(&mmc_base->rsp76);
			} else
				/* response types 1, 1b, 3, 4, 5, 6 */
				cmd->response[0] = readl(&mmc_base->rsp10);
		}
	}

	if (data && (data->flags & MMC_DATA_READ)) {
		mmc_read_data(mmc_base,	data->dest,
				data->blocksize * data->blocks);
	} else if (data && (data->flags & MMC_DATA_WRITE)) {
		mmc_write_data(mmc_base, data->src,
				data->blocksize * data->blocks);
	}
	return 0;
}

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
	unsigned int *output_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BRR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);
			for (k = 0; k < count; k++) {
				*output_buf = readl(&mmc_base->data);
				output_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BWR_MASK)
			writel(readl(&mmc_base->stat) | BWR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
				unsigned int size)
{
	unsigned int *input_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BWR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BWR_MASK,
					&mmc_base->stat);
			for (k = 0; k < count; k++) {
				writel(*input_buf, &mmc_base->data);
				input_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BRR_MASK)
			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static void mmc_set_ios(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int dsor = 0;
	ulong start;

	/* configue bus width */
	switch (mmc->bus_width) {
	case 8:
		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
			&mmc_base->con);
		break;

	case 4:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
			&mmc_base->hctl);
		break;

	case 1:
	default:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
			&mmc_base->hctl);
		break;
	}

	/* configure clock with 96Mhz system clock.
	 */
	if (mmc->clock != 0) {
		dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
		if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
			dsor++;
	}

	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
				(ICE_STOP | DTO_15THDTO | CEN_DISABLE));

	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
				(dsor << CLKD_OFFSET) | ICE_OSCILLATE);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}

int omap_mmc_init(int dev_index)
{
	struct mmc *mmc;

	mmc = &hsmmc_dev[dev_index];

	sprintf(mmc->name, "OMAP SD/MMC");
	mmc->send_cmd = mmc_send_cmd;
	mmc->set_ios = mmc_set_ios;
	mmc->init = mmc_init_setup;
	mmc->getcd = NULL;

	switch (dev_index) {
	case 0:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		break;
#ifdef OMAP_HSMMC2_BASE
	case 1:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
		break;
#endif
#ifdef OMAP_HSMMC3_BASE
	case 2:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
		break;
#endif
	default:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		return 1;
	}
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
				MMC_MODE_HC;

	mmc->f_min = 400000;
	mmc->f_max = 52000000;

	mmc->b_max = 0;

#if defined(CONFIG_OMAP34XX)
	/*
	 * Silicon revs 2.1 and older do not support multiblock transfers.
	 */
	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
		mmc->b_max = 1;
#endif

	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
de941241 SG	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	* Sukumar Ghorai <s-ghorai@ti.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation's version 2 of
	12	* the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <config.h>
	26	#include <common.h>
	27	#include <mmc.h>
	28	#include <part.h>
	29	#include <i2c.h>
	30	#include <twl4030.h>
14fa2dd0	31	#include <twl6030.h>
de941241 SG	32	#include <asm/io.h>
de941241 SG	33	#include <asm/arch/mmc_host_def.h>
96e0e7b3	34	#include <asm/arch/sys_proto.h>
de941241	35
eb9a28f6 NM	36	/* If we fail after 1 second wait, something is really bad */
	37	#define MAX_RETRY_MS 1000
	38
933efe64 S	39	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size);
	40	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
	41	unsigned int siz);
de941241	42	static struct mmc hsmmc_dev[2];
14fa2dd0 B	43
	44	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	45	static void omap4_vmmc_pbias_config(struct mmc *mmc)
	46	{
	47	u32 value = 0;
	48	struct omap4_sys_ctrl_regs *const ctrl =
	49	(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
	50
	51
	52	value = readl(&ctrl->control_pbiaslite);
	53	value &= ~(MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ);
	54	writel(value, &ctrl->control_pbiaslite);
	55	/* set VMMC to 3V */
	56	twl6030_power_mmc_init();
	57	value = readl(&ctrl->control_pbiaslite);
	58	value \|= MMC1_PBIASLITE_VMODE \| MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ;
	59	writel(value, &ctrl->control_pbiaslite);
	60	}
	61	#endif
	62
	63	unsigned char mmc_board_init(struct mmc *mmc)
de941241 SG	64	{
	65	#if defined(CONFIG_TWL4030_POWER)
	66	twl4030_power_mmc_init();
	67	#endif
	68
	69	#if defined(CONFIG_OMAP34XX)
	70	t2_t t2_base = (t2_t )T2_BASE;
	71	struct prcm prcm_base = (struct prcm )PRCM_BASE;
	72
	73	writel(readl(&t2_base->pbias_lite) \| PBIASLITEPWRDNZ1 \|
	74	PBIASSPEEDCTRL0 \| PBIASLITEPWRDNZ0,
	75	&t2_base->pbias_lite);
	76
	77	writel(readl(&t2_base->devconf0) \| MMCSDIO1ADPCLKISEL,
	78	&t2_base->devconf0);
	79
	80	writel(readl(&t2_base->devconf1) \| MMCSDIO2ADPCLKISEL,
	81	&t2_base->devconf1);
	82
	83	writel(readl(&prcm_base->fclken1_core) \|
	84	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	85	&prcm_base->fclken1_core);
	86
	87	writel(readl(&prcm_base->iclken1_core) \|
	88	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	89	&prcm_base->iclken1_core);
	90	#endif
	91
14fa2dd0 B	92	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	93	/* PBIAS config needed for MMC1 only */
	94	if (mmc->block_dev.dev == 0)
	95	omap4_vmmc_pbias_config(mmc);
	96	#endif
de941241 SG	97
	98	return 0;
	99	}
	100
933efe64	101	void mmc_init_stream(struct hsmmc *mmc_base)
de941241	102	{
eb9a28f6	103	ulong start;
de941241 SG	104
	105	writel(readl(&mmc_base->con) \| INIT_INITSTREAM, &mmc_base->con);
	106
	107	writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6 NM	108	start = get_timer(0);
	109	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	110	if (get_timer(0) - start > MAX_RETRY_MS) {
	111	printf("%s: timedout waiting for cc!\n", __func__);
	112	return;
	113	}
	114	}
de941241 SG	115	writel(CC_MASK, &mmc_base->stat)
	116	;
	117	writel(MMC_CMD0, &mmc_base->cmd)
	118	;
eb9a28f6 NM	119	start = get_timer(0);
	120	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	121	if (get_timer(0) - start > MAX_RETRY_MS) {
	122	printf("%s: timedout waiting for cc2!\n", __func__);
	123	return;
	124	}
	125	}
de941241 SG	126	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
	127	}
	128
	129
	130	static int mmc_init_setup(struct mmc *mmc)
	131	{
933efe64	132	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241 SG	133	unsigned int reg_val;
de941241 SG	134	unsigned int dsor;
eb9a28f6	135	ulong start;
de941241	136
14fa2dd0	137	mmc_board_init(mmc);
de941241 SG	138
	139	writel(readl(&mmc_base->sysconfig) \| MMC_SOFTRESET,
	140	&mmc_base->sysconfig);
eb9a28f6 NM	141	start = get_timer(0);
	142	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
	143	if (get_timer(0) - start > MAX_RETRY_MS) {
	144	printf("%s: timedout waiting for cc2!\n", __func__);
	145	return TIMEOUT;
	146	}
	147	}
de941241	148	writel(readl(&mmc_base->sysctl) \| SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6 NM	149	start = get_timer(0);
	150	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
	151	if (get_timer(0) - start > MAX_RETRY_MS) {
	152	printf("%s: timedout waiting for softresetall!\n",
	153	__func__);
	154	return TIMEOUT;
	155	}
	156	}
de941241 SG	157	writel(DTW_1_BITMODE \| SDBP_PWROFF \| SDVS_3V0, &mmc_base->hctl);
	158	writel(readl(&mmc_base->capa) \| VS30_3V0SUP \| VS18_1V8SUP,
	159	&mmc_base->capa);
	160
	161	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
	162
	163	writel(CTPL_MMC_SD \| reg_val \| WPP_ACTIVEHIGH \| CDP_ACTIVEHIGH \|
	164	MIT_CTO \| DW8_1_4BITMODE \| MODE_FUNC \| STR_BLOCK \|
	165	HR_NOHOSTRESP \| INIT_NOINIT \| NOOPENDRAIN, &mmc_base->con);
	166
	167	dsor = 240;
	168	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	169	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	170	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	171	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
eb9a28f6 NM	172	start = get_timer(0);
	173	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	174	if (get_timer(0) - start > MAX_RETRY_MS) {
	175	printf("%s: timedout waiting for ics!\n", __func__);
	176	return TIMEOUT;
	177	}
	178	}
de941241 SG	179	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	180
	181	writel(readl(&mmc_base->hctl) \| SDBP_PWRON, &mmc_base->hctl);
	182
	183	writel(IE_BADA \| IE_CERR \| IE_DEB \| IE_DCRC \| IE_DTO \| IE_CIE \|
	184	IE_CEB \| IE_CCRC \| IE_CTO \| IE_BRR \| IE_BWR \| IE_TC \| IE_CC,
	185	&mmc_base->ie);
	186
	187	mmc_init_stream(mmc_base);
	188
	189	return 0;
	190	}
	191
	192
	193	static int mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	194	struct mmc_data *data)
	195	{
933efe64	196	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	197	unsigned int flags, mmc_stat;
eb9a28f6	198	ulong start;
de941241	199
eb9a28f6 NM	200	start = get_timer(0);
	201	while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) {
	202	if (get_timer(0) - start > MAX_RETRY_MS) {
	203	printf("%s: timedout waiting for cmddis!\n", __func__);
	204	return TIMEOUT;
	205	}
	206	}
de941241	207	writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6 NM	208	start = get_timer(0);
	209	while (readl(&mmc_base->stat)) {
	210	if (get_timer(0) - start > MAX_RETRY_MS) {
	211	printf("%s: timedout waiting for stat!\n", __func__);
	212	return TIMEOUT;
	213	}
	214	}
de941241 SG	215	/*
	216	* CMDREG
	217	* CMDIDX[13:8] : Command index
	218	* DATAPRNT[5] : Data Present Select
	219	* ENCMDIDX[4] : Command Index Check Enable
	220	* ENCMDCRC[3] : Command CRC Check Enable
	221	* RSPTYP[1:0]
	222	* 00 = No Response
	223	* 01 = Length 136
	224	* 10 = Length 48
	225	* 11 = Length 48 Check busy after response
	226	*/
	227	/* Delay added before checking the status of frq change
	228	* retry not supported by mmc.c(core file)
	229	*/
	230	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
	231	udelay(50000); /* wait 50 ms */
	232
	233	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	234	flags = 0;
	235	else if (cmd->resp_type & MMC_RSP_136)
	236	flags = RSP_TYPE_LGHT136 \| CICE_NOCHECK;
	237	else if (cmd->resp_type & MMC_RSP_BUSY)
	238	flags = RSP_TYPE_LGHT48B;
	239	else
	240	flags = RSP_TYPE_LGHT48;
	241
	242	/* enable default flags */
	243	flags = flags \| (CMD_TYPE_NORMAL \| CICE_NOCHECK \| CCCE_NOCHECK \|
	244	MSBS_SGLEBLK \| ACEN_DISABLE \| BCE_DISABLE \| DE_DISABLE);
	245
	246	if (cmd->resp_type & MMC_RSP_CRC)
	247	flags \|= CCCE_CHECK;
	248	if (cmd->resp_type & MMC_RSP_OPCODE)
	249	flags \|= CICE_CHECK;
	250
	251	if (data) {
	252	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) \|\|
	253	(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
	254	flags \|= (MSBS_MULTIBLK \| BCE_ENABLE);
	255	data->blocksize = 512;
	256	writel(data->blocksize \| (data->blocks << 16),
	257	&mmc_base->blk);
	258	} else
	259	writel(data->blocksize \| NBLK_STPCNT, &mmc_base->blk);
	260
	261	if (data->flags & MMC_DATA_READ)
	262	flags \|= (DP_DATA \| DDIR_READ);
	263	else
	264	flags \|= (DP_DATA \| DDIR_WRITE);
	265	}
	266
	267	writel(cmd->cmdarg, &mmc_base->arg);
	268	writel((cmd->cmdidx << 24) \| flags, &mmc_base->cmd);
	269
eb9a28f6	270	start = get_timer(0);
de941241 SG	271	do {
de941241 SG	272	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	273	if (get_timer(0) - start > MAX_RETRY_MS) {
	274	printf("%s : timeout: No status update\n", __func__);
	275	return TIMEOUT;
	276	}
	277	} while (!mmc_stat);
de941241 SG	278
	279	if ((mmc_stat & IE_CTO) != 0)
	280	return TIMEOUT;
	281	else if ((mmc_stat & ERRI_MASK) != 0)
	282	return -1;
	283
	284	if (mmc_stat & CC_MASK) {
	285	writel(CC_MASK, &mmc_base->stat);
	286	if (cmd->resp_type & MMC_RSP_PRESENT) {
	287	if (cmd->resp_type & MMC_RSP_136) {
	288	/* response type 2 */
	289	cmd->response[3] = readl(&mmc_base->rsp10);
	290	cmd->response[2] = readl(&mmc_base->rsp32);
	291	cmd->response[1] = readl(&mmc_base->rsp54);
	292	cmd->response[0] = readl(&mmc_base->rsp76);
	293	} else
	294	/* response types 1, 1b, 3, 4, 5, 6 */
	295	cmd->response[0] = readl(&mmc_base->rsp10);
	296	}
	297	}
	298
	299	if (data && (data->flags & MMC_DATA_READ)) {
	300	mmc_read_data(mmc_base, data->dest,
	301	data->blocksize * data->blocks);
	302	} else if (data && (data->flags & MMC_DATA_WRITE)) {
	303	mmc_write_data(mmc_base, data->src,
	304	data->blocksize * data->blocks);
	305	}
	306	return 0;
	307	}
	308
933efe64	309	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size)
de941241 SG	310	{
	311	unsigned int output_buf = (unsigned int )buf;
	312	unsigned int mmc_stat;
	313	unsigned int count;
	314
	315	/*
	316	* Start Polled Read
	317	*/
	318	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	319	count /= 4;
	320
	321	while (size) {
eb9a28f6	322	ulong start = get_timer(0);
de941241 SG	323	do {
de941241 SG	324	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	325	if (get_timer(0) - start > MAX_RETRY_MS) {
	326	printf("%s: timedout waiting for status!\n",
	327	__func__);
	328	return TIMEOUT;
	329	}
de941241 SG	330	} while (mmc_stat == 0);
	331
	332	if ((mmc_stat & ERRI_MASK) != 0)
	333	return 1;
	334
	335	if (mmc_stat & BRR_MASK) {
	336	unsigned int k;
	337
	338	writel(readl(&mmc_base->stat) \| BRR_MASK,
	339	&mmc_base->stat);
	340	for (k = 0; k < count; k++) {
	341	*output_buf = readl(&mmc_base->data);
	342	output_buf++;
	343	}
	344	size -= (count*4);
	345	}
	346
	347	if (mmc_stat & BWR_MASK)
	348	writel(readl(&mmc_base->stat) \| BWR_MASK,
	349	&mmc_base->stat);
	350
	351	if (mmc_stat & TC_MASK) {
	352	writel(readl(&mmc_base->stat) \| TC_MASK,
	353	&mmc_base->stat);
	354	break;
	355	}
	356	}
	357	return 0;
	358	}
	359
933efe64 S	360	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
933efe64 S	361	unsigned int size)
de941241 SG	362	{
	363	unsigned int input_buf = (unsigned int )buf;
	364	unsigned int mmc_stat;
	365	unsigned int count;
	366
	367	/*
	368	* Start Polled Read
	369	*/
	370	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	371	count /= 4;
	372
	373	while (size) {
eb9a28f6	374	ulong start = get_timer(0);
de941241 SG	375	do {
de941241 SG	376	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	377	if (get_timer(0) - start > MAX_RETRY_MS) {
	378	printf("%s: timedout waiting for status!\n",
	379	__func__);
	380	return TIMEOUT;
	381	}
de941241 SG	382	} while (mmc_stat == 0);
	383
	384	if ((mmc_stat & ERRI_MASK) != 0)
	385	return 1;
	386
	387	if (mmc_stat & BWR_MASK) {
	388	unsigned int k;
	389
	390	writel(readl(&mmc_base->stat) \| BWR_MASK,
	391	&mmc_base->stat);
	392	for (k = 0; k < count; k++) {
	393	writel(*input_buf, &mmc_base->data);
	394	input_buf++;
	395	}
	396	size -= (count*4);
	397	}
	398
	399	if (mmc_stat & BRR_MASK)
	400	writel(readl(&mmc_base->stat) \| BRR_MASK,
	401	&mmc_base->stat);
	402
	403	if (mmc_stat & TC_MASK) {
	404	writel(readl(&mmc_base->stat) \| TC_MASK,
	405	&mmc_base->stat);
	406	break;
	407	}
	408	}
	409	return 0;
	410	}
	411
	412	static void mmc_set_ios(struct mmc *mmc)
	413	{
933efe64	414	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	415	unsigned int dsor = 0;
eb9a28f6	416	ulong start;
de941241 SG	417
	418	/* configue bus width */
	419	switch (mmc->bus_width) {
	420	case 8:
	421	writel(readl(&mmc_base->con) \| DTW_8_BITMODE,
	422	&mmc_base->con);
	423	break;
	424
	425	case 4:
	426	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	427	&mmc_base->con);
	428	writel(readl(&mmc_base->hctl) \| DTW_4_BITMODE,
	429	&mmc_base->hctl);
	430	break;
	431
	432	case 1:
	433	default:
	434	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	435	&mmc_base->con);
	436	writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
	437	&mmc_base->hctl);
	438	break;
	439	}
	440
	441	/* configure clock with 96Mhz system clock.
	442	*/
	443	if (mmc->clock != 0) {
	444	dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
	445	if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
	446	dsor++;
	447	}
	448
	449	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	450	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	451
	452	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	453	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
	454
eb9a28f6 NM	455	start = get_timer(0);
	456	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	457	if (get_timer(0) - start > MAX_RETRY_MS) {
	458	printf("%s: timedout waiting for ics!\n", __func__);
	459	return;
	460	}
	461	}
de941241 SG	462	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	463	}
	464
	465	int omap_mmc_init(int dev_index)
	466	{
	467	struct mmc *mmc;
	468
	469	mmc = &hsmmc_dev[dev_index];
	470
	471	sprintf(mmc->name, "OMAP SD/MMC");
	472	mmc->send_cmd = mmc_send_cmd;
	473	mmc->set_ios = mmc_set_ios;
	474	mmc->init = mmc_init_setup;
48972d90	475	mmc->getcd = NULL;
de941241 SG	476
	477	switch (dev_index) {
	478	case 0:
933efe64	479	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241	480	break;
1037d585	481	#ifdef OMAP_HSMMC2_BASE
de941241	482	case 1:
933efe64	483	mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
de941241	484	break;
1037d585 TR	485	#endif
1037d585 TR	486	#ifdef OMAP_HSMMC3_BASE
de941241	487	case 2:
933efe64	488	mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
de941241	489	break;
1037d585	490	#endif
de941241	491	default:
933efe64	492	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 SG	493	return 1;
	494	}
	495	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
ecd9af88 B	496	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS \|
ecd9af88 B	497	MMC_MODE_HC;
de941241 SG	498
	499	mmc->f_min = 400000;
	500	mmc->f_max = 52000000;
	501
8feafcc4 JR	502	mmc->b_max = 0;
8feafcc4 JR	503
4ca9244d JR	504	#if defined(CONFIG_OMAP34XX)
	505	/*
	506	* Silicon revs 2.1 and older do not support multiblock transfers.
	507	*/
	508	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
	509	mmc->b_max = 1;
	510	#endif
	511
de941241 SG	512	mmc_register(mmc);
	513
	514	return 0;
	515	}