]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mmc/omap_hsmmc.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
CommitLineData
de941241
SG		 1/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
93bfd616 27#include <malloc.h>
f0d53e88 28#include <memalign.h>
de941241
SG		 29#include <mmc.h>
30#include <part.h>
31#include <i2c.h>
339d5789 32#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
cb199102 33#include <palmas.h>
339d5789 34#endif
de941241
SG		 35#include <asm/io.h>
36#include <asm/arch/mmc_host_def.h>
3b68939f
RQ		 37#if !defined(CONFIG_SOC_KEYSTONE)
38#include <asm/gpio.h>
96e0e7b3 39#include <asm/arch/sys_proto.h>
3b68939f 40#endif
2a48b3a2
TR		 41#ifdef CONFIG_MMC_OMAP36XX_PINS
42#include <asm/arch/mux.h>
43#endif
a9d6a7e2
M		 44#include <dm.h>
45
46DECLARE_GLOBAL_DATA_PTR;
de941241 47
ab769f22
PA		 48/* simplify defines to OMAP_HSMMC_USE_GPIO */
49#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51#define OMAP_HSMMC_USE_GPIO
52#else
53#undef OMAP_HSMMC_USE_GPIO
54#endif
55
25c719e2
GI		 56/* common definitions for all OMAPs */
57#define SYSCTL_SRC (1 << 25)
58#define SYSCTL_SRD (1 << 26)
59
cc22b0c0
NK		 60struct omap_hsmmc_data {
61 struct hsmmc *base_addr;
c4d660d4 62#if !CONFIG_IS_ENABLED(DM_MMC)
93bfd616 63 struct mmc_config cfg;
3d673ffc 64#endif
48a2f114 65 uint bus_width;
5baf543e 66 uint clock;
ab769f22 67#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 68#if CONFIG_IS_ENABLED(DM_MMC)
a9d6a7e2
M		 69 struct gpio_desc cd_gpio; /* Change Detect GPIO */
70 struct gpio_desc wp_gpio; /* Write Protect GPIO */
71 bool cd_inverted;
72#else
e874d5b0 73 int cd_gpio;
e3913f56 74 int wp_gpio;
ab769f22 75#endif
b5944817
KVA		 76#endif
77#if CONFIG_IS_ENABLED(DM_MMC)
78 uint iov;
8fc238bf 79 enum bus_mode mode;
a9d6a7e2 80#endif
f0d53e88
KVA		 81 u8 controller_flags;
82#ifndef CONFIG_OMAP34XX
83 struct omap_hsmmc_adma_desc *adma_desc_table;
84 uint desc_slot;
85#endif
86};
87
88#ifndef CONFIG_OMAP34XX
89struct omap_hsmmc_adma_desc {
90 u8 attr;
91 u8 reserved;
92 u16 len;
93 u32 addr;
cc22b0c0
NK		 94};
95
f0d53e88
KVA		 96#define ADMA_MAX_LEN 63488
97
98/* Decriptor table defines */
99#define ADMA_DESC_ATTR_VALID BIT(0)
100#define ADMA_DESC_ATTR_END BIT(1)
101#define ADMA_DESC_ATTR_INT BIT(2)
102#define ADMA_DESC_ATTR_ACT1 BIT(4)
103#define ADMA_DESC_ATTR_ACT2 BIT(5)
104
105#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
106#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
107#endif
108
eb9a28f6
NM		 109/* If we fail after 1 second wait, something is really bad */
110#define MAX_RETRY_MS 1000
a4efd737 111#define MMC_TIMEOUT_MS 20
eb9a28f6 112
f0d53e88
KVA		 113/* DMA transfers can take a long time if a lot a data is transferred.
114 * The timeout must take in account the amount of data. Let's assume
115 * that the time will never exceed 333 ms per MB (in other word we assume
116 * that the bandwidth is always above 3MB/s).
117 */
118#define DMA_TIMEOUT_PER_MB 333
b5944817
KVA		 119#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
120#define OMAP_HSMMC_NO_1_8_V BIT(1)
f0d53e88
KVA		 121#define OMAP_HSMMC_USE_ADMA BIT(2)
122
933efe64
S		 123static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
124static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
125 unsigned int siz);
5baf543e
JJH		 126static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
127static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
14761cae 128static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
14fa2dd0 129
ae000e23
JJH		 130static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
131{
c4d660d4 132#if CONFIG_IS_ENABLED(DM_MMC)
ae000e23
JJH		 133 return dev_get_priv(mmc->dev);
134#else
135 return (struct omap_hsmmc_data *)mmc->priv;
136#endif
3d673ffc
JJH		 137}
138static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
139{
c4d660d4 140#if CONFIG_IS_ENABLED(DM_MMC)
3d673ffc
JJH		 141 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
142 return &plat->cfg;
143#else
144 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
145#endif
ae000e23
JJH		 146}
147
c4d660d4 148#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
e874d5b0
NK		 149static int omap_mmc_setup_gpio_in(int gpio, const char *label)
150{
5915a2ad 151 int ret;
e874d5b0 152
5915a2ad
SG		 153#ifndef CONFIG_DM_GPIO
154 if (!gpio_is_valid(gpio))
e874d5b0 155 return -1;
5915a2ad
SG		 156#endif
157 ret = gpio_request(gpio, label);
158 if (ret)
159 return ret;
e874d5b0 160
5915a2ad
SG		 161 ret = gpio_direction_input(gpio);
162 if (ret)
163 return ret;
e874d5b0
NK		 164
165 return gpio;
166}
e874d5b0
NK		 167#endif
168
750121c3 169static unsigned char mmc_board_init(struct mmc *mmc)
de941241 170{
de941241 171#if defined(CONFIG_OMAP34XX)
3d673ffc 172 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
de941241
SG		 173 t2_t *t2_base = (t2_t *)T2_BASE;
174 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
b1e725f2 175 u32 pbias_lite;
6aca17c9
AF		 176#ifdef CONFIG_MMC_OMAP36XX_PINS
177 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
178#endif
de941241 179
b1e725f2
GI		 180 pbias_lite = readl(&t2_base->pbias_lite);
181 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
5bfdd1fc
AA		 182#ifdef CONFIG_TARGET_OMAP3_CAIRO
183 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
184 pbias_lite &= ~PBIASLITEVMODE0;
6aca17c9
AF		 185#endif
186#ifdef CONFIG_MMC_OMAP36XX_PINS
187 if (get_cpu_family() == CPU_OMAP36XX) {
188 /* Disable extended drain IO before changing PBIAS */
189 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
190 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
191 }
5bfdd1fc 192#endif
b1e725f2 193 writel(pbias_lite, &t2_base->pbias_lite);
aac5450e 194
b1e725f2 195 writel(pbias_lite | PBIASLITEPWRDNZ1 |
de941241
SG		 196 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
197 &t2_base->pbias_lite);
198
6aca17c9
AF		 199#ifdef CONFIG_MMC_OMAP36XX_PINS
200 if (get_cpu_family() == CPU_OMAP36XX)
201 /* Enable extended drain IO after changing PBIAS */
202 writel(wkup_ctrl |
203 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
204 OMAP34XX_CTRL_WKUP_CTRL);
205#endif
de941241
SG		 206 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
207 &t2_base->devconf0);
208
209 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
210 &t2_base->devconf1);
211
bbbc1ae9 212 /* Change from default of 52MHz to 26MHz if necessary */
3d673ffc 213 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
bbbc1ae9
JS		 214 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
215 &t2_base->ctl_prog_io1);
216
de941241
SG		 217 writel(readl(&prcm_base->fclken1_core) |
218 EN_MMC1 | EN_MMC2 | EN_MMC3,
219 &prcm_base->fclken1_core);
220
221 writel(readl(&prcm_base->iclken1_core) |
222 EN_MMC1 | EN_MMC2 | EN_MMC3,
223 &prcm_base->iclken1_core);
224#endif
225
b4b06006 226#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
14fa2dd0 227 /* PBIAS config needed for MMC1 only */
dc09127a 228 if (mmc_get_blk_desc(mmc)->devnum == 0)
b4b06006 229 vmmc_pbias_config(LDO_VOLT_3V0);
dd23e59d 230#endif
de941241
SG		 231
232 return 0;
233}
234
933efe64 235void mmc_init_stream(struct hsmmc *mmc_base)
de941241 236{
eb9a28f6 237 ulong start;
de941241
SG		 238
239 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
240
241 writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6
NM		 242 start = get_timer(0);
243 while (!(readl(&mmc_base->stat) & CC_MASK)) {
244 if (get_timer(0) - start > MAX_RETRY_MS) {
245 printf("%s: timedout waiting for cc!\n", __func__);
246 return;
247 }
248 }
de941241
SG		 249 writel(CC_MASK, &mmc_base->stat)
250 ;
251 writel(MMC_CMD0, &mmc_base->cmd)
252 ;
eb9a28f6
NM		 253 start = get_timer(0);
254 while (!(readl(&mmc_base->stat) & CC_MASK)) {
255 if (get_timer(0) - start > MAX_RETRY_MS) {
256 printf("%s: timedout waiting for cc2!\n", __func__);
257 return;
258 }
259 }
de941241
SG		 260 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
261}
262
b5944817 263#if CONFIG_IS_ENABLED(DM_MMC)
8fc238bf
JJH		 264static void omap_hsmmc_set_timing(struct mmc *mmc)
265{
266 u32 val;
267 struct hsmmc *mmc_base;
268 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
269
270 mmc_base = priv->base_addr;
271
272 val = readl(&mmc_base->ac12);
273 val &= ~AC12_UHSMC_MASK;
274 priv->mode = mmc->selected_mode;
275
9b3fc218
KVA		 276 if (mmc_is_mode_ddr(priv->mode))
277 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
278 else
279 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
280
8fc238bf
JJH		 281 switch (priv->mode) {
282 case MMC_HS_200:
283 case UHS_SDR104:
284 val |= AC12_UHSMC_SDR104;
285 break;
286 case UHS_SDR50:
287 val |= AC12_UHSMC_SDR50;
288 break;
289 case MMC_DDR_52:
290 case UHS_DDR50:
291 val |= AC12_UHSMC_DDR50;
292 break;
293 case SD_HS:
294 case MMC_HS_52:
295 case UHS_SDR25:
296 val |= AC12_UHSMC_SDR25;
297 break;
298 case MMC_LEGACY:
299 case MMC_HS:
300 case SD_LEGACY:
301 case UHS_SDR12:
302 val |= AC12_UHSMC_SDR12;
303 break;
304 default:
305 val |= AC12_UHSMC_RES;
306 break;
307 }
308 writel(val, &mmc_base->ac12);
309}
310
b5944817
KVA		 311static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
312{
313 struct hsmmc *mmc_base;
314 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
315 u32 val;
316
317 mmc_base = priv->base_addr;
318
319 val = readl(&mmc_base->hctl) & ~SDVS_MASK;
320
321 switch (priv->iov) {
322 case IOV_3V3:
323 val |= SDVS_3V3;
324 break;
325 case IOV_3V0:
326 val |= SDVS_3V0;
327 break;
328 case IOV_1V8:
329 val |= SDVS_1V8;
330 break;
331 }
332
333 writel(val, &mmc_base->hctl);
334}
335
336static void omap_hsmmc_set_capabilities(struct mmc *mmc)
337{
338 struct hsmmc *mmc_base;
339 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
340 u32 val;
341
342 mmc_base = priv->base_addr;
343 val = readl(&mmc_base->capa);
344
345 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
346 val |= (VS30_3V0SUP | VS18_1V8SUP);
347 priv->iov = IOV_3V0;
348 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
349 val |= VS30_3V0SUP;
350 val &= ~VS18_1V8SUP;
351 priv->iov = IOV_3V0;
352 } else {
353 val |= VS18_1V8SUP;
354 val &= ~VS30_3V0SUP;
355 priv->iov = IOV_1V8;
356 }
357
358 writel(val, &mmc_base->capa);
359}
14761cae
JJH		 360
361#ifdef MMC_SUPPORTS_TUNING
362static void omap_hsmmc_disable_tuning(struct mmc *mmc)
363{
364 struct hsmmc *mmc_base;
365 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
366 u32 val;
367
368 mmc_base = priv->base_addr;
369 val = readl(&mmc_base->ac12);
370 val &= ~(AC12_SCLK_SEL);
371 writel(val, &mmc_base->ac12);
372
373 val = readl(&mmc_base->dll);
374 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
375 writel(val, &mmc_base->dll);
376}
377
378static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
379{
380 int i;
381 struct hsmmc *mmc_base;
382 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
383 u32 val;
384
385 mmc_base = priv->base_addr;
386 val = readl(&mmc_base->dll);
387 val |= DLL_FORCE_VALUE;
388 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
389 val |= (count << DLL_FORCE_SR_C_SHIFT);
390 writel(val, &mmc_base->dll);
391
392 val |= DLL_CALIB;
393 writel(val, &mmc_base->dll);
394 for (i = 0; i < 1000; i++) {
395 if (readl(&mmc_base->dll) & DLL_CALIB)
396 break;
397 }
398 val &= ~DLL_CALIB;
399 writel(val, &mmc_base->dll);
400}
401
402static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
403{
404 struct omap_hsmmc_data *priv = dev_get_priv(dev);
405 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
406 struct mmc *mmc = upriv->mmc;
407 struct hsmmc *mmc_base;
408 u32 val;
409 u8 cur_match, prev_match = 0;
410 int ret;
411 u32 phase_delay = 0;
412 u32 start_window = 0, max_window = 0;
413 u32 length = 0, max_len = 0;
414
415 mmc_base = priv->base_addr;
416 val = readl(&mmc_base->capa2);
417
418 /* clock tuning is not needed for upto 52MHz */
419 if (!((mmc->selected_mode == MMC_HS_200) ||
420 (mmc->selected_mode == UHS_SDR104) ||
421 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
422 return 0;
423
424 val = readl(&mmc_base->dll);
425 val |= DLL_SWT;
426 writel(val, &mmc_base->dll);
427 while (phase_delay <= MAX_PHASE_DELAY) {
428 omap_hsmmc_set_dll(mmc, phase_delay);
429
430 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
431
432 if (cur_match) {
433 if (prev_match) {
434 length++;
435 } else {
436 start_window = phase_delay;
437 length = 1;
438 }
439 }
440
441 if (length > max_len) {
442 max_window = start_window;
443 max_len = length;
444 }
445
446 prev_match = cur_match;
447 phase_delay += 4;
448 }
449
450 if (!max_len) {
451 ret = -EIO;
452 goto tuning_error;
453 }
454
455 val = readl(&mmc_base->ac12);
456 if (!(val & AC12_SCLK_SEL)) {
457 ret = -EIO;
458 goto tuning_error;
459 }
460
461 phase_delay = max_window + 4 * ((3 * max_len) >> 2);
462 omap_hsmmc_set_dll(mmc, phase_delay);
463
464 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
465 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
466
467 return 0;
468
469tuning_error:
470
471 omap_hsmmc_disable_tuning(mmc);
472 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
473 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
474
475 return ret;
476}
477#endif
b5944817
KVA		 478#endif
479
2faa1a30
JJH		 480static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
481{
482 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
483 struct hsmmc *mmc_base = priv->base_addr;
484 u32 irq_mask = INT_EN_MASK;
485
486 /*
487 * TODO: Errata i802 indicates only DCRC interrupts can occur during
488 * tuning procedure and DCRC should be disabled. But see occurences
489 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
490 * interrupts occur along with BRR, so the data is actually in the
491 * buffer. It has to be debugged why these interrutps occur
492 */
493 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
494 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
495
496 writel(irq_mask, &mmc_base->ie);
497}
498
ab769f22 499static int omap_hsmmc_init_setup(struct mmc *mmc)
de941241 500{
ae000e23 501 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
cc22b0c0 502 struct hsmmc *mmc_base;
de941241
SG		 503 unsigned int reg_val;
504 unsigned int dsor;
eb9a28f6 505 ulong start;
de941241 506
ae000e23 507 mmc_base = priv->base_addr;
14fa2dd0 508 mmc_board_init(mmc);
de941241
SG		 509
510 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
511 &mmc_base->sysconfig);
eb9a28f6
NM		 512 start = get_timer(0);
513 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
514 if (get_timer(0) - start > MAX_RETRY_MS) {
515 printf("%s: timedout waiting for cc2!\n", __func__);
915ffa52 516 return -ETIMEDOUT;
eb9a28f6
NM		 517 }
518 }
de941241 519 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6
NM		 520 start = get_timer(0);
521 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
522 if (get_timer(0) - start > MAX_RETRY_MS) {
523 printf("%s: timedout waiting for softresetall!\n",
524 __func__);
915ffa52 525 return -ETIMEDOUT;
eb9a28f6
NM		 526 }
527 }
f0d53e88
KVA		 528#ifndef CONFIG_OMAP34XX
529 reg_val = readl(&mmc_base->hl_hwinfo);
530 if (reg_val & MADMA_EN)
531 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
532#endif
b5944817
KVA		 533
534#if CONFIG_IS_ENABLED(DM_MMC)
535 omap_hsmmc_set_capabilities(mmc);
536 omap_hsmmc_conf_bus_power(mmc);
537#else
de941241
SG		 538 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
539 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
540 &mmc_base->capa);
b5944817 541#endif
de941241
SG		 542
543 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
544
545 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
546 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
547 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
548
549 dsor = 240;
550 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
29171dcf 551 (ICE_STOP | DTO_15THDTO));
de941241
SG		 552 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
553 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
eb9a28f6
NM		 554 start = get_timer(0);
555 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
556 if (get_timer(0) - start > MAX_RETRY_MS) {
557 printf("%s: timedout waiting for ics!\n", __func__);
915ffa52 558 return -ETIMEDOUT;
eb9a28f6
NM		 559 }
560 }
de941241
SG		 561 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
562
563 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
564
2faa1a30 565 mmc_enable_irq(mmc, NULL);
de941241
SG		 566 mmc_init_stream(mmc_base);
567
568 return 0;
569}
570
25c719e2
GI		 571/*
572 * MMC controller internal finite state machine reset
573 *
574 * Used to reset command or data internal state machines, using respectively
575 * SRC or SRD bit of SYSCTL register
576 */
577static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
578{
579 ulong start;
580
581 mmc_reg_out(&mmc_base->sysctl, bit, bit);
582
61a6cc27
OT		 583 /*
584 * CMD(DAT) lines reset procedures are slightly different
585 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
586 * According to OMAP3 TRM:
587 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
588 * returns to 0x0.
589 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
590 * procedure steps must be as follows:
591 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
592 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
593 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
594 * 3. Wait until the SRC (SRD) bit returns to 0x0
595 * (reset procedure is completed).
596 */
597#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
dce55b93 598 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
61a6cc27
OT		 599 if (!(readl(&mmc_base->sysctl) & bit)) {
600 start = get_timer(0);
601 while (!(readl(&mmc_base->sysctl) & bit)) {
a4efd737 602 if (get_timer(0) - start > MMC_TIMEOUT_MS)
61a6cc27
OT		 603 return;
604 }
605 }
606#endif
25c719e2
GI		 607 start = get_timer(0);
608 while ((readl(&mmc_base->sysctl) & bit) != 0) {
609 if (get_timer(0) - start > MAX_RETRY_MS) {
610 printf("%s: timedout waiting for sysctl %x to clear\n",
611 __func__, bit);
612 return;
613 }
614 }
615}
f0d53e88
KVA		 616
617#ifndef CONFIG_OMAP34XX
618static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
619{
620 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
621 struct omap_hsmmc_adma_desc *desc;
622 u8 attr;
623
624 desc = &priv->adma_desc_table[priv->desc_slot];
625
626 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
627 if (!end)
628 priv->desc_slot++;
629 else
630 attr |= ADMA_DESC_ATTR_END;
631
632 desc->len = len;
633 desc->addr = (u32)buf;
634 desc->reserved = 0;
635 desc->attr = attr;
636}
637
638static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
639 struct mmc_data *data)
640{
641 uint total_len = data->blocksize * data->blocks;
642 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
643 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
644 int i = desc_count;
645 char *buf;
646
647 priv->desc_slot = 0;
648 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
649 memalign(ARCH_DMA_MINALIGN, desc_count *
650 sizeof(struct omap_hsmmc_adma_desc));
651
652 if (data->flags & MMC_DATA_READ)
653 buf = data->dest;
654 else
655 buf = (char *)data->src;
656
657 while (--i) {
658 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
659 buf += ADMA_MAX_LEN;
660 total_len -= ADMA_MAX_LEN;
661 }
662
663 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
664
665 flush_dcache_range((long)priv->adma_desc_table,
666 (long)priv->adma_desc_table +
667 ROUND(desc_count *
668 sizeof(struct omap_hsmmc_adma_desc),
669 ARCH_DMA_MINALIGN));
670}
671
672static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
673{
674 struct hsmmc *mmc_base;
675 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
676 u32 val;
677 char *buf;
678
679 mmc_base = priv->base_addr;
680 omap_hsmmc_prepare_adma_table(mmc, data);
681
682 if (data->flags & MMC_DATA_READ)
683 buf = data->dest;
684 else
685 buf = (char *)data->src;
686
687 val = readl(&mmc_base->hctl);
688 val |= DMA_SELECT;
689 writel(val, &mmc_base->hctl);
690
691 val = readl(&mmc_base->con);
692 val |= DMA_MASTER;
693 writel(val, &mmc_base->con);
694
695 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
696
697 flush_dcache_range((u32)buf,
698 (u32)buf +
699 ROUND(data->blocksize * data->blocks,
700 ARCH_DMA_MINALIGN));
701}
702
703static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
704{
705 struct hsmmc *mmc_base;
706 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
707 u32 val;
708
709 mmc_base = priv->base_addr;
710
711 val = readl(&mmc_base->con);
712 val &= ~DMA_MASTER;
713 writel(val, &mmc_base->con);
714
715 val = readl(&mmc_base->hctl);
716 val &= ~DMA_SELECT;
717 writel(val, &mmc_base->hctl);
718
719 kfree(priv->adma_desc_table);
720}
721#else
722#define omap_hsmmc_adma_desc
723#define omap_hsmmc_prepare_adma_table
724#define omap_hsmmc_prepare_data
725#define omap_hsmmc_dma_cleanup
726#endif
727
c4d660d4 728#if !CONFIG_IS_ENABLED(DM_MMC)
ab769f22 729static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
de941241
SG		 730 struct mmc_data *data)
731{
ae000e23 732 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
b5511d6c
JJH		 733#else
734static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
735 struct mmc_data *data)
736{
737 struct omap_hsmmc_data *priv = dev_get_priv(dev);
f0d53e88
KVA		 738 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
739 struct mmc *mmc = upriv->mmc;
b5511d6c 740#endif
cc22b0c0 741 struct hsmmc *mmc_base;
de941241 742 unsigned int flags, mmc_stat;
eb9a28f6 743 ulong start;
de941241 744
ae000e23 745 mmc_base = priv->base_addr;
866bb984
KVA		 746
747 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
748 return 0;
749
eb9a28f6 750 start = get_timer(0);
a7778f8f 751 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
eb9a28f6 752 if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f
TR		 753 printf("%s: timedout waiting on cmd inhibit to clear\n",
754 __func__);
915ffa52 755 return -ETIMEDOUT;
eb9a28f6
NM		 756 }
757 }
de941241 758 writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6
NM		 759 start = get_timer(0);
760 while (readl(&mmc_base->stat)) {
761 if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de
GI		 762 printf("%s: timedout waiting for STAT (%x) to clear\n",
763 __func__, readl(&mmc_base->stat));
915ffa52 764 return -ETIMEDOUT;
eb9a28f6
NM		 765 }
766 }
de941241
SG		 767 /*
768 * CMDREG
769 * CMDIDX[13:8] : Command index
770 * DATAPRNT[5] : Data Present Select
771 * ENCMDIDX[4] : Command Index Check Enable
772 * ENCMDCRC[3] : Command CRC Check Enable
773 * RSPTYP[1:0]
774 * 00 = No Response
775 * 01 = Length 136
776 * 10 = Length 48
777 * 11 = Length 48 Check busy after response
778 */
779 /* Delay added before checking the status of frq change
780 * retry not supported by mmc.c(core file)
781 */
782 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
783 udelay(50000); /* wait 50 ms */
784
785 if (!(cmd->resp_type & MMC_RSP_PRESENT))
786 flags = 0;
787 else if (cmd->resp_type & MMC_RSP_136)
788 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
789 else if (cmd->resp_type & MMC_RSP_BUSY)
790 flags = RSP_TYPE_LGHT48B;
791 else
792 flags = RSP_TYPE_LGHT48;
793
794 /* enable default flags */
795 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
29171dcf
KVA		 796 MSBS_SGLEBLK);
797 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
de941241
SG		 798
799 if (cmd->resp_type & MMC_RSP_CRC)
800 flags |= CCCE_CHECK;
801 if (cmd->resp_type & MMC_RSP_OPCODE)
802 flags |= CICE_CHECK;
803
804 if (data) {
805 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
806 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
866bb984 807 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
de941241
SG		 808 data->blocksize = 512;
809 writel(data->blocksize | (data->blocks << 16),
810 &mmc_base->blk);
811 } else
812 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
813
814 if (data->flags & MMC_DATA_READ)
815 flags |= (DP_DATA | DDIR_READ);
816 else
817 flags |= (DP_DATA | DDIR_WRITE);
f0d53e88
KVA		 818
819#ifndef CONFIG_OMAP34XX
820 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
821 !mmc_is_tuning_cmd(cmd->cmdidx)) {
822 omap_hsmmc_prepare_data(mmc, data);
823 flags |= DE_ENABLE;
824 }
825#endif
de941241
SG		 826 }
827
2faa1a30
JJH		 828 mmc_enable_irq(mmc, cmd);
829
de941241 830 writel(cmd->cmdarg, &mmc_base->arg);
152ba363 831 udelay(20); /* To fix "No status update" error on eMMC */
de941241
SG		 832 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
833
eb9a28f6 834 start = get_timer(0);
de941241
SG		 835 do {
836 mmc_stat = readl(&mmc_base->stat);
f0d53e88 837 if (get_timer(start) > MAX_RETRY_MS) {
eb9a28f6 838 printf("%s : timeout: No status update\n", __func__);
915ffa52 839 return -ETIMEDOUT;
eb9a28f6
NM		 840 }
841 } while (!mmc_stat);
de941241 842
25c719e2
GI		 843 if ((mmc_stat & IE_CTO) != 0) {
844 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
915ffa52 845 return -ETIMEDOUT;
25c719e2 846 } else if ((mmc_stat & ERRI_MASK) != 0)
de941241
SG		 847 return -1;
848
849 if (mmc_stat & CC_MASK) {
850 writel(CC_MASK, &mmc_base->stat);
851 if (cmd->resp_type & MMC_RSP_PRESENT) {
852 if (cmd->resp_type & MMC_RSP_136) {
853 /* response type 2 */
854 cmd->response[3] = readl(&mmc_base->rsp10);
855 cmd->response[2] = readl(&mmc_base->rsp32);
856 cmd->response[1] = readl(&mmc_base->rsp54);
857 cmd->response[0] = readl(&mmc_base->rsp76);
858 } else
859 /* response types 1, 1b, 3, 4, 5, 6 */
860 cmd->response[0] = readl(&mmc_base->rsp10);
861 }
862 }
863
f0d53e88
KVA		 864#ifndef CONFIG_OMAP34XX
865 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
866 !mmc_is_tuning_cmd(cmd->cmdidx)) {
867 u32 sz_mb, timeout;
868
869 if (mmc_stat & IE_ADMAE) {
870 omap_hsmmc_dma_cleanup(mmc);
871 return -EIO;
872 }
873
874 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
875 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
876 if (timeout < MAX_RETRY_MS)
877 timeout = MAX_RETRY_MS;
878
879 start = get_timer(0);
880 do {
881 mmc_stat = readl(&mmc_base->stat);
882 if (mmc_stat & TC_MASK) {
883 writel(readl(&mmc_base->stat) | TC_MASK,
884 &mmc_base->stat);
885 break;
886 }
887 if (get_timer(start) > timeout) {
888 printf("%s : DMA timeout: No status update\n",
889 __func__);
890 return -ETIMEDOUT;
891 }
892 } while (1);
893
894 omap_hsmmc_dma_cleanup(mmc);
895 return 0;
896 }
897#endif
898
de941241
SG		 899 if (data && (data->flags & MMC_DATA_READ)) {
900 mmc_read_data(mmc_base, data->dest,
901 data->blocksize * data->blocks);
902 } else if (data && (data->flags & MMC_DATA_WRITE)) {
903 mmc_write_data(mmc_base, data->src,
904 data->blocksize * data->blocks);
905 }
906 return 0;
907}
908
933efe64 909static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
de941241
SG		 910{
911 unsigned int *output_buf = (unsigned int *)buf;
912 unsigned int mmc_stat;
913 unsigned int count;
914
915 /*
916 * Start Polled Read
917 */
918 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
919 count /= 4;
920
921 while (size) {
eb9a28f6 922 ulong start = get_timer(0);
de941241
SG		 923 do {
924 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 925 if (get_timer(0) - start > MAX_RETRY_MS) {
926 printf("%s: timedout waiting for status!\n",
927 __func__);
915ffa52 928 return -ETIMEDOUT;
eb9a28f6 929 }
de941241
SG		 930 } while (mmc_stat == 0);
931
25c719e2
GI		 932 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
933 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
934
de941241
SG		 935 if ((mmc_stat & ERRI_MASK) != 0)
936 return 1;
937
938 if (mmc_stat & BRR_MASK) {
939 unsigned int k;
940
941 writel(readl(&mmc_base->stat) | BRR_MASK,
942 &mmc_base->stat);
943 for (k = 0; k < count; k++) {
944 *output_buf = readl(&mmc_base->data);
945 output_buf++;
946 }
947 size -= (count*4);
948 }
949
950 if (mmc_stat & BWR_MASK)
951 writel(readl(&mmc_base->stat) | BWR_MASK,
952 &mmc_base->stat);
953
954 if (mmc_stat & TC_MASK) {
955 writel(readl(&mmc_base->stat) | TC_MASK,
956 &mmc_base->stat);
957 break;
958 }
959 }
960 return 0;
961}
962
933efe64
S		 963static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
964 unsigned int size)
de941241
SG		 965{
966 unsigned int *input_buf = (unsigned int *)buf;
967 unsigned int mmc_stat;
968 unsigned int count;
969
970 /*
152ba363 971 * Start Polled Write
de941241
SG		 972 */
973 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
974 count /= 4;
975
976 while (size) {
eb9a28f6 977 ulong start = get_timer(0);
de941241
SG		 978 do {
979 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 980 if (get_timer(0) - start > MAX_RETRY_MS) {
981 printf("%s: timedout waiting for status!\n",
982 __func__);
915ffa52 983 return -ETIMEDOUT;
eb9a28f6 984 }
de941241
SG		 985 } while (mmc_stat == 0);
986
25c719e2
GI		 987 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
988 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
989
de941241
SG		 990 if ((mmc_stat & ERRI_MASK) != 0)
991 return 1;
992
993 if (mmc_stat & BWR_MASK) {
994 unsigned int k;
995
996 writel(readl(&mmc_base->stat) | BWR_MASK,
997 &mmc_base->stat);
998 for (k = 0; k < count; k++) {
999 writel(*input_buf, &mmc_base->data);
1000 input_buf++;
1001 }
1002 size -= (count*4);
1003 }
1004
1005 if (mmc_stat & BRR_MASK)
1006 writel(readl(&mmc_base->stat) | BRR_MASK,
1007 &mmc_base->stat);
1008
1009 if (mmc_stat & TC_MASK) {
1010 writel(readl(&mmc_base->stat) | TC_MASK,
1011 &mmc_base->stat);
1012 break;
1013 }
1014 }
1015 return 0;
1016}
1017
5baf543e
JJH		 1018static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1019{
1020 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1021}
1022
1023static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1024{
1025 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1026}
1027
1028static void omap_hsmmc_set_clock(struct mmc *mmc)
1029{
1030 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1031 struct hsmmc *mmc_base;
1032 unsigned int dsor = 0;
1033 ulong start;
1034
1035 mmc_base = priv->base_addr;
1036 omap_hsmmc_stop_clock(mmc_base);
1037
1038 /* TODO: Is setting DTO required here? */
1039 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1040 (ICE_STOP | DTO_15THDTO));
1041
1042 if (mmc->clock != 0) {
1043 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1044 if (dsor > CLKD_MAX)
1045 dsor = CLKD_MAX;
1046 } else {
1047 dsor = CLKD_MAX;
1048 }
1049
1050 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1051 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1052
1053 start = get_timer(0);
1054 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1055 if (get_timer(0) - start > MAX_RETRY_MS) {
1056 printf("%s: timedout waiting for ics!\n", __func__);
1057 return;
1058 }
1059 }
1060
1061 priv->clock = mmc->clock;
1062 omap_hsmmc_start_clock(mmc_base);
1063}
1064
48a2f114 1065static void omap_hsmmc_set_bus_width(struct mmc *mmc)
de941241 1066{
ae000e23 1067 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
cc22b0c0 1068 struct hsmmc *mmc_base;
de941241 1069
ae000e23 1070 mmc_base = priv->base_addr;
de941241
SG		 1071 /* configue bus width */
1072 switch (mmc->bus_width) {
1073 case 8:
1074 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1075 &mmc_base->con);
1076 break;
1077
1078 case 4:
1079 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1080 &mmc_base->con);
1081 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1082 &mmc_base->hctl);
1083 break;
1084
1085 case 1:
1086 default:
1087 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1088 &mmc_base->con);
1089 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1090 &mmc_base->hctl);
1091 break;
1092 }
1093
48a2f114
KVA		 1094 priv->bus_width = mmc->bus_width;
1095}
1096
1097#if !CONFIG_IS_ENABLED(DM_MMC)
1098static int omap_hsmmc_set_ios(struct mmc *mmc)
1099{
1100 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1101#else
1102static int omap_hsmmc_set_ios(struct udevice *dev)
1103{
1104 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1105 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1106 struct mmc *mmc = upriv->mmc;
1107#endif
1108
1109 if (priv->bus_width != mmc->bus_width)
1110 omap_hsmmc_set_bus_width(mmc);
1111
5baf543e
JJH		 1112 if (priv->clock != mmc->clock)
1113 omap_hsmmc_set_clock(mmc);
07b0b9c0 1114
8fc238bf
JJH		 1115#if CONFIG_IS_ENABLED(DM_MMC)
1116 if (priv->mode != mmc->selected_mode)
1117 omap_hsmmc_set_timing(mmc);
1118#endif
07b0b9c0 1119 return 0;
de941241
SG		 1120}
1121
ab769f22 1122#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 1123#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c 1124static int omap_hsmmc_getcd(struct udevice *dev)
a9d6a7e2 1125{
b5511d6c 1126 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 1127 int value;
1128
1129 value = dm_gpio_get_value(&priv->cd_gpio);
1130 /* if no CD return as 1 */
1131 if (value < 0)
1132 return 1;
1133
1134 if (priv->cd_inverted)
1135 return !value;
1136 return value;
1137}
1138
b5511d6c 1139static int omap_hsmmc_getwp(struct udevice *dev)
a9d6a7e2 1140{
b5511d6c 1141 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 1142 int value;
1143
1144 value = dm_gpio_get_value(&priv->wp_gpio);
1145 /* if no WP return as 0 */
1146 if (value < 0)
1147 return 0;
1148 return value;
1149}
1150#else
ab769f22
PA		 1151static int omap_hsmmc_getcd(struct mmc *mmc)
1152{
ae000e23 1153 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 1154 int cd_gpio;
1155
1156 /* if no CD return as 1 */
ae000e23 1157 cd_gpio = priv->cd_gpio;
ab769f22
PA		 1158 if (cd_gpio < 0)
1159 return 1;
1160
0b03a931
IG		 1161 /* NOTE: assumes card detect signal is active-low */
1162 return !gpio_get_value(cd_gpio);
ab769f22
PA		 1163}
1164
1165static int omap_hsmmc_getwp(struct mmc *mmc)
1166{
ae000e23 1167 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 1168 int wp_gpio;
1169
1170 /* if no WP return as 0 */
ae000e23 1171 wp_gpio = priv->wp_gpio;
ab769f22
PA		 1172 if (wp_gpio < 0)
1173 return 0;
1174
0b03a931 1175 /* NOTE: assumes write protect signal is active-high */
ab769f22
PA		 1176 return gpio_get_value(wp_gpio);
1177}
1178#endif
a9d6a7e2 1179#endif
ab769f22 1180
c4d660d4 1181#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c
JJH		 1182static const struct dm_mmc_ops omap_hsmmc_ops = {
1183 .send_cmd = omap_hsmmc_send_cmd,
1184 .set_ios = omap_hsmmc_set_ios,
1185#ifdef OMAP_HSMMC_USE_GPIO
1186 .get_cd = omap_hsmmc_getcd,
1187 .get_wp = omap_hsmmc_getwp,
1188#endif
14761cae
JJH		 1189#ifdef MMC_SUPPORTS_TUNING
1190 .execute_tuning = omap_hsmmc_execute_tuning,
1191#endif
b5511d6c
JJH		 1192};
1193#else
ab769f22
PA		 1194static const struct mmc_ops omap_hsmmc_ops = {
1195 .send_cmd = omap_hsmmc_send_cmd,
1196 .set_ios = omap_hsmmc_set_ios,
1197 .init = omap_hsmmc_init_setup,
1198#ifdef OMAP_HSMMC_USE_GPIO
1199 .getcd = omap_hsmmc_getcd,
1200 .getwp = omap_hsmmc_getwp,
1201#endif
1202};
b5511d6c 1203#endif
ab769f22 1204
c4d660d4 1205#if !CONFIG_IS_ENABLED(DM_MMC)
e3913f56
NK		 1206int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1207 int wp_gpio)
de941241 1208{
93bfd616 1209 struct mmc *mmc;
ae000e23 1210 struct omap_hsmmc_data *priv;
93bfd616
PA		 1211 struct mmc_config *cfg;
1212 uint host_caps_val;
1213
ae000e23
JJH		 1214 priv = malloc(sizeof(*priv));
1215 if (priv == NULL)
93bfd616 1216 return -1;
de941241 1217
5a20397b 1218 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
de941241
SG		 1219
1220 switch (dev_index) {
1221 case 0:
ae000e23 1222 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 1223 break;
1037d585 1224#ifdef OMAP_HSMMC2_BASE
de941241 1225 case 1:
ae000e23 1226 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
152ba363 1227#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
3891a54f 1228 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
3b68939f
RQ		 1229 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1230 defined(CONFIG_HSMMC2_8BIT)
152ba363
LP		 1231 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1232 host_caps_val |= MMC_MODE_8BIT;
1233#endif
de941241 1234 break;
1037d585
TR		 1235#endif
1236#ifdef OMAP_HSMMC3_BASE
de941241 1237 case 2:
ae000e23 1238 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
3891a54f 1239#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
152ba363
LP		 1240 /* Enable 8-bit interface for eMMC on DRA7XX */
1241 host_caps_val |= MMC_MODE_8BIT;
1242#endif
de941241 1243 break;
1037d585 1244#endif
de941241 1245 default:
ae000e23 1246 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241
SG		 1247 return 1;
1248 }
ab769f22
PA		 1249#ifdef OMAP_HSMMC_USE_GPIO
1250 /* on error gpio values are set to -1, which is what we want */
ae000e23
JJH		 1251 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1252 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
ab769f22 1253#endif
173ddc5b 1254
ae000e23 1255 cfg = &priv->cfg;
de941241 1256
93bfd616
PA		 1257 cfg->name = "OMAP SD/MMC";
1258 cfg->ops = &omap_hsmmc_ops;
1259
1260 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1261 cfg->host_caps = host_caps_val & ~host_caps_mask;
1262
1263 cfg->f_min = 400000;
bbbc1ae9
JS		 1264
1265 if (f_max != 0)
93bfd616 1266 cfg->f_max = f_max;
bbbc1ae9 1267 else {
93bfd616
PA		 1268 if (cfg->host_caps & MMC_MODE_HS) {
1269 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1270 cfg->f_max = 52000000;
bbbc1ae9 1271 else
93bfd616 1272 cfg->f_max = 26000000;
bbbc1ae9 1273 } else
93bfd616 1274 cfg->f_max = 20000000;
bbbc1ae9 1275 }
de941241 1276
93bfd616 1277 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
8feafcc4 1278
4ca9244d
JR		 1279#if defined(CONFIG_OMAP34XX)
1280 /*
1281 * Silicon revs 2.1 and older do not support multiblock transfers.
1282 */
1283 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
93bfd616 1284 cfg->b_max = 1;
4ca9244d 1285#endif
ae000e23 1286 mmc = mmc_create(cfg, priv);
93bfd616
PA		 1287 if (mmc == NULL)
1288 return -1;
de941241
SG		 1289
1290 return 0;
1291}
a9d6a7e2 1292#else
2558c049 1293#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 1294static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1295{
3d673ffc
JJH		 1296 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1297 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2 1298 const void *fdt = gd->fdt_blob;
e160f7d4 1299 int node = dev_of_offset(dev);
a9d6a7e2
M		 1300 int val;
1301
a821c4af
SG		 1302 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1303 sizeof(struct hsmmc *),
741726ae 1304 MAP_NOCACHE);
a9d6a7e2
M		 1305
1306 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1307 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1308 if (val < 0) {
1309 printf("error: bus-width property missing\n");
1310 return -ENOENT;
1311 }
1312
1313 switch (val) {
1314 case 0x8:
1315 cfg->host_caps |= MMC_MODE_8BIT;
1316 case 0x4:
1317 cfg->host_caps |= MMC_MODE_4BIT;
1318 break;
1319 default:
1320 printf("error: invalid bus-width property\n");
1321 return -ENOENT;
1322 }
1323
1324 cfg->f_min = 400000;
1325 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1326 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1327 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
b5944817
KVA		 1328 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1329 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1330 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1331 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
a9d6a7e2 1332
4de2de51 1333#ifdef OMAP_HSMMC_USE_GPIO
2558c049 1334 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
4de2de51 1335#endif
a9d6a7e2
M		 1336
1337 return 0;
1338}
2558c049 1339#endif
a9d6a7e2 1340
17c9a1c1
JJH		 1341#ifdef CONFIG_BLK
1342
1343static int omap_hsmmc_bind(struct udevice *dev)
1344{
1345 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1346
1347 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1348}
1349#endif
a9d6a7e2
M		 1350static int omap_hsmmc_probe(struct udevice *dev)
1351{
3d673ffc 1352 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
a9d6a7e2
M		 1353 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1354 struct omap_hsmmc_data *priv = dev_get_priv(dev);
3d673ffc 1355 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2
M		 1356 struct mmc *mmc;
1357
a9d6a7e2 1358 cfg->name = "OMAP SD/MMC";
2558c049
LV		 1359 priv->base_addr = plat->base_addr;
1360#ifdef OMAP_HSMMC_USE_GPIO
1361 priv->cd_inverted = plat->cd_inverted;
1362#endif
a9d6a7e2 1363
17c9a1c1
JJH		 1364#ifdef CONFIG_BLK
1365 mmc = &plat->mmc;
1366#else
a9d6a7e2
M		 1367 mmc = mmc_create(cfg, priv);
1368 if (mmc == NULL)
1369 return -1;
17c9a1c1 1370#endif
a9d6a7e2 1371
2558c049 1372#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
5cc6a245
M		 1373 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1374 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1375#endif
1376
cffe5d86 1377 mmc->dev = dev;
a9d6a7e2
M		 1378 upriv->mmc = mmc;
1379
b5511d6c 1380 return omap_hsmmc_init_setup(mmc);
a9d6a7e2
M		 1381}
1382
2558c049 1383#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2 1384static const struct udevice_id omap_hsmmc_ids[] = {
741726ae
JJH		 1385 { .compatible = "ti,omap3-hsmmc" },
1386 { .compatible = "ti,omap4-hsmmc" },
1387 { .compatible = "ti,am33xx-hsmmc" },
a9d6a7e2
M		 1388 { }
1389};
2558c049 1390#endif
a9d6a7e2
M		 1391
1392U_BOOT_DRIVER(omap_hsmmc) = {
1393 .name = "omap_hsmmc",
1394 .id = UCLASS_MMC,
2558c049 1395#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 1396 .of_match = omap_hsmmc_ids,
1397 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2558c049
LV		 1398 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1399#endif
17c9a1c1
JJH		 1400#ifdef CONFIG_BLK
1401 .bind = omap_hsmmc_bind,
1402#endif
b5511d6c 1403 .ops = &omap_hsmmc_ops,
a9d6a7e2
M		 1404 .probe = omap_hsmmc_probe,
1405 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
cbcb1701 1406 .flags = DM_FLAG_PRE_RELOC,
a9d6a7e2
M		 1407};
1408#endif
"Das U-Boot" Source Tree