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Commit | Line | Data |
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a8cb4fb5 SG |
1 | /* |
2 | * Copyright (c) 2013 Google, Inc | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <clk.h> | |
9 | #include <dm.h> | |
bfeb443e | 10 | #include <dt-structs.h> |
a8cb4fb5 SG |
11 | #include <dwmmc.h> |
12 | #include <errno.h> | |
bfeb443e | 13 | #include <mapmem.h> |
e1efec4e | 14 | #include <pwrseq.h> |
a8cb4fb5 | 15 | #include <syscon.h> |
e1efec4e | 16 | #include <asm/gpio.h> |
a8cb4fb5 SG |
17 | #include <asm/arch/clock.h> |
18 | #include <asm/arch/periph.h> | |
19 | #include <linux/err.h> | |
20 | ||
21 | DECLARE_GLOBAL_DATA_PTR; | |
22 | ||
f6e41d17 | 23 | struct rockchip_mmc_plat { |
bfeb443e SG |
24 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
25 | struct dtd_rockchip_rk3288_dw_mshc dtplat; | |
26 | #endif | |
f6e41d17 SG |
27 | struct mmc_config cfg; |
28 | struct mmc mmc; | |
29 | }; | |
30 | ||
a8cb4fb5 | 31 | struct rockchip_dwmmc_priv { |
135aa950 | 32 | struct clk clk; |
a8cb4fb5 | 33 | struct dwmci_host host; |
6809b04f SG |
34 | int fifo_depth; |
35 | bool fifo_mode; | |
36 | u32 minmax[2]; | |
a8cb4fb5 SG |
37 | }; |
38 | ||
39 | static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) | |
40 | { | |
41 | struct udevice *dev = host->priv; | |
42 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); | |
43 | int ret; | |
44 | ||
135aa950 | 45 | ret = clk_set_rate(&priv->clk, freq); |
a8cb4fb5 | 46 | if (ret < 0) { |
419b0801 | 47 | debug("%s: err=%d\n", __func__, ret); |
a8cb4fb5 SG |
48 | return ret; |
49 | } | |
50 | ||
51 | return freq; | |
52 | } | |
53 | ||
54 | static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) | |
55 | { | |
bfeb443e | 56 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
a8cb4fb5 SG |
57 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); |
58 | struct dwmci_host *host = &priv->host; | |
59 | ||
60 | host->name = dev->name; | |
be5f04e8 | 61 | host->ioaddr = dev_read_addr_ptr(dev); |
fd1bf8df | 62 | host->buswidth = dev_read_u32_default(dev, "bus-width", 4); |
a8cb4fb5 SG |
63 | host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; |
64 | host->priv = dev; | |
65 | ||
ace2198b | 66 | /* use non-removeable as sdcard and emmc as judgement */ |
fd1bf8df | 67 | if (dev_read_bool(dev, "non-removable")) |
6579385b | 68 | host->dev_index = 0; |
69 | else | |
ace2198b | 70 | host->dev_index = 1; |
a8cb4fb5 | 71 | |
fd1bf8df PT |
72 | priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); |
73 | ||
6809b04f SG |
74 | if (priv->fifo_depth < 0) |
75 | return -EINVAL; | |
fd1bf8df | 76 | priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); |
ff71f9ac PT |
77 | |
78 | /* | |
79 | * 'clock-freq-min-max' is deprecated | |
80 | * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) | |
81 | */ | |
fd1bf8df PT |
82 | if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { |
83 | int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); | |
ff71f9ac PT |
84 | |
85 | if (val < 0) | |
86 | return val; | |
87 | ||
88 | priv->minmax[0] = 400000; /* 400 kHz */ | |
89 | priv->minmax[1] = val; | |
90 | } else { | |
91 | debug("%s: 'clock-freq-min-max' property was deprecated.\n", | |
92 | __func__); | |
93 | } | |
bfeb443e | 94 | #endif |
a8cb4fb5 SG |
95 | return 0; |
96 | } | |
97 | ||
98 | static int rockchip_dwmmc_probe(struct udevice *dev) | |
99 | { | |
f6e41d17 | 100 | struct rockchip_mmc_plat *plat = dev_get_platdata(dev); |
a8cb4fb5 SG |
101 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
102 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); | |
103 | struct dwmci_host *host = &priv->host; | |
e1efec4e | 104 | struct udevice *pwr_dev __maybe_unused; |
a8cb4fb5 SG |
105 | int ret; |
106 | ||
bfeb443e SG |
107 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
108 | struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; | |
109 | ||
110 | host->name = dev->name; | |
111 | host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); | |
112 | host->buswidth = dtplat->bus_width; | |
113 | host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; | |
114 | host->priv = dev; | |
115 | host->dev_index = 0; | |
116 | priv->fifo_depth = dtplat->fifo_depth; | |
117 | priv->fifo_mode = 0; | |
80935298 KY |
118 | priv->minmax[0] = 400000; /* 400 kHz */ |
119 | priv->minmax[1] = dtplat->max_frequency; | |
bfeb443e SG |
120 | |
121 | ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); | |
122 | if (ret < 0) | |
123 | return ret; | |
124 | #else | |
419b0801 | 125 | ret = clk_get_by_index(dev, 0, &priv->clk); |
898d6439 | 126 | if (ret < 0) |
a8cb4fb5 | 127 | return ret; |
bfeb443e | 128 | #endif |
28637248 | 129 | host->fifoth_val = MSIZE(0x2) | |
6809b04f SG |
130 | RX_WMARK(priv->fifo_depth / 2 - 1) | |
131 | TX_WMARK(priv->fifo_depth / 2); | |
28637248 | 132 | |
6809b04f | 133 | host->fifo_mode = priv->fifo_mode; |
28637248 | 134 | |
e1efec4e SG |
135 | #ifdef CONFIG_PWRSEQ |
136 | /* Enable power if needed */ | |
137 | ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", | |
138 | &pwr_dev); | |
139 | if (!ret) { | |
140 | ret = pwrseq_set_power(pwr_dev, true); | |
141 | if (ret) | |
142 | return ret; | |
143 | } | |
144 | #endif | |
e5113c33 | 145 | dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); |
f6e41d17 | 146 | host->mmc = &plat->mmc; |
f6e41d17 | 147 | host->mmc->priv = &priv->host; |
cffe5d86 | 148 | host->mmc->dev = dev; |
a8cb4fb5 SG |
149 | upriv->mmc = host->mmc; |
150 | ||
42b37d8d | 151 | return dwmci_probe(dev); |
a8cb4fb5 SG |
152 | } |
153 | ||
f6e41d17 SG |
154 | static int rockchip_dwmmc_bind(struct udevice *dev) |
155 | { | |
f6e41d17 | 156 | struct rockchip_mmc_plat *plat = dev_get_platdata(dev); |
f6e41d17 | 157 | |
24f5aec3 | 158 | return dwmci_bind(dev, &plat->mmc, &plat->cfg); |
f6e41d17 SG |
159 | } |
160 | ||
a8cb4fb5 SG |
161 | static const struct udevice_id rockchip_dwmmc_ids[] = { |
162 | { .compatible = "rockchip,rk3288-dw-mshc" }, | |
163 | { } | |
164 | }; | |
165 | ||
166 | U_BOOT_DRIVER(rockchip_dwmmc_drv) = { | |
bfeb443e | 167 | .name = "rockchip_rk3288_dw_mshc", |
a8cb4fb5 SG |
168 | .id = UCLASS_MMC, |
169 | .of_match = rockchip_dwmmc_ids, | |
170 | .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, | |
42b37d8d | 171 | .ops = &dm_dwmci_ops, |
f6e41d17 | 172 | .bind = rockchip_dwmmc_bind, |
a8cb4fb5 SG |
173 | .probe = rockchip_dwmmc_probe, |
174 | .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), | |
f6e41d17 | 175 | .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), |
a8cb4fb5 | 176 | }; |
e1efec4e SG |
177 | |
178 | #ifdef CONFIG_PWRSEQ | |
179 | static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable) | |
180 | { | |
181 | struct gpio_desc reset; | |
182 | int ret; | |
183 | ||
184 | ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); | |
185 | if (ret) | |
186 | return ret; | |
187 | dm_gpio_set_value(&reset, 1); | |
188 | udelay(1); | |
189 | dm_gpio_set_value(&reset, 0); | |
190 | udelay(200); | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = { | |
196 | .set_power = rockchip_dwmmc_pwrseq_set_power, | |
197 | }; | |
198 | ||
199 | static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = { | |
200 | { .compatible = "mmc-pwrseq-emmc" }, | |
201 | { } | |
202 | }; | |
203 | ||
204 | U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = { | |
205 | .name = "mmc_pwrseq_emmc", | |
206 | .id = UCLASS_PWRSEQ, | |
207 | .of_match = rockchip_dwmmc_pwrseq_ids, | |
208 | .ops = &rockchip_dwmmc_pwrseq_ops, | |
209 | }; | |
210 | #endif |