[people/ms/u-boot.git] / drivers / mmc / rockchip_sdhci.c

/*
 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
 *
 * Rockchip SD Host Controller Interface
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <dt-structs.h>
#include <libfdt.h>
#include <malloc.h>
#include <mapmem.h>
#include <sdhci.h>
#include <clk.h>

DECLARE_GLOBAL_DATA_PTR;
/* 400KHz is max freq for card ID etc. Use that as min */
#define EMMC_MIN_FREQ	400000

struct rockchip_sdhc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
#endif
	struct mmc_config cfg;
	struct mmc mmc;
};

struct rockchip_sdhc {
	struct sdhci_host host;
	void *base;
};

static int arasan_sdhci_probe(struct udevice *dev)
{
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
	struct rockchip_sdhc *prv = dev_get_priv(dev);
	struct sdhci_host *host = &prv->host;
	int max_frequency, ret;
	struct clk clk;

#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;

	host->name = dev->name;
	host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
	max_frequency = dtplat->max_frequency;
	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
#else
	max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
	ret = clk_get_by_index(dev, 0, &clk);
#endif
	if (!ret) {
		ret = clk_set_rate(&clk, max_frequency);
		if (IS_ERR_VALUE(ret))
			printf("%s clk set rate fail!\n", __func__);
	} else {
		printf("%s fail to get clk\n", __func__);
	}

	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
	host->max_clk = max_frequency;

	ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);

	host->mmc = &plat->mmc;
	if (ret)
		return ret;
	host->mmc->priv = &prv->host;
	host->mmc->dev = dev;
	upriv->mmc = host->mmc;

	return sdhci_probe(dev);
}

static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	struct sdhci_host *host = dev_get_priv(dev);

	host->name = dev->name;
	host->ioaddr = dev_read_addr_ptr(dev);
#endif

	return 0;
}

static int rockchip_sdhci_bind(struct udevice *dev)
{
	struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id arasan_sdhci_ids[] = {
	{ .compatible = "arasan,sdhci-5.1" },
	{ }
};

U_BOOT_DRIVER(arasan_sdhci_drv) = {
	.name		= "rockchip_rk3399_sdhci_5_1",
	.id		= UCLASS_MMC,
	.of_match	= arasan_sdhci_ids,
	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
	.ops		= &sdhci_ops,
	.bind		= rockchip_sdhci_bind,
	.probe		= arasan_sdhci_probe,
	.priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
	.platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
};
Commit	Line	Data
79c83065 KY	1	/*
	2	* (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
	3	*
	4	* Rockchip SD Host Controller Interface
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10	#include <dm.h>
c2868212	11	#include <dt-structs.h>
79c83065 KY	12	#include <libfdt.h>
79c83065 KY	13	#include <malloc.h>
c2868212	14	#include <mapmem.h>
79c83065	15	#include <sdhci.h>
39fbb56f	16	#include <clk.h>
79c83065	17
39fbb56f	18	DECLARE_GLOBAL_DATA_PTR;
79c83065 KY	19	/* 400KHz is max freq for card ID etc. Use that as min */
	20	#define EMMC_MIN_FREQ 400000
	21
	22	struct rockchip_sdhc_plat {
c2868212 KY	23	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	24	struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
	25	#endif
79c83065 KY	26	struct mmc_config cfg;
	27	struct mmc mmc;
	28	};
	29
	30	struct rockchip_sdhc {
	31	struct sdhci_host host;
	32	void *base;
	33	};
	34
	35	static int arasan_sdhci_probe(struct udevice *dev)
	36	{
	37	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	38	struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
	39	struct rockchip_sdhc *prv = dev_get_priv(dev);
	40	struct sdhci_host *host = &prv->host;
39fbb56f KY	41	int max_frequency, ret;
	42	struct clk clk;
	43
c2868212 KY	44	#if CONFIG_IS_ENABLED(OF_PLATDATA)
c2868212 KY	45	struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
39fbb56f	46
c2868212	47	host->name = dev->name;
5184dadd	48	host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
c2868212 KY	49	max_frequency = dtplat->max_frequency;
	50	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
	51	#else
fd1bf8df	52	max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
39fbb56f	53	ret = clk_get_by_index(dev, 0, &clk);
c2868212	54	#endif
39fbb56f KY	55	if (!ret) {
	56	ret = clk_set_rate(&clk, max_frequency);
	57	if (IS_ERR_VALUE(ret))
	58	printf("%s clk set rate fail!\n", __func__);
	59	} else {
	60	printf("%s fail to get clk\n", __func__);
	61	}
79c83065	62
79c83065	63	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
6d0e34bf	64	host->max_clk = max_frequency;
79c83065	65
6d0e34bf	66	ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
79c83065 KY	67
	68	host->mmc = &plat->mmc;
	69	if (ret)
	70	return ret;
	71	host->mmc->priv = &prv->host;
	72	host->mmc->dev = dev;
	73	upriv->mmc = host->mmc;
	74
	75	return sdhci_probe(dev);
	76	}
	77
	78	static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
	79	{
c2868212	80	#if !CONFIG_IS_ENABLED(OF_PLATDATA)
79c83065 KY	81	struct sdhci_host *host = dev_get_priv(dev);
	82
	83	host->name = dev->name;
327b2b35	84	host->ioaddr = dev_read_addr_ptr(dev);
c2868212	85	#endif
79c83065 KY	86
	87	return 0;
	88	}
	89
	90	static int rockchip_sdhci_bind(struct udevice *dev)
	91	{
	92	struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
79c83065	93
24f5aec3	94	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
79c83065 KY	95	}
	96
	97	static const struct udevice_id arasan_sdhci_ids[] = {
	98	{ .compatible = "arasan,sdhci-5.1" },
	99	{ }
	100	};
	101
	102	U_BOOT_DRIVER(arasan_sdhci_drv) = {
c2868212	103	.name = "rockchip_rk3399_sdhci_5_1",
79c83065 KY	104	.id = UCLASS_MMC,
	105	.of_match = arasan_sdhci_ids,
	106	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
	107	.ops = &sdhci_ops,
	108	.bind = rockchip_sdhci_bind,
	109	.probe = arasan_sdhci_probe,
	110	.priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
	111	.platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
	112	};