[people/ms/u-boot.git] / drivers / mmc / sdhci.c

/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <leiwen@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
 */

#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
#else
void *aligned_buffer;
#endif

static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
	unsigned long timeout;

	/* Wait max 100 ms */
	timeout = 100;
	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
		if (timeout == 0) {
			printf("%s: Reset 0x%x never completed.\n",
			       __func__, (int)mask);
			return;
		}
		timeout--;
		udelay(1000);
	}
}

static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
	int i;
	if (cmd->resp_type & MMC_RSP_136) {
		/* CRC is stripped so we need to do some shifting. */
		for (i = 0; i < 4; i++) {
			cmd->response[i] = sdhci_readl(host,
					SDHCI_RESPONSE + (3-i)*4) << 8;
			if (i != 3)
				cmd->response[i] |= sdhci_readb(host,
						SDHCI_RESPONSE + (3-i)*4-1);
		}
	} else {
		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	}
}

static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
{
	int i;
	char *offs;
	for (i = 0; i < data->blocksize; i += 4) {
		offs = data->dest + i;
		if (data->flags == MMC_DATA_READ)
			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
		else
			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
	}
}

static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
				unsigned int start_addr)
{
	unsigned int stat, rdy, mask, timeout, block = 0;
#ifdef CONFIG_MMC_SDMA
	unsigned char ctrl;
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif

	timeout = 1000000;
	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR) {
			printf("%s: Error detected in status(0x%X)!\n",
			       __func__, stat);
			return -1;
		}
		if (stat & rdy) {
			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
				continue;
			sdhci_writel(host, rdy, SDHCI_INT_STATUS);
			sdhci_transfer_pio(host, data);
			data->dest += data->blocksize;
			if (++block >= data->blocks)
				break;
		}
#ifdef CONFIG_MMC_SDMA
		if (stat & SDHCI_INT_DMA_END) {
			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		}
#endif
		if (timeout-- > 0)
			udelay(10);
		else {
			printf("%s: Transfer data timeout\n", __func__);
			return -1;
		}
	} while (!(stat & SDHCI_INT_DATA_END));
	return 0;
}

/*
 * No command will be sent by driver if card is busy, so driver must wait
 * for card ready state.
 * Every time when card is busy after timeout then (last) timeout value will be
 * increased twice but only if it doesn't exceed global defined maximum.
 * Each function call will use last timeout value. Max timeout can be redefined
 * in board config file.
 */
#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
#define CONFIG_SDHCI_CMD_MAX_TIMEOUT		3200
#endif
#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT	100
#define SDHCI_READ_STATUS_TIMEOUT		1000

#ifdef CONFIG_DM_MMC_OPS
static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

#else
static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
#endif
	struct sdhci_host *host = mmc->priv;
	unsigned int stat = 0;
	int ret = 0;
	int trans_bytes = 0, is_aligned = 1;
	u32 mask, flags, mode;
	unsigned int time = 0, start_addr = 0;
	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
	unsigned start = get_timer(0);

	/* Timeout unit - ms */
	static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;

	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		mask &= ~SDHCI_DATA_INHIBIT;

	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
		if (time >= cmd_timeout) {
			printf("%s: MMC: %d busy ", __func__, mmc_dev);
			if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
				cmd_timeout += cmd_timeout;
				printf("timeout increasing to: %u ms.\n",
				       cmd_timeout);
			} else {
				puts("timeout.\n");
				return -ECOMM;
			}
		}
		time++;
		udelay(1000);
	}

	mask = SDHCI_INT_RESPONSE;
	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->resp_type & MMC_RSP_BUSY) {
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
		if (data)
			mask |= SDHCI_INT_DATA_END;
	} else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
	if (data)
		flags |= SDHCI_CMD_DATA;

	/* Set Transfer mode regarding to data flag */
	if (data != 0) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
		mode = SDHCI_TRNS_BLK_CNT_EN;
		trans_bytes = data->blocks * data->blocksize;
		if (data->blocks > 1)
			mode |= SDHCI_TRNS_MULTI;

		if (data->flags == MMC_DATA_READ)
			mode |= SDHCI_TRNS_READ;

#ifdef CONFIG_MMC_SDMA
		if (data->flags == MMC_DATA_READ)
			start_addr = (unsigned long)data->dest;
		else
			start_addr = (unsigned long)data->src;
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				(start_addr & 0x7) != 0x0) {
			is_aligned = 0;
			start_addr = (unsigned long)aligned_buffer;
			if (data->flags != MMC_DATA_READ)
				memcpy(aligned_buffer, data->src, trans_bytes);
		}

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
		/*
		 * Always use this bounce-buffer when
		 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
		 */
		is_aligned = 0;
		start_addr = (unsigned long)aligned_buffer;
		if (data->flags != MMC_DATA_READ)
			memcpy(aligned_buffer, data->src, trans_bytes);
#endif

		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		mode |= SDHCI_TRNS_DMA;
#endif
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
				data->blocksize),
				SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
	} else if (cmd->resp_type & MMC_RSP_BUSY) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	}

	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDMA
	flush_cache(start_addr, trans_bytes);
#endif
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	start = get_timer(0);
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR)
			break;

		if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
			if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
				return 0;
			} else {
				printf("%s: Timeout for status update!\n",
				       __func__);
				return -ETIMEDOUT;
			}
		}
	} while ((stat & mask) != mask);

	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
		sdhci_cmd_done(host, cmd);
		sdhci_writel(host, mask, SDHCI_INT_STATUS);
	} else
		ret = -1;

	if (!ret && data)
		ret = sdhci_transfer_data(host, data, start_addr);

	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
		udelay(1000);

	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	if (!ret) {
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				!is_aligned && (data->flags == MMC_DATA_READ))
			memcpy(data->dest, aligned_buffer, trans_bytes);
		return 0;
	}

	sdhci_reset(host, SDHCI_RESET_CMD);
	sdhci_reset(host, SDHCI_RESET_DATA);
	if (stat & SDHCI_INT_TIMEOUT)
		return -ETIMEDOUT;
	else
		return -ECOMM;
}

static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
	struct sdhci_host *host = mmc->priv;
	unsigned int div, clk, timeout, reg;

	/* Wait max 20 ms */
	timeout = 200;
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
			   (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
		if (timeout == 0) {
			printf("%s: Timeout to wait cmd & data inhibit\n",
			       __func__);
			return -1;
		}

		timeout--;
		udelay(100);
	}

	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return 0;

	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		/* Version 3.00 divisors must be a multiple of 2. */
		if (mmc->cfg->f_max <= clock)
			div = 1;
		else {
			for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
				if ((mmc->cfg->f_max / div) <= clock)
					break;
			}
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
			if ((mmc->cfg->f_max / div) <= clock)
				break;
		}
	}
	div >>= 1;

	if (host->set_clock)
		host->set_clock(host->index, div);

	clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			printf("%s: Internal clock never stabilised.\n",
			       __func__);
			return -1;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	return 0;
}

static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
	u8 pwr = 0;

	if (power != (unsigned short)-1) {
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		}
	}

	if (pwr == 0) {
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
		return;
	}

	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

	pwr |= SDHCI_POWER_ON;

	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}

#ifdef CONFIG_DM_MMC_OPS
static int sdhci_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static void sdhci_set_ios(struct mmc *mmc)
{
#endif
	u32 ctrl;
	struct sdhci_host *host = mmc->priv;

	if (host->set_control_reg)
		host->set_control_reg(host);

	if (mmc->clock != host->clock)
		sdhci_set_clock(mmc, mmc->clock);

	/* Set bus width */
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if (mmc->bus_width == 8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (mmc->bus_width == 4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}

	if (mmc->clock > 26000000)
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
		ctrl &= ~SDHCI_CTRL_HISPD;

	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#ifdef CONFIG_DM_MMC_OPS
	return 0;
#endif
}

static int sdhci_init(struct mmc *mmc)
{
	struct sdhci_host *host = mmc->priv;

	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
		aligned_buffer = memalign(8, 512*1024);
		if (!aligned_buffer) {
			printf("%s: Aligned buffer alloc failed!!!\n",
			       __func__);
			return -1;
		}
	}

	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);

	if (host->quirks & SDHCI_QUIRK_NO_CD) {
#if defined(CONFIG_PIC32_SDHCI)
		/* PIC32 SDHCI CD errata:
		 * - set CD_TEST and clear CD_TEST_INS bit
		 */
		sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
#else
		unsigned int status;

		sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
			SDHCI_HOST_CONTROL);

		status = sdhci_readl(host, SDHCI_PRESENT_STATE);
		while ((!(status & SDHCI_CARD_PRESENT)) ||
		    (!(status & SDHCI_CARD_STATE_STABLE)) ||
		    (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
			status = sdhci_readl(host, SDHCI_PRESENT_STATE);
#endif
	}

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
		     SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}

#ifdef CONFIG_DM_MMC_OPS
int sdhci_probe(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return sdhci_init(mmc);
}

const struct dm_mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
};
#else
static const struct mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
	.init		= sdhci_init,
};
#endif

int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
		u32 max_clk, u32 min_clk)
{
	u32 caps;

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);

	cfg->name = host->name;
#ifndef CONFIG_DM_MMC_OPS
	cfg->ops = &sdhci_ops;
#endif
	if (max_clk)
		cfg->f_max = max_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
				SDHCI_CLOCK_BASE_SHIFT;
		else
			cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
				SDHCI_CLOCK_BASE_SHIFT;
		cfg->f_max *= 1000000;
	}
	if (cfg->f_max == 0)
		return -EINVAL;
	if (min_clk)
		cfg->f_min = min_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
		else
			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
	}
	cfg->voltages = 0;
	if (caps & SDHCI_CAN_VDD_330)
		cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
	if (caps & SDHCI_CAN_VDD_300)
		cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & SDHCI_CAN_VDD_180)
		cfg->voltages |= MMC_VDD_165_195;

	cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		if (caps & SDHCI_CAN_DO_8BIT)
			cfg->host_caps |= MMC_MODE_8BIT;
	}

	if (host->host_caps)
		cfg->host_caps |= host->host_caps;


	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	return 0;
}

#ifdef CONFIG_BLK
int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
{
	return mmc_bind(dev, mmc, cfg);
}
#else
int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
	unsigned int caps;

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDMA
	if (!(caps & SDHCI_CAN_DO_SDMA)) {
		printf("%s: Your controller doesn't support SDMA!!\n",
		       __func__);
		return -1;
	}
#endif

	if (sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk)) {
		printf("%s: Hardware doesn't specify base clock frequency\n",
		       __func__);
		return -EINVAL;
	}

	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
		host->cfg.voltages |= host->voltages;

	sdhci_reset(host, SDHCI_RESET_ALL);

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL) {
		printf("%s: mmc create fail!\n", __func__);
		return -1;
	}

	return 0;
}
#endif
Commit	Line	Data
af62a557 LW	1	/*
	2	* Copyright 2011, Marvell Semiconductor Inc.
	3	* Lei Wen <leiwen@marvell.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
af62a557 LW	6	*
	7	* Back ported to the 8xx platform (from the 8260 platform) by
	8	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
	9	*/
	10
	11	#include <common.h>
2a809093	12	#include <errno.h>
af62a557 LW	13	#include <malloc.h>
	14	#include <mmc.h>
	15	#include <sdhci.h>
	16
492d3223 SR	17	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	18	void aligned_buffer = (void )CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
	19	#else
af62a557	20	void *aligned_buffer;
492d3223	21	#endif
af62a557 LW	22
	23	static void sdhci_reset(struct sdhci_host *host, u8 mask)
	24	{
	25	unsigned long timeout;
	26
	27	/* Wait max 100 ms */
	28	timeout = 100;
	29	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	30	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
	31	if (timeout == 0) {
30e6d979 DR	32	printf("%s: Reset 0x%x never completed.\n",
30e6d979 DR	33	__func__, (int)mask);
af62a557 LW	34	return;
	35	}
	36	timeout--;
	37	udelay(1000);
	38	}
	39	}
	40
	41	static void sdhci_cmd_done(struct sdhci_host host, struct mmc_cmd cmd)
	42	{
	43	int i;
	44	if (cmd->resp_type & MMC_RSP_136) {
	45	/* CRC is stripped so we need to do some shifting. */
	46	for (i = 0; i < 4; i++) {
	47	cmd->response[i] = sdhci_readl(host,
	48	SDHCI_RESPONSE + (3-i)*4) << 8;
	49	if (i != 3)
	50	cmd->response[i] \|= sdhci_readb(host,
	51	SDHCI_RESPONSE + (3-i)*4-1);
	52	}
	53	} else {
	54	cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	55	}
	56	}
	57
	58	static void sdhci_transfer_pio(struct sdhci_host host, struct mmc_data data)
	59	{
	60	int i;
	61	char *offs;
	62	for (i = 0; i < data->blocksize; i += 4) {
	63	offs = data->dest + i;
	64	if (data->flags == MMC_DATA_READ)
	65	(u32 )offs = sdhci_readl(host, SDHCI_BUFFER);
	66	else
	67	sdhci_writel(host, (u32 )offs, SDHCI_BUFFER);
	68	}
	69	}
	70
	71	static int sdhci_transfer_data(struct sdhci_host host, struct mmc_data data,
	72	unsigned int start_addr)
	73	{
a004abde	74	unsigned int stat, rdy, mask, timeout, block = 0;
804c7f42 JC	75	#ifdef CONFIG_MMC_SDMA
804c7f42 JC	76	unsigned char ctrl;
2c011847	77	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
804c7f42	78	ctrl &= ~SDHCI_CTRL_DMA_MASK;
2c011847	79	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
804c7f42	80	#endif
af62a557	81
5d48e422	82	timeout = 1000000;
af62a557 LW	83	rdy = SDHCI_INT_SPACE_AVAIL \| SDHCI_INT_DATA_AVAIL;
	84	mask = SDHCI_DATA_AVAILABLE \| SDHCI_SPACE_AVAILABLE;
	85	do {
	86	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	87	if (stat & SDHCI_INT_ERROR) {
30e6d979 DR	88	printf("%s: Error detected in status(0x%X)!\n",
30e6d979 DR	89	__func__, stat);
af62a557 LW	90	return -1;
	91	}
	92	if (stat & rdy) {
	93	if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
	94	continue;
	95	sdhci_writel(host, rdy, SDHCI_INT_STATUS);
	96	sdhci_transfer_pio(host, data);
	97	data->dest += data->blocksize;
	98	if (++block >= data->blocks)
	99	break;
	100	}
	101	#ifdef CONFIG_MMC_SDMA
	102	if (stat & SDHCI_INT_DMA_END) {
	103	sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
3e81c772	104	start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
af62a557 LW	105	start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
	106	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	107	}
	108	#endif
a004abde LW	109	if (timeout-- > 0)
	110	udelay(10);
	111	else {
30e6d979	112	printf("%s: Transfer data timeout\n", __func__);
a004abde LW	113	return -1;
a004abde LW	114	}
af62a557 LW	115	} while (!(stat & SDHCI_INT_DATA_END));
	116	return 0;
	117	}
	118
56b34bc6 PM	119	/*
	120	* No command will be sent by driver if card is busy, so driver must wait
	121	* for card ready state.
	122	* Every time when card is busy after timeout then (last) timeout value will be
	123	* increased twice but only if it doesn't exceed global defined maximum.
	124	* Each function call will use last timeout value. Max timeout can be redefined
	125	* in board config file.
	126	*/
	127	#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
	128	#define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
	129	#endif
	130	#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
d90bb439	131	#define SDHCI_READ_STATUS_TIMEOUT 1000
56b34bc6	132
ef1e4eda SG	133	#ifdef CONFIG_DM_MMC_OPS
	134	static int sdhci_send_command(struct udevice dev, struct mmc_cmd cmd,
	135	struct mmc_data *data)
	136	{
	137	struct mmc *mmc = mmc_get_mmc_dev(dev);
	138
	139	#else
6588c78b	140	static int sdhci_send_command(struct mmc mmc, struct mmc_cmd cmd,
ef1e4eda	141	struct mmc_data *data)
af62a557	142	{
ef1e4eda	143	#endif
93bfd616	144	struct sdhci_host *host = mmc->priv;
af62a557 LW	145	unsigned int stat = 0;
	146	int ret = 0;
	147	int trans_bytes = 0, is_aligned = 1;
	148	u32 mask, flags, mode;
56b34bc6	149	unsigned int time = 0, start_addr = 0;
19d2e342	150	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
29905a45	151	unsigned start = get_timer(0);
af62a557	152
56b34bc6 PM	153	/* Timeout unit - ms */
56b34bc6 PM	154	static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
af62a557 LW	155
	156	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	157	mask = SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT;
	158
	159	/* We shouldn't wait for data inihibit for stop commands, even
	160	though they might use busy signaling */
	161	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	162	mask &= ~SDHCI_DATA_INHIBIT;
	163
	164	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
56b34bc6	165	if (time >= cmd_timeout) {
30e6d979	166	printf("%s: MMC: %d busy ", __func__, mmc_dev);
56b34bc6 PM	167	if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
	168	cmd_timeout += cmd_timeout;
	169	printf("timeout increasing to: %u ms.\n",
	170	cmd_timeout);
	171	} else {
	172	puts("timeout.\n");
915ffa52	173	return -ECOMM;
56b34bc6	174	}
af62a557	175	}
56b34bc6	176	time++;
af62a557 LW	177	udelay(1000);
	178	}
	179
	180	mask = SDHCI_INT_RESPONSE;
	181	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	182	flags = SDHCI_CMD_RESP_NONE;
	183	else if (cmd->resp_type & MMC_RSP_136)
	184	flags = SDHCI_CMD_RESP_LONG;
	185	else if (cmd->resp_type & MMC_RSP_BUSY) {
	186	flags = SDHCI_CMD_RESP_SHORT_BUSY;
17ea3c86 JC	187	if (data)
17ea3c86 JC	188	mask \|= SDHCI_INT_DATA_END;
af62a557 LW	189	} else
	190	flags = SDHCI_CMD_RESP_SHORT;
	191
	192	if (cmd->resp_type & MMC_RSP_CRC)
	193	flags \|= SDHCI_CMD_CRC;
	194	if (cmd->resp_type & MMC_RSP_OPCODE)
	195	flags \|= SDHCI_CMD_INDEX;
	196	if (data)
	197	flags \|= SDHCI_CMD_DATA;
	198
30e6d979	199	/* Set Transfer mode regarding to data flag */
af62a557 LW	200	if (data != 0) {
	201	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	202	mode = SDHCI_TRNS_BLK_CNT_EN;
	203	trans_bytes = data->blocks * data->blocksize;
	204	if (data->blocks > 1)
	205	mode \|= SDHCI_TRNS_MULTI;
	206
	207	if (data->flags == MMC_DATA_READ)
	208	mode \|= SDHCI_TRNS_READ;
	209
	210	#ifdef CONFIG_MMC_SDMA
	211	if (data->flags == MMC_DATA_READ)
3c1fcb77	212	start_addr = (unsigned long)data->dest;
af62a557	213	else
3c1fcb77	214	start_addr = (unsigned long)data->src;
af62a557 LW	215	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	216	(start_addr & 0x7) != 0x0) {
	217	is_aligned = 0;
3c1fcb77	218	start_addr = (unsigned long)aligned_buffer;
af62a557 LW	219	if (data->flags != MMC_DATA_READ)
	220	memcpy(aligned_buffer, data->src, trans_bytes);
	221	}
	222
492d3223 SR	223	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	224	/*
	225	* Always use this bounce-buffer when
	226	* CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
	227	*/
	228	is_aligned = 0;
	229	start_addr = (unsigned long)aligned_buffer;
	230	if (data->flags != MMC_DATA_READ)
	231	memcpy(aligned_buffer, data->src, trans_bytes);
	232	#endif
	233
af62a557 LW	234	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	235	mode \|= SDHCI_TRNS_DMA;
	236	#endif
	237	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
	238	data->blocksize),
	239	SDHCI_BLOCK_SIZE);
	240	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
	241	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
5e1c23cd KL	242	} else if (cmd->resp_type & MMC_RSP_BUSY) {
5e1c23cd KL	243	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
af62a557 LW	244	}
	245
	246	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
	247	#ifdef CONFIG_MMC_SDMA
2c2ec4c9	248	flush_cache(start_addr, trans_bytes);
af62a557 LW	249	#endif
af62a557 LW	250	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
29905a45	251	start = get_timer(0);
af62a557 LW	252	do {
	253	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	254	if (stat & SDHCI_INT_ERROR)
	255	break;
af62a557	256
bae4a1fd MY	257	if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
	258	if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
	259	return 0;
	260	} else {
	261	printf("%s: Timeout for status update!\n",
	262	__func__);
915ffa52	263	return -ETIMEDOUT;
bae4a1fd	264	}
3a638320	265	}
bae4a1fd	266	} while ((stat & mask) != mask);
3a638320	267
af62a557 LW	268	if ((stat & (SDHCI_INT_ERROR \| mask)) == mask) {
	269	sdhci_cmd_done(host, cmd);
	270	sdhci_writel(host, mask, SDHCI_INT_STATUS);
	271	} else
	272	ret = -1;
	273
	274	if (!ret && data)
	275	ret = sdhci_transfer_data(host, data, start_addr);
	276
13243f2e TB	277	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
	278	udelay(1000);
	279
af62a557 LW	280	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	281	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	282	if (!ret) {
	283	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	284	!is_aligned && (data->flags == MMC_DATA_READ))
	285	memcpy(data->dest, aligned_buffer, trans_bytes);
	286	return 0;
	287	}
	288
	289	sdhci_reset(host, SDHCI_RESET_CMD);
	290	sdhci_reset(host, SDHCI_RESET_DATA);
	291	if (stat & SDHCI_INT_TIMEOUT)
915ffa52	292	return -ETIMEDOUT;
af62a557	293	else
915ffa52	294	return -ECOMM;
af62a557 LW	295	}
	296
	297	static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
	298	{
93bfd616	299	struct sdhci_host *host = mmc->priv;
79667b7b	300	unsigned int div, clk, timeout, reg;
af62a557	301
79667b7b WY	302	/* Wait max 20 ms */
	303	timeout = 200;
	304	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
	305	(SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT)) {
	306	if (timeout == 0) {
	307	printf("%s: Timeout to wait cmd & data inhibit\n",
	308	__func__);
	309	return -1;
	310	}
	311
	312	timeout--;
	313	udelay(100);
	314	}
	315
	316	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1d405e20	317	reg &= ~(SDHCI_CLOCK_CARD_EN \| SDHCI_CLOCK_INT_EN);
79667b7b	318	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
af62a557 LW	319
	320	if (clock == 0)
	321	return 0;
	322
113e5dfc	323	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
af62a557	324	/* Version 3.00 divisors must be a multiple of 2. */
93bfd616	325	if (mmc->cfg->f_max <= clock)
af62a557 LW	326	div = 1;
	327	else {
	328	for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
93bfd616	329	if ((mmc->cfg->f_max / div) <= clock)
af62a557 LW	330	break;
	331	}
	332	}
	333	} else {
	334	/* Version 2.00 divisors must be a power of 2. */
	335	for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
93bfd616	336	if ((mmc->cfg->f_max / div) <= clock)
af62a557 LW	337	break;
	338	}
	339	}
	340	div >>= 1;
	341
b09ed6e4 JC	342	if (host->set_clock)
	343	host->set_clock(host->index, div);
	344
af62a557 LW	345	clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	346	clk \|= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
	347	<< SDHCI_DIVIDER_HI_SHIFT;
	348	clk \|= SDHCI_CLOCK_INT_EN;
	349	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	350
	351	/* Wait max 20 ms */
	352	timeout = 20;
	353	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	354	& SDHCI_CLOCK_INT_STABLE)) {
	355	if (timeout == 0) {
30e6d979 DR	356	printf("%s: Internal clock never stabilised.\n",
30e6d979 DR	357	__func__);
af62a557 LW	358	return -1;
	359	}
	360	timeout--;
	361	udelay(1000);
	362	}
	363
	364	clk \|= SDHCI_CLOCK_CARD_EN;
	365	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	366	return 0;
	367	}
	368
	369	static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
	370	{
	371	u8 pwr = 0;
	372
	373	if (power != (unsigned short)-1) {
	374	switch (1 << power) {
	375	case MMC_VDD_165_195:
	376	pwr = SDHCI_POWER_180;
	377	break;
	378	case MMC_VDD_29_30:
	379	case MMC_VDD_30_31:
	380	pwr = SDHCI_POWER_300;
	381	break;
	382	case MMC_VDD_32_33:
	383	case MMC_VDD_33_34:
	384	pwr = SDHCI_POWER_330;
	385	break;
	386	}
	387	}
	388
	389	if (pwr == 0) {
	390	sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
	391	return;
	392	}
	393
688c2d14 MC	394	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
	395	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	396
af62a557 LW	397	pwr \|= SDHCI_POWER_ON;
	398
	399	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	400	}
	401
ef1e4eda SG	402	#ifdef CONFIG_DM_MMC_OPS
	403	static int sdhci_set_ios(struct udevice *dev)
	404	{
	405	struct mmc *mmc = mmc_get_mmc_dev(dev);
	406	#else
6588c78b	407	static void sdhci_set_ios(struct mmc *mmc)
af62a557	408	{
ef1e4eda	409	#endif
af62a557	410	u32 ctrl;
93bfd616	411	struct sdhci_host *host = mmc->priv;
af62a557	412
236bfecf JC	413	if (host->set_control_reg)
	414	host->set_control_reg(host);
	415
af62a557 LW	416	if (mmc->clock != host->clock)
	417	sdhci_set_clock(mmc, mmc->clock);
	418
	419	/* Set bus width */
	420	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	421	if (mmc->bus_width == 8) {
	422	ctrl &= ~SDHCI_CTRL_4BITBUS;
113e5dfc JC	423	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
113e5dfc JC	424	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	425	ctrl \|= SDHCI_CTRL_8BITBUS;
af62a557 LW	426	} else {
f88a429f MR	427	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
f88a429f MR	428	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	429	ctrl &= ~SDHCI_CTRL_8BITBUS;
	430	if (mmc->bus_width == 4)
	431	ctrl \|= SDHCI_CTRL_4BITBUS;
	432	else
	433	ctrl &= ~SDHCI_CTRL_4BITBUS;
	434	}
	435
	436	if (mmc->clock > 26000000)
	437	ctrl \|= SDHCI_CTRL_HISPD;
	438	else
	439	ctrl &= ~SDHCI_CTRL_HISPD;
	440
236bfecf JC	441	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
	442	ctrl &= ~SDHCI_CTRL_HISPD;
	443
af62a557	444	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
ef1e4eda SG	445	#ifdef CONFIG_DM_MMC_OPS
	446	return 0;
	447	#endif
af62a557 LW	448	}
af62a557 LW	449
6588c78b	450	static int sdhci_init(struct mmc *mmc)
af62a557	451	{
93bfd616	452	struct sdhci_host *host = mmc->priv;
af62a557 LW	453
	454	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
	455	aligned_buffer = memalign(8, 512*1024);
	456	if (!aligned_buffer) {
30e6d979 DR	457	printf("%s: Aligned buffer alloc failed!!!\n",
30e6d979 DR	458	__func__);
af62a557 LW	459	return -1;
	460	}
	461	}
	462
93bfd616	463	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
470dcc75 JH	464
470dcc75 JH	465	if (host->quirks & SDHCI_QUIRK_NO_CD) {
102142c9 AP	466	#if defined(CONFIG_PIC32_SDHCI)
	467	/* PIC32 SDHCI CD errata:
	468	* - set CD_TEST and clear CD_TEST_INS bit
	469	*/
	470	sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
	471	#else
470dcc75 JH	472	unsigned int status;
470dcc75 JH	473
e113fe3c	474	sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS \| SDHCI_CTRL_CD_TEST,
470dcc75 JH	475	SDHCI_HOST_CONTROL);
	476
	477	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	478	while ((!(status & SDHCI_CARD_PRESENT)) \|\|
	479	(!(status & SDHCI_CARD_STATE_STABLE)) \|\|
	480	(!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
	481	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
102142c9	482	#endif
470dcc75 JH	483	}
470dcc75 JH	484
ce0c1bc1	485	/* Enable only interrupts served by the SD controller */
30e6d979 DR	486	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK,
30e6d979 DR	487	SDHCI_INT_ENABLE);
ce0c1bc1 ŁM	488	/* Mask all sdhci interrupt sources */
ce0c1bc1 ŁM	489	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
af62a557	490
af62a557 LW	491	return 0;
	492	}
	493
ef1e4eda SG	494	#ifdef CONFIG_DM_MMC_OPS
	495	int sdhci_probe(struct udevice *dev)
	496	{
	497	struct mmc *mmc = mmc_get_mmc_dev(dev);
	498
	499	return sdhci_init(mmc);
	500	}
ab769f22	501
ef1e4eda SG	502	const struct dm_mmc_ops sdhci_ops = {
	503	.send_cmd = sdhci_send_command,
	504	.set_ios = sdhci_set_ios,
	505	};
	506	#else
ab769f22 PA	507	static const struct mmc_ops sdhci_ops = {
	508	.send_cmd = sdhci_send_command,
	509	.set_ios = sdhci_set_ios,
	510	.init = sdhci_init,
	511	};
ef1e4eda	512	#endif
ab769f22	513
14bed52d JC	514	int sdhci_setup_cfg(struct mmc_config cfg, struct sdhci_host host,
14bed52d JC	515	u32 max_clk, u32 min_clk)
af62a557	516	{
14bed52d JC	517	u32 caps;
	518
	519	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	520	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
	521
	522	cfg->name = host->name;
2a809093 SG	523	#ifndef CONFIG_DM_MMC_OPS
2a809093 SG	524	cfg->ops = &sdhci_ops;
af62a557	525	#endif
af62a557	526	if (max_clk)
2a809093	527	cfg->f_max = max_clk;
af62a557	528	else {
14bed52d	529	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
2a809093 SG	530	cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
2a809093 SG	531	SDHCI_CLOCK_BASE_SHIFT;
af62a557	532	else
2a809093 SG	533	cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
	534	SDHCI_CLOCK_BASE_SHIFT;
	535	cfg->f_max *= 1000000;
af62a557	536	}
2a809093 SG	537	if (cfg->f_max == 0)
2a809093 SG	538	return -EINVAL;
af62a557	539	if (min_clk)
2a809093	540	cfg->f_min = min_clk;
af62a557	541	else {
14bed52d	542	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
2a809093	543	cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
af62a557	544	else
2a809093	545	cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
af62a557	546	}
2a809093	547	cfg->voltages = 0;
af62a557	548	if (caps & SDHCI_CAN_VDD_330)
2a809093	549	cfg->voltages \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
af62a557	550	if (caps & SDHCI_CAN_VDD_300)
2a809093	551	cfg->voltages \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
af62a557	552	if (caps & SDHCI_CAN_VDD_180)
2a809093	553	cfg->voltages \|= MMC_VDD_165_195;
236bfecf	554
2a809093	555	cfg->host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT;
14bed52d	556	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
1695b29a	557	if (caps & SDHCI_CAN_DO_8BIT)
2a809093	558	cfg->host_caps \|= MMC_MODE_8BIT;
1695b29a	559	}
42979002	560
14bed52d JC	561	if (host->host_caps)
14bed52d JC	562	cfg->host_caps \|= host->host_caps;
42979002	563
ef1e4eda	564
2a809093	565	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
93bfd616	566
2a809093 SG	567	return 0;
	568	}
	569
ef1e4eda SG	570	#ifdef CONFIG_BLK
	571	int sdhci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg)
	572	{
	573	return mmc_bind(dev, mmc, cfg);
	574	}
	575	#else
2a809093 SG	576	int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
	577	{
	578	unsigned int caps;
	579
	580	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	581	#ifdef CONFIG_MMC_SDMA
	582	if (!(caps & SDHCI_CAN_DO_SDMA)) {
	583	printf("%s: Your controller doesn't support SDMA!!\n",
	584	__func__);
	585	return -1;
	586	}
	587	#endif
	588
14bed52d	589	if (sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk)) {
2a809093 SG	590	printf("%s: Hardware doesn't specify base clock frequency\n",
	591	__func__);
	592	return -EINVAL;
	593	}
	594
	595	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
	596	host->cfg.voltages \|= host->voltages;
af62a557 LW	597
af62a557 LW	598	sdhci_reset(host, SDHCI_RESET_ALL);
93bfd616 PA	599
	600	host->mmc = mmc_create(&host->cfg, host);
	601	if (host->mmc == NULL) {
	602	printf("%s: mmc create fail!\n", __func__);
	603	return -1;
	604	}
af62a557 LW	605
	606	return 0;
	607	}
ef1e4eda	608	#endif