[people/ms/u-boot.git] / drivers / mmc / sdhci.c

/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <leiwen@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
 */

#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>

void *aligned_buffer;

static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
	unsigned long timeout;

	/* Wait max 100 ms */
	timeout = 100;
	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
		if (timeout == 0) {
			printf("Reset 0x%x never completed.\n", (int)mask);
			return;
		}
		timeout--;
		udelay(1000);
	}
}

static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
	int i;
	if (cmd->resp_type & MMC_RSP_136) {
		/* CRC is stripped so we need to do some shifting. */
		for (i = 0; i < 4; i++) {
			cmd->response[i] = sdhci_readl(host,
					SDHCI_RESPONSE + (3-i)*4) << 8;
			if (i != 3)
				cmd->response[i] |= sdhci_readb(host,
						SDHCI_RESPONSE + (3-i)*4-1);
		}
	} else {
		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	}
}

static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
{
	int i;
	char *offs;
	for (i = 0; i < data->blocksize; i += 4) {
		offs = data->dest + i;
		if (data->flags == MMC_DATA_READ)
			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
		else
			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
	}
}

static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
				unsigned int start_addr)
{
	unsigned int stat, rdy, mask, timeout, block = 0;
#ifdef CONFIG_MMC_SDMA
	unsigned char ctrl;
	ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	ctrl |= SDHCI_CTRL_SDMA;
	sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
#endif

	timeout = 1000000;
	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR) {
			printf("Error detected in status(0x%X)!\n", stat);
			return -1;
		}
		if (stat & rdy) {
			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
				continue;
			sdhci_writel(host, rdy, SDHCI_INT_STATUS);
			sdhci_transfer_pio(host, data);
			data->dest += data->blocksize;
			if (++block >= data->blocks)
				break;
		}
#ifdef CONFIG_MMC_SDMA
		if (stat & SDHCI_INT_DMA_END) {
			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		}
#endif
		if (timeout-- > 0)
			udelay(10);
		else {
			printf("Transfer data timeout\n");
			return -1;
		}
	} while (!(stat & SDHCI_INT_DATA_END));
	return 0;
}

int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
		       struct mmc_data *data)
{
	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
	unsigned int stat = 0;
	int ret = 0;
	int trans_bytes = 0, is_aligned = 1;
	u32 mask, flags, mode;
	unsigned int timeout, start_addr = 0;
	unsigned int retry = 10000;

	/* Wait max 10 ms */
	timeout = 10;

	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		mask &= ~SDHCI_DATA_INHIBIT;

	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
		if (timeout == 0) {
			printf("Controller never released inhibit bit(s).\n");
			return COMM_ERR;
		}
		timeout--;
		udelay(1000);
	}

	mask = SDHCI_INT_RESPONSE;
	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->resp_type & MMC_RSP_BUSY) {
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
		mask |= SDHCI_INT_DATA_END;
	} else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
	if (data)
		flags |= SDHCI_CMD_DATA;

	/*Set Transfer mode regarding to data flag*/
	if (data != 0) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
		mode = SDHCI_TRNS_BLK_CNT_EN;
		trans_bytes = data->blocks * data->blocksize;
		if (data->blocks > 1)
			mode |= SDHCI_TRNS_MULTI;

		if (data->flags == MMC_DATA_READ)
			mode |= SDHCI_TRNS_READ;

#ifdef CONFIG_MMC_SDMA
		if (data->flags == MMC_DATA_READ)
			start_addr = (unsigned int)data->dest;
		else
			start_addr = (unsigned int)data->src;
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				(start_addr & 0x7) != 0x0) {
			is_aligned = 0;
			start_addr = (unsigned int)aligned_buffer;
			if (data->flags != MMC_DATA_READ)
				memcpy(aligned_buffer, data->src, trans_bytes);
		}

		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		mode |= SDHCI_TRNS_DMA;
#endif
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
				data->blocksize),
				SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
	}

	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDMA
	flush_cache(start_addr, trans_bytes);
#endif
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR)
			break;
		if (--retry == 0)
			break;
	} while ((stat & mask) != mask);

	if (retry == 0) {
		if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
			return 0;
		else {
			printf("Timeout for status update!\n");
			return TIMEOUT;
		}
	}

	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
		sdhci_cmd_done(host, cmd);
		sdhci_writel(host, mask, SDHCI_INT_STATUS);
	} else
		ret = -1;

	if (!ret && data)
		ret = sdhci_transfer_data(host, data, start_addr);

	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
		udelay(1000);

	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	if (!ret) {
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				!is_aligned && (data->flags == MMC_DATA_READ))
			memcpy(data->dest, aligned_buffer, trans_bytes);
		return 0;
	}

	sdhci_reset(host, SDHCI_RESET_CMD);
	sdhci_reset(host, SDHCI_RESET_DATA);
	if (stat & SDHCI_INT_TIMEOUT)
		return TIMEOUT;
	else
		return COMM_ERR;
}

static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
	unsigned int div, clk, timeout;

	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return 0;

	if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
		/* Version 3.00 divisors must be a multiple of 2. */
		if (mmc->f_max <= clock)
			div = 1;
		else {
			for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
				if ((mmc->f_max / div) <= clock)
					break;
			}
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
			if ((mmc->f_max / div) <= clock)
				break;
		}
	}
	div >>= 1;

	if (host->set_clock)
		host->set_clock(host->index, div);

	clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			printf("Internal clock never stabilised.\n");
			return -1;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	return 0;
}

static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
	u8 pwr = 0;

	if (power != (unsigned short)-1) {
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		}
	}

	if (pwr == 0) {
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
		return;
	}

	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

	pwr |= SDHCI_POWER_ON;

	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}

void sdhci_set_ios(struct mmc *mmc)
{
	u32 ctrl;
	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;

	if (host->set_control_reg)
		host->set_control_reg(host);

	if (mmc->clock != host->clock)
		sdhci_set_clock(mmc, mmc->clock);

	/* Set bus width */
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if (mmc->bus_width == 8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
			ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
			ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (mmc->bus_width == 4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}

	if (mmc->clock > 26000000)
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
		ctrl &= ~SDHCI_CTRL_HISPD;

	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}

int sdhci_init(struct mmc *mmc)
{
	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;

	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
		aligned_buffer = memalign(8, 512*1024);
		if (!aligned_buffer) {
			printf("Aligned buffer alloc failed!!!");
			return -1;
		}
	}

	sdhci_set_power(host, fls(mmc->voltages) - 1);

	if (host->quirks & SDHCI_QUIRK_NO_CD) {
		unsigned int status;

		sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
			SDHCI_HOST_CONTROL);

		status = sdhci_readl(host, SDHCI_PRESENT_STATE);
		while ((!(status & SDHCI_CARD_PRESENT)) ||
		    (!(status & SDHCI_CARD_STATE_STABLE)) ||
		    (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
			status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	}

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK
		     , SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}

int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
	struct mmc *mmc;
	unsigned int caps;

	mmc = malloc(sizeof(struct mmc));
	if (!mmc) {
		printf("mmc malloc fail!\n");
		return -1;
	}

	mmc->priv = host;
	host->mmc = mmc;

	sprintf(mmc->name, "%s", host->name);
	mmc->send_cmd = sdhci_send_command;
	mmc->set_ios = sdhci_set_ios;
	mmc->init = sdhci_init;
	mmc->getcd = NULL;
	mmc->getwp = NULL;

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDMA
	if (!(caps & SDHCI_CAN_DO_SDMA)) {
		printf("Your controller don't support sdma!!\n");
		return -1;
	}
#endif

	if (max_clk)
		mmc->f_max = max_clk;
	else {
		if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
			mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
				>> SDHCI_CLOCK_BASE_SHIFT;
		else
			mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
				>> SDHCI_CLOCK_BASE_SHIFT;
		mmc->f_max *= 1000000;
	}
	if (mmc->f_max == 0) {
		printf("Hardware doesn't specify base clock frequency\n");
		return -1;
	}
	if (min_clk)
		mmc->f_min = min_clk;
	else {
		if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
			mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
		else
			mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
	}

	mmc->voltages = 0;
	if (caps & SDHCI_CAN_VDD_330)
		mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
	if (caps & SDHCI_CAN_VDD_300)
		mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & SDHCI_CAN_VDD_180)
		mmc->voltages |= MMC_VDD_165_195;

	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
		mmc->voltages |= host->voltages;

	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
	if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
		if (caps & SDHCI_CAN_DO_8BIT)
			mmc->host_caps |= MMC_MODE_8BIT;
	}
	if (host->host_caps)
		mmc->host_caps |= host->host_caps;

	sdhci_reset(host, SDHCI_RESET_ALL);
	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
af62a557 LW	1	/*
	2	* Copyright 2011, Marvell Semiconductor Inc.
	3	* Lei Wen <leiwen@marvell.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
af62a557 LW	6	*
	7	* Back ported to the 8xx platform (from the 8260 platform) by
	8	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
	9	*/
	10
	11	#include <common.h>
	12	#include <malloc.h>
	13	#include <mmc.h>
	14	#include <sdhci.h>
	15
	16	void *aligned_buffer;
	17
	18	static void sdhci_reset(struct sdhci_host *host, u8 mask)
	19	{
	20	unsigned long timeout;
	21
	22	/* Wait max 100 ms */
	23	timeout = 100;
	24	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	25	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
	26	if (timeout == 0) {
	27	printf("Reset 0x%x never completed.\n", (int)mask);
	28	return;
	29	}
	30	timeout--;
	31	udelay(1000);
	32	}
	33	}
	34
	35	static void sdhci_cmd_done(struct sdhci_host host, struct mmc_cmd cmd)
	36	{
	37	int i;
	38	if (cmd->resp_type & MMC_RSP_136) {
	39	/* CRC is stripped so we need to do some shifting. */
	40	for (i = 0; i < 4; i++) {
	41	cmd->response[i] = sdhci_readl(host,
	42	SDHCI_RESPONSE + (3-i)*4) << 8;
	43	if (i != 3)
	44	cmd->response[i] \|= sdhci_readb(host,
	45	SDHCI_RESPONSE + (3-i)*4-1);
	46	}
	47	} else {
	48	cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	49	}
	50	}
	51
	52	static void sdhci_transfer_pio(struct sdhci_host host, struct mmc_data data)
	53	{
	54	int i;
	55	char *offs;
	56	for (i = 0; i < data->blocksize; i += 4) {
	57	offs = data->dest + i;
	58	if (data->flags == MMC_DATA_READ)
	59	(u32 )offs = sdhci_readl(host, SDHCI_BUFFER);
	60	else
	61	sdhci_writel(host, (u32 )offs, SDHCI_BUFFER);
	62	}
	63	}
	64
	65	static int sdhci_transfer_data(struct sdhci_host host, struct mmc_data data,
	66	unsigned int start_addr)
	67	{
a004abde	68	unsigned int stat, rdy, mask, timeout, block = 0;
804c7f42 JC	69	#ifdef CONFIG_MMC_SDMA
	70	unsigned char ctrl;
	71	ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
	72	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	73	ctrl \|= SDHCI_CTRL_SDMA;
	74	sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
	75	#endif
af62a557	76
5d48e422	77	timeout = 1000000;
af62a557 LW	78	rdy = SDHCI_INT_SPACE_AVAIL \| SDHCI_INT_DATA_AVAIL;
	79	mask = SDHCI_DATA_AVAILABLE \| SDHCI_SPACE_AVAILABLE;
	80	do {
	81	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	82	if (stat & SDHCI_INT_ERROR) {
	83	printf("Error detected in status(0x%X)!\n", stat);
	84	return -1;
	85	}
	86	if (stat & rdy) {
	87	if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
	88	continue;
	89	sdhci_writel(host, rdy, SDHCI_INT_STATUS);
	90	sdhci_transfer_pio(host, data);
	91	data->dest += data->blocksize;
	92	if (++block >= data->blocks)
	93	break;
	94	}
	95	#ifdef CONFIG_MMC_SDMA
	96	if (stat & SDHCI_INT_DMA_END) {
	97	sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
3e81c772	98	start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
af62a557 LW	99	start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
	100	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	101	}
	102	#endif
a004abde LW	103	if (timeout-- > 0)
	104	udelay(10);
	105	else {
	106	printf("Transfer data timeout\n");
	107	return -1;
	108	}
af62a557 LW	109	} while (!(stat & SDHCI_INT_DATA_END));
	110	return 0;
	111	}
	112
	113	int sdhci_send_command(struct mmc mmc, struct mmc_cmd cmd,
	114	struct mmc_data *data)
	115	{
	116	struct sdhci_host host = (struct sdhci_host )mmc->priv;
	117	unsigned int stat = 0;
	118	int ret = 0;
	119	int trans_bytes = 0, is_aligned = 1;
	120	u32 mask, flags, mode;
	121	unsigned int timeout, start_addr = 0;
3a638320	122	unsigned int retry = 10000;
af62a557 LW	123
	124	/* Wait max 10 ms */
	125	timeout = 10;
	126
	127	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	128	mask = SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT;
	129
	130	/* We shouldn't wait for data inihibit for stop commands, even
	131	though they might use busy signaling */
	132	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	133	mask &= ~SDHCI_DATA_INHIBIT;
	134
	135	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
	136	if (timeout == 0) {
	137	printf("Controller never released inhibit bit(s).\n");
	138	return COMM_ERR;
	139	}
	140	timeout--;
	141	udelay(1000);
	142	}
	143
	144	mask = SDHCI_INT_RESPONSE;
	145	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	146	flags = SDHCI_CMD_RESP_NONE;
	147	else if (cmd->resp_type & MMC_RSP_136)
	148	flags = SDHCI_CMD_RESP_LONG;
	149	else if (cmd->resp_type & MMC_RSP_BUSY) {
	150	flags = SDHCI_CMD_RESP_SHORT_BUSY;
	151	mask \|= SDHCI_INT_DATA_END;
	152	} else
	153	flags = SDHCI_CMD_RESP_SHORT;
	154
	155	if (cmd->resp_type & MMC_RSP_CRC)
	156	flags \|= SDHCI_CMD_CRC;
	157	if (cmd->resp_type & MMC_RSP_OPCODE)
	158	flags \|= SDHCI_CMD_INDEX;
	159	if (data)
	160	flags \|= SDHCI_CMD_DATA;
	161
	162	/Set Transfer mode regarding to data flag/
	163	if (data != 0) {
	164	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	165	mode = SDHCI_TRNS_BLK_CNT_EN;
	166	trans_bytes = data->blocks * data->blocksize;
	167	if (data->blocks > 1)
	168	mode \|= SDHCI_TRNS_MULTI;
	169
	170	if (data->flags == MMC_DATA_READ)
	171	mode \|= SDHCI_TRNS_READ;
	172
	173	#ifdef CONFIG_MMC_SDMA
	174	if (data->flags == MMC_DATA_READ)
	175	start_addr = (unsigned int)data->dest;
	176	else
	177	start_addr = (unsigned int)data->src;
	178	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	179	(start_addr & 0x7) != 0x0) {
	180	is_aligned = 0;
	181	start_addr = (unsigned int)aligned_buffer;
	182	if (data->flags != MMC_DATA_READ)
	183	memcpy(aligned_buffer, data->src, trans_bytes);
	184	}
	185
	186	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
187	mode \|= SDHCI_TRNS_DMA;
188	#endif
189	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
190	data->blocksize),
191	SDHCI_BLOCK_SIZE);
192	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
193	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
194	}
195
196	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
197	#ifdef CONFIG_MMC_SDMA
2c2ec4c9	198	flush_cache(start_addr, trans_bytes);
af62a557 LW	199	#endif
	200	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	201	do {
	202	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	203	if (stat & SDHCI_INT_ERROR)
	204	break;
3a638320 JC	205	if (--retry == 0)
3a638320 JC	206	break;
af62a557 LW	207	} while ((stat & mask) != mask);
af62a557 LW	208
3a638320 JC	209	if (retry == 0) {
	210	if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
	211	return 0;
	212	else {
	213	printf("Timeout for status update!\n");
	214	return TIMEOUT;
	215	}
	216	}
	217
af62a557 LW	218	if ((stat & (SDHCI_INT_ERROR \| mask)) == mask) {
	219	sdhci_cmd_done(host, cmd);
	220	sdhci_writel(host, mask, SDHCI_INT_STATUS);
	221	} else
	222	ret = -1;
	223
	224	if (!ret && data)
	225	ret = sdhci_transfer_data(host, data, start_addr);
	226
13243f2e TB	227	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
	228	udelay(1000);
	229
af62a557 LW	230	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	231	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	232	if (!ret) {
	233	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	234	!is_aligned && (data->flags == MMC_DATA_READ))
	235	memcpy(data->dest, aligned_buffer, trans_bytes);
	236	return 0;
	237	}
	238
	239	sdhci_reset(host, SDHCI_RESET_CMD);
	240	sdhci_reset(host, SDHCI_RESET_DATA);
	241	if (stat & SDHCI_INT_TIMEOUT)
	242	return TIMEOUT;
	243	else
	244	return COMM_ERR;
	245	}
	246
	247	static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
	248	{
	249	struct sdhci_host host = (struct sdhci_host )mmc->priv;
	250	unsigned int div, clk, timeout;
	251
	252	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
	253
	254	if (clock == 0)
	255	return 0;
	256
073cfd1c	257	if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
af62a557 LW	258	/* Version 3.00 divisors must be a multiple of 2. */
	259	if (mmc->f_max <= clock)
	260	div = 1;
	261	else {
	262	for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
	263	if ((mmc->f_max / div) <= clock)
	264	break;
	265	}
	266	}
	267	} else {
	268	/* Version 2.00 divisors must be a power of 2. */
	269	for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
	270	if ((mmc->f_max / div) <= clock)
	271	break;
	272	}
	273	}
	274	div >>= 1;
	275
b09ed6e4 JC	276	if (host->set_clock)
	277	host->set_clock(host->index, div);
	278
af62a557 LW	279	clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	280	clk \|= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
	281	<< SDHCI_DIVIDER_HI_SHIFT;
	282	clk \|= SDHCI_CLOCK_INT_EN;
	283	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	284
	285	/* Wait max 20 ms */
	286	timeout = 20;
	287	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	288	& SDHCI_CLOCK_INT_STABLE)) {
	289	if (timeout == 0) {
	290	printf("Internal clock never stabilised.\n");
	291	return -1;
	292	}
	293	timeout--;
	294	udelay(1000);
	295	}
	296
	297	clk \|= SDHCI_CLOCK_CARD_EN;
	298	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	299	return 0;
	300	}
	301
	302	static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
	303	{
	304	u8 pwr = 0;
	305
	306	if (power != (unsigned short)-1) {
	307	switch (1 << power) {
	308	case MMC_VDD_165_195:
	309	pwr = SDHCI_POWER_180;
	310	break;
	311	case MMC_VDD_29_30:
	312	case MMC_VDD_30_31:
	313	pwr = SDHCI_POWER_300;
	314	break;
	315	case MMC_VDD_32_33:
	316	case MMC_VDD_33_34:
	317	pwr = SDHCI_POWER_330;
	318	break;
	319	}
	320	}
	321
	322	if (pwr == 0) {
	323	sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
	324	return;
	325	}
	326
688c2d14 MC	327	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
	328	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	329
af62a557 LW	330	pwr \|= SDHCI_POWER_ON;
	331
	332	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	333	}
	334
	335	void sdhci_set_ios(struct mmc *mmc)
	336	{
	337	u32 ctrl;
	338	struct sdhci_host host = (struct sdhci_host )mmc->priv;
	339
236bfecf JC	340	if (host->set_control_reg)
	341	host->set_control_reg(host);
	342
af62a557 LW	343	if (mmc->clock != host->clock)
	344	sdhci_set_clock(mmc, mmc->clock);
	345
	346	/* Set bus width */
	347	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	348	if (mmc->bus_width == 8) {
	349	ctrl &= ~SDHCI_CTRL_4BITBUS;
073cfd1c	350	if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
af62a557 LW	351	ctrl \|= SDHCI_CTRL_8BITBUS;
af62a557 LW	352	} else {
073cfd1c	353	if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
af62a557 LW	354	ctrl &= ~SDHCI_CTRL_8BITBUS;
	355	if (mmc->bus_width == 4)
	356	ctrl \|= SDHCI_CTRL_4BITBUS;
	357	else
	358	ctrl &= ~SDHCI_CTRL_4BITBUS;
	359	}
	360
	361	if (mmc->clock > 26000000)
	362	ctrl \|= SDHCI_CTRL_HISPD;
	363	else
	364	ctrl &= ~SDHCI_CTRL_HISPD;
	365
236bfecf JC	366	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
	367	ctrl &= ~SDHCI_CTRL_HISPD;
	368
af62a557 LW	369	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
	370	}
	371
	372	int sdhci_init(struct mmc *mmc)
	373	{
	374	struct sdhci_host host = (struct sdhci_host )mmc->priv;
	375
	376	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
	377	aligned_buffer = memalign(8, 512*1024);
	378	if (!aligned_buffer) {
	379	printf("Aligned buffer alloc failed!!!");
	380	return -1;
	381	}
	382	}
	383
470dcc75 JH	384	sdhci_set_power(host, fls(mmc->voltages) - 1);
	385
	386	if (host->quirks & SDHCI_QUIRK_NO_CD) {
	387	unsigned int status;
	388
	389	sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS \| SDHCI_CTRL_CD_TEST,
	390	SDHCI_HOST_CONTROL);
	391
	392	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	393	while ((!(status & SDHCI_CARD_PRESENT)) \|\|
	394	(!(status & SDHCI_CARD_STATE_STABLE)) \|\|
	395	(!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
	396	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	397	}
	398
ce0c1bc1 ŁM	399	/* Enable only interrupts served by the SD controller */
	400	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK
	401	, SDHCI_INT_ENABLE);
	402	/* Mask all sdhci interrupt sources */
	403	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
af62a557	404
af62a557 LW	405	return 0;
	406	}
	407
	408	int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
	409	{
	410	struct mmc *mmc;
	411	unsigned int caps;
	412
	413	mmc = malloc(sizeof(struct mmc));
	414	if (!mmc) {
	415	printf("mmc malloc fail!\n");
	416	return -1;
	417	}
	418
	419	mmc->priv = host;
6cf1b17c	420	host->mmc = mmc;
af62a557 LW	421
	422	sprintf(mmc->name, "%s", host->name);
	423	mmc->send_cmd = sdhci_send_command;
	424	mmc->set_ios = sdhci_set_ios;
	425	mmc->init = sdhci_init;
48972d90	426	mmc->getcd = NULL;
d23d8d7e	427	mmc->getwp = NULL;
af62a557 LW	428
	429	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	430	#ifdef CONFIG_MMC_SDMA
	431	if (!(caps & SDHCI_CAN_DO_SDMA)) {
	432	printf("Your controller don't support sdma!!\n");
	433	return -1;
	434	}
	435	#endif
	436
	437	if (max_clk)
	438	mmc->f_max = max_clk;
	439	else {
073cfd1c	440	if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
af62a557 LW	441	mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
	442	>> SDHCI_CLOCK_BASE_SHIFT;
	443	else
	444	mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
	445	>> SDHCI_CLOCK_BASE_SHIFT;
	446	mmc->f_max *= 1000000;
	447	}
	448	if (mmc->f_max == 0) {
	449	printf("Hardware doesn't specify base clock frequency\n");
	450	return -1;
	451	}
	452	if (min_clk)
	453	mmc->f_min = min_clk;
	454	else {
073cfd1c	455	if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
af62a557 LW	456	mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
	457	else
	458	mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
	459	}
	460
	461	mmc->voltages = 0;
	462	if (caps & SDHCI_CAN_VDD_330)
	463	mmc->voltages \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
	464	if (caps & SDHCI_CAN_VDD_300)
	465	mmc->voltages \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
	466	if (caps & SDHCI_CAN_VDD_180)
	467	mmc->voltages \|= MMC_VDD_165_195;
236bfecf JC	468
	469	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
	470	mmc->voltages \|= host->voltages;
	471
af62a557	472	mmc->host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT;
1695b29a JT	473	if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
	474	if (caps & SDHCI_CAN_DO_8BIT)
	475	mmc->host_caps \|= MMC_MODE_8BIT;
	476	}
236bfecf JC	477	if (host->host_caps)
236bfecf JC	478	mmc->host_caps \|= host->host_caps;
af62a557 LW	479
	480	sdhci_reset(host, SDHCI_RESET_ALL);
	481	mmc_register(mmc);
	482
	483	return 0;
	484	}