[people/ms/u-boot.git] / drivers / mmc / sdhci.c

/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <leiwen@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
 */

#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
#else
void *aligned_buffer;
#endif

static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
	unsigned long timeout;

	/* Wait max 100 ms */
	timeout = 100;
	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
		if (timeout == 0) {
			printf("%s: Reset 0x%x never completed.\n",
			       __func__, (int)mask);
			return;
		}
		timeout--;
		udelay(1000);
	}
}

static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
	int i;
	if (cmd->resp_type & MMC_RSP_136) {
		/* CRC is stripped so we need to do some shifting. */
		for (i = 0; i < 4; i++) {
			cmd->response[i] = sdhci_readl(host,
					SDHCI_RESPONSE + (3-i)*4) << 8;
			if (i != 3)
				cmd->response[i] |= sdhci_readb(host,
						SDHCI_RESPONSE + (3-i)*4-1);
		}
	} else {
		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	}
}

static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
{
	int i;
	char *offs;
	for (i = 0; i < data->blocksize; i += 4) {
		offs = data->dest + i;
		if (data->flags == MMC_DATA_READ)
			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
		else
			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
	}
}

static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
				unsigned int start_addr)
{
	unsigned int stat, rdy, mask, timeout, block = 0;
#ifdef CONFIG_MMC_SDMA
	unsigned char ctrl;
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif

	timeout = 1000000;
	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR) {
			printf("%s: Error detected in status(0x%X)!\n",
			       __func__, stat);
			return -1;
		}
		if (stat & rdy) {
			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
				continue;
			sdhci_writel(host, rdy, SDHCI_INT_STATUS);
			sdhci_transfer_pio(host, data);
			data->dest += data->blocksize;
			if (++block >= data->blocks)
				break;
		}
#ifdef CONFIG_MMC_SDMA
		if (stat & SDHCI_INT_DMA_END) {
			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		}
#endif
		if (timeout-- > 0)
			udelay(10);
		else {
			printf("%s: Transfer data timeout\n", __func__);
			return -1;
		}
	} while (!(stat & SDHCI_INT_DATA_END));
	return 0;
}

/*
 * No command will be sent by driver if card is busy, so driver must wait
 * for card ready state.
 * Every time when card is busy after timeout then (last) timeout value will be
 * increased twice but only if it doesn't exceed global defined maximum.
 * Each function call will use last timeout value.
 */
#define SDHCI_CMD_MAX_TIMEOUT			3200
#define SDHCI_CMD_DEFAULT_TIMEOUT		100
#define SDHCI_READ_STATUS_TIMEOUT		1000

#ifdef CONFIG_DM_MMC_OPS
static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

#else
static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
#endif
	struct sdhci_host *host = mmc->priv;
	unsigned int stat = 0;
	int ret = 0;
	int trans_bytes = 0, is_aligned = 1;
	u32 mask, flags, mode;
	unsigned int time = 0, start_addr = 0;
	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
	unsigned start = get_timer(0);

	/* Timeout unit - ms */
	static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;

	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		mask &= ~SDHCI_DATA_INHIBIT;

	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
		if (time >= cmd_timeout) {
			printf("%s: MMC: %d busy ", __func__, mmc_dev);
			if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
				cmd_timeout += cmd_timeout;
				printf("timeout increasing to: %u ms.\n",
				       cmd_timeout);
			} else {
				puts("timeout.\n");
				return -ECOMM;
			}
		}
		time++;
		udelay(1000);
	}

	mask = SDHCI_INT_RESPONSE;
	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->resp_type & MMC_RSP_BUSY) {
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
		if (data)
			mask |= SDHCI_INT_DATA_END;
	} else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
	if (data)
		flags |= SDHCI_CMD_DATA;

	/* Set Transfer mode regarding to data flag */
	if (data != 0) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
		mode = SDHCI_TRNS_BLK_CNT_EN;
		trans_bytes = data->blocks * data->blocksize;
		if (data->blocks > 1)
			mode |= SDHCI_TRNS_MULTI;

		if (data->flags == MMC_DATA_READ)
			mode |= SDHCI_TRNS_READ;

#ifdef CONFIG_MMC_SDMA
		if (data->flags == MMC_DATA_READ)
			start_addr = (unsigned long)data->dest;
		else
			start_addr = (unsigned long)data->src;
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				(start_addr & 0x7) != 0x0) {
			is_aligned = 0;
			start_addr = (unsigned long)aligned_buffer;
			if (data->flags != MMC_DATA_READ)
				memcpy(aligned_buffer, data->src, trans_bytes);
		}

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
		/*
		 * Always use this bounce-buffer when
		 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
		 */
		is_aligned = 0;
		start_addr = (unsigned long)aligned_buffer;
		if (data->flags != MMC_DATA_READ)
			memcpy(aligned_buffer, data->src, trans_bytes);
#endif

		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		mode |= SDHCI_TRNS_DMA;
#endif
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
				data->blocksize),
				SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
	} else if (cmd->resp_type & MMC_RSP_BUSY) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	}

	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDMA
	flush_cache(start_addr, trans_bytes);
#endif
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	start = get_timer(0);
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR)
			break;

		if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
			if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
				return 0;
			} else {
				printf("%s: Timeout for status update!\n",
				       __func__);
				return -ETIMEDOUT;
			}
		}
	} while ((stat & mask) != mask);

	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
		sdhci_cmd_done(host, cmd);
		sdhci_writel(host, mask, SDHCI_INT_STATUS);
	} else
		ret = -1;

	if (!ret && data)
		ret = sdhci_transfer_data(host, data, start_addr);

	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
		udelay(1000);

	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	if (!ret) {
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				!is_aligned && (data->flags == MMC_DATA_READ))
			memcpy(data->dest, aligned_buffer, trans_bytes);
		return 0;
	}

	sdhci_reset(host, SDHCI_RESET_CMD);
	sdhci_reset(host, SDHCI_RESET_DATA);
	if (stat & SDHCI_INT_TIMEOUT)
		return -ETIMEDOUT;
	else
		return -ECOMM;
}

static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
	struct sdhci_host *host = mmc->priv;
	unsigned int div, clk = 0, timeout, reg;

	/* Wait max 20 ms */
	timeout = 200;
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
			   (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
		if (timeout == 0) {
			printf("%s: Timeout to wait cmd & data inhibit\n",
			       __func__);
			return -1;
		}

		timeout--;
		udelay(100);
	}

	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return 0;

	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		/*
		 * Check if the Host Controller supports Programmable Clock
		 * Mode.
		 */
		if (host->clk_mul) {
			for (div = 1; div <= 1024; div++) {
				if ((mmc->cfg->f_max * host->clk_mul / div)
					<= clock)
					break;
			}

			/*
			 * Set Programmable Clock Mode in the Clock
			 * Control register.
			 */
			clk = SDHCI_PROG_CLOCK_MODE;
			div--;
		} else {
			/* Version 3.00 divisors must be a multiple of 2. */
			if (mmc->cfg->f_max <= clock) {
				div = 1;
			} else {
				for (div = 2;
				     div < SDHCI_MAX_DIV_SPEC_300;
				     div += 2) {
					if ((mmc->cfg->f_max / div) <= clock)
						break;
				}
			}
			div >>= 1;
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
			if ((mmc->cfg->f_max / div) <= clock)
				break;
		}
		div >>= 1;
	}

	if (host->set_clock)
		host->set_clock(host->index, div);

	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			printf("%s: Internal clock never stabilised.\n",
			       __func__);
			return -1;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	return 0;
}

static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
	u8 pwr = 0;

	if (power != (unsigned short)-1) {
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		}
	}

	if (pwr == 0) {
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
		return;
	}

	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

	pwr |= SDHCI_POWER_ON;

	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}

#ifdef CONFIG_DM_MMC_OPS
static int sdhci_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static void sdhci_set_ios(struct mmc *mmc)
{
#endif
	u32 ctrl;
	struct sdhci_host *host = mmc->priv;

	if (host->set_control_reg)
		host->set_control_reg(host);

	if (mmc->clock != host->clock)
		sdhci_set_clock(mmc, mmc->clock);

	/* Set bus width */
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if (mmc->bus_width == 8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (mmc->bus_width == 4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}

	if (mmc->clock > 26000000)
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
		ctrl &= ~SDHCI_CTRL_HISPD;

	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#ifdef CONFIG_DM_MMC_OPS
	return 0;
#endif
}

static int sdhci_init(struct mmc *mmc)
{
	struct sdhci_host *host = mmc->priv;

	sdhci_reset(host, SDHCI_RESET_ALL);

	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
		aligned_buffer = memalign(8, 512*1024);
		if (!aligned_buffer) {
			printf("%s: Aligned buffer alloc failed!!!\n",
			       __func__);
			return -1;
		}
	}

	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);

	if (host->quirks & SDHCI_QUIRK_NO_CD) {
#if defined(CONFIG_PIC32_SDHCI)
		/* PIC32 SDHCI CD errata:
		 * - set CD_TEST and clear CD_TEST_INS bit
		 */
		sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
#else
		unsigned int status;

		sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
			SDHCI_HOST_CONTROL);

		status = sdhci_readl(host, SDHCI_PRESENT_STATE);
		while ((!(status & SDHCI_CARD_PRESENT)) ||
		    (!(status & SDHCI_CARD_STATE_STABLE)) ||
		    (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
			status = sdhci_readl(host, SDHCI_PRESENT_STATE);
#endif
	}

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
		     SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}

#ifdef CONFIG_DM_MMC_OPS
int sdhci_probe(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return sdhci_init(mmc);
}

const struct dm_mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
};
#else
static const struct mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
	.init		= sdhci_init,
};
#endif

int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
		u32 max_clk, u32 min_clk)
{
	u32 caps, caps_1;

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);

#ifdef CONFIG_MMC_SDMA
	if (!(caps & SDHCI_CAN_DO_SDMA)) {
		printf("%s: Your controller doesn't support SDMA!!\n",
		       __func__);
		return -EINVAL;
	}
#endif
	if (host->quirks & SDHCI_QUIRK_REG32_RW)
		host->version =
			sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
	else
		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);

	cfg->name = host->name;
#ifndef CONFIG_DM_MMC_OPS
	cfg->ops = &sdhci_ops;
#endif
	if (max_clk)
		cfg->f_max = max_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
				SDHCI_CLOCK_BASE_SHIFT;
		else
			cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
				SDHCI_CLOCK_BASE_SHIFT;
		cfg->f_max *= 1000000;
	}
	if (cfg->f_max == 0) {
		printf("%s: Hardware doesn't specify base clock frequency\n",
		       __func__);
		return -EINVAL;
	}
	if (min_clk)
		cfg->f_min = min_clk;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
		else
			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
	}
	cfg->voltages = 0;
	if (caps & SDHCI_CAN_VDD_330)
		cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
	if (caps & SDHCI_CAN_VDD_300)
		cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & SDHCI_CAN_VDD_180)
		cfg->voltages |= MMC_VDD_165_195;

	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
		cfg->voltages |= host->voltages;

	cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		if (caps & SDHCI_CAN_DO_8BIT)
			cfg->host_caps |= MMC_MODE_8BIT;
	}

	if (host->host_caps)
		cfg->host_caps |= host->host_caps;


	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	/*
	 * In case of Host Controller v3.00, find out whether clock
	 * multiplier is supported.
	 */
	caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
			SDHCI_CLOCK_MUL_SHIFT;

	return 0;
}

#ifdef CONFIG_BLK
int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
{
	return mmc_bind(dev, mmc, cfg);
}
#else
int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
	int ret;

	ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
	if (ret)
		return ret;

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL) {
		printf("%s: mmc create fail!\n", __func__);
		return -1;
	}

	return 0;
}
#endif
Commit	Line	Data
af62a557 LW	1	/*
	2	* Copyright 2011, Marvell Semiconductor Inc.
	3	* Lei Wen <leiwen@marvell.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
af62a557 LW	6	*
	7	* Back ported to the 8xx platform (from the 8260 platform) by
	8	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
	9	*/
	10
	11	#include <common.h>
2a809093	12	#include <errno.h>
af62a557 LW	13	#include <malloc.h>
	14	#include <mmc.h>
	15	#include <sdhci.h>
	16
492d3223 SR	17	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	18	void aligned_buffer = (void )CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
	19	#else
af62a557	20	void *aligned_buffer;
492d3223	21	#endif
af62a557 LW	22
	23	static void sdhci_reset(struct sdhci_host *host, u8 mask)
	24	{
	25	unsigned long timeout;
	26
	27	/* Wait max 100 ms */
	28	timeout = 100;
	29	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	30	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
	31	if (timeout == 0) {
30e6d979 DR	32	printf("%s: Reset 0x%x never completed.\n",
30e6d979 DR	33	__func__, (int)mask);
af62a557 LW	34	return;
	35	}
	36	timeout--;
	37	udelay(1000);
	38	}
	39	}
	40
	41	static void sdhci_cmd_done(struct sdhci_host host, struct mmc_cmd cmd)
	42	{
	43	int i;
	44	if (cmd->resp_type & MMC_RSP_136) {
	45	/* CRC is stripped so we need to do some shifting. */
	46	for (i = 0; i < 4; i++) {
	47	cmd->response[i] = sdhci_readl(host,
	48	SDHCI_RESPONSE + (3-i)*4) << 8;
	49	if (i != 3)
	50	cmd->response[i] \|= sdhci_readb(host,
	51	SDHCI_RESPONSE + (3-i)*4-1);
	52	}
	53	} else {
	54	cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	55	}
	56	}
	57
	58	static void sdhci_transfer_pio(struct sdhci_host host, struct mmc_data data)
	59	{
	60	int i;
	61	char *offs;
	62	for (i = 0; i < data->blocksize; i += 4) {
	63	offs = data->dest + i;
	64	if (data->flags == MMC_DATA_READ)
	65	(u32 )offs = sdhci_readl(host, SDHCI_BUFFER);
	66	else
	67	sdhci_writel(host, (u32 )offs, SDHCI_BUFFER);
	68	}
	69	}
	70
	71	static int sdhci_transfer_data(struct sdhci_host host, struct mmc_data data,
	72	unsigned int start_addr)
	73	{
a004abde	74	unsigned int stat, rdy, mask, timeout, block = 0;
804c7f42 JC	75	#ifdef CONFIG_MMC_SDMA
804c7f42 JC	76	unsigned char ctrl;
2c011847	77	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
804c7f42	78	ctrl &= ~SDHCI_CTRL_DMA_MASK;
2c011847	79	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
804c7f42	80	#endif
af62a557	81
5d48e422	82	timeout = 1000000;
af62a557 LW	83	rdy = SDHCI_INT_SPACE_AVAIL \| SDHCI_INT_DATA_AVAIL;
	84	mask = SDHCI_DATA_AVAILABLE \| SDHCI_SPACE_AVAILABLE;
	85	do {
	86	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	87	if (stat & SDHCI_INT_ERROR) {
30e6d979 DR	88	printf("%s: Error detected in status(0x%X)!\n",
30e6d979 DR	89	__func__, stat);
af62a557 LW	90	return -1;
	91	}
	92	if (stat & rdy) {
	93	if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
	94	continue;
	95	sdhci_writel(host, rdy, SDHCI_INT_STATUS);
	96	sdhci_transfer_pio(host, data);
	97	data->dest += data->blocksize;
	98	if (++block >= data->blocks)
	99	break;
	100	}
	101	#ifdef CONFIG_MMC_SDMA
	102	if (stat & SDHCI_INT_DMA_END) {
	103	sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
3e81c772	104	start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
af62a557 LW	105	start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
	106	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	107	}
	108	#endif
a004abde LW	109	if (timeout-- > 0)
	110	udelay(10);
	111	else {
30e6d979	112	printf("%s: Transfer data timeout\n", __func__);
a004abde LW	113	return -1;
a004abde LW	114	}
af62a557 LW	115	} while (!(stat & SDHCI_INT_DATA_END));
	116	return 0;
	117	}
	118
56b34bc6 PM	119	/*
	120	* No command will be sent by driver if card is busy, so driver must wait
	121	* for card ready state.
	122	* Every time when card is busy after timeout then (last) timeout value will be
	123	* increased twice but only if it doesn't exceed global defined maximum.
65a25b20	124	* Each function call will use last timeout value.
56b34bc6	125	*/
65a25b20	126	#define SDHCI_CMD_MAX_TIMEOUT 3200
d8ce77b2	127	#define SDHCI_CMD_DEFAULT_TIMEOUT 100
d90bb439	128	#define SDHCI_READ_STATUS_TIMEOUT 1000
56b34bc6	129
ef1e4eda SG	130	#ifdef CONFIG_DM_MMC_OPS
	131	static int sdhci_send_command(struct udevice dev, struct mmc_cmd cmd,
	132	struct mmc_data *data)
	133	{
	134	struct mmc *mmc = mmc_get_mmc_dev(dev);
	135
	136	#else
6588c78b	137	static int sdhci_send_command(struct mmc mmc, struct mmc_cmd cmd,
ef1e4eda	138	struct mmc_data *data)
af62a557	139	{
ef1e4eda	140	#endif
93bfd616	141	struct sdhci_host *host = mmc->priv;
af62a557 LW	142	unsigned int stat = 0;
	143	int ret = 0;
	144	int trans_bytes = 0, is_aligned = 1;
	145	u32 mask, flags, mode;
56b34bc6	146	unsigned int time = 0, start_addr = 0;
19d2e342	147	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
29905a45	148	unsigned start = get_timer(0);
af62a557	149
56b34bc6	150	/* Timeout unit - ms */
d8ce77b2	151	static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
af62a557 LW	152
	153	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	154	mask = SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT;
	155
	156	/* We shouldn't wait for data inihibit for stop commands, even
	157	though they might use busy signaling */
	158	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	159	mask &= ~SDHCI_DATA_INHIBIT;
	160
	161	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
56b34bc6	162	if (time >= cmd_timeout) {
30e6d979	163	printf("%s: MMC: %d busy ", __func__, mmc_dev);
65a25b20	164	if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
56b34bc6 PM	165	cmd_timeout += cmd_timeout;
	166	printf("timeout increasing to: %u ms.\n",
	167	cmd_timeout);
	168	} else {
	169	puts("timeout.\n");
915ffa52	170	return -ECOMM;
56b34bc6	171	}
af62a557	172	}
56b34bc6	173	time++;
af62a557 LW	174	udelay(1000);
	175	}
	176
	177	mask = SDHCI_INT_RESPONSE;
	178	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	179	flags = SDHCI_CMD_RESP_NONE;
	180	else if (cmd->resp_type & MMC_RSP_136)
	181	flags = SDHCI_CMD_RESP_LONG;
	182	else if (cmd->resp_type & MMC_RSP_BUSY) {
	183	flags = SDHCI_CMD_RESP_SHORT_BUSY;
17ea3c86 JC	184	if (data)
17ea3c86 JC	185	mask \|= SDHCI_INT_DATA_END;
af62a557 LW	186	} else
	187	flags = SDHCI_CMD_RESP_SHORT;
	188
	189	if (cmd->resp_type & MMC_RSP_CRC)
	190	flags \|= SDHCI_CMD_CRC;
	191	if (cmd->resp_type & MMC_RSP_OPCODE)
	192	flags \|= SDHCI_CMD_INDEX;
	193	if (data)
	194	flags \|= SDHCI_CMD_DATA;
	195
30e6d979	196	/* Set Transfer mode regarding to data flag */
af62a557 LW	197	if (data != 0) {
	198	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	199	mode = SDHCI_TRNS_BLK_CNT_EN;
	200	trans_bytes = data->blocks * data->blocksize;
	201	if (data->blocks > 1)
	202	mode \|= SDHCI_TRNS_MULTI;
	203
	204	if (data->flags == MMC_DATA_READ)
	205	mode \|= SDHCI_TRNS_READ;
	206
	207	#ifdef CONFIG_MMC_SDMA
	208	if (data->flags == MMC_DATA_READ)
3c1fcb77	209	start_addr = (unsigned long)data->dest;
af62a557	210	else
3c1fcb77	211	start_addr = (unsigned long)data->src;
af62a557 LW	212	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	213	(start_addr & 0x7) != 0x0) {
	214	is_aligned = 0;
3c1fcb77	215	start_addr = (unsigned long)aligned_buffer;
af62a557 LW	216	if (data->flags != MMC_DATA_READ)
	217	memcpy(aligned_buffer, data->src, trans_bytes);
	218	}
	219
492d3223 SR	220	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	221	/*
	222	* Always use this bounce-buffer when
	223	* CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
	224	*/
	225	is_aligned = 0;
	226	start_addr = (unsigned long)aligned_buffer;
	227	if (data->flags != MMC_DATA_READ)
	228	memcpy(aligned_buffer, data->src, trans_bytes);
	229	#endif
	230
af62a557 LW	231	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	232	mode \|= SDHCI_TRNS_DMA;
	233	#endif
	234	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
	235	data->blocksize),
	236	SDHCI_BLOCK_SIZE);
	237	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
	238	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
5e1c23cd KL	239	} else if (cmd->resp_type & MMC_RSP_BUSY) {
5e1c23cd KL	240	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
af62a557 LW	241	}
	242
	243	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
	244	#ifdef CONFIG_MMC_SDMA
2c2ec4c9	245	flush_cache(start_addr, trans_bytes);
af62a557 LW	246	#endif
af62a557 LW	247	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
29905a45	248	start = get_timer(0);
af62a557 LW	249	do {
	250	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	251	if (stat & SDHCI_INT_ERROR)
	252	break;
af62a557	253
bae4a1fd MY	254	if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
	255	if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
	256	return 0;
	257	} else {
	258	printf("%s: Timeout for status update!\n",
	259	__func__);
915ffa52	260	return -ETIMEDOUT;
bae4a1fd	261	}
3a638320	262	}
bae4a1fd	263	} while ((stat & mask) != mask);
3a638320	264
af62a557 LW	265	if ((stat & (SDHCI_INT_ERROR \| mask)) == mask) {
	266	sdhci_cmd_done(host, cmd);
	267	sdhci_writel(host, mask, SDHCI_INT_STATUS);
	268	} else
	269	ret = -1;
	270
	271	if (!ret && data)
	272	ret = sdhci_transfer_data(host, data, start_addr);
	273
13243f2e TB	274	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
	275	udelay(1000);
	276
af62a557 LW	277	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	278	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	279	if (!ret) {
	280	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	281	!is_aligned && (data->flags == MMC_DATA_READ))
	282	memcpy(data->dest, aligned_buffer, trans_bytes);
	283	return 0;
	284	}
	285
	286	sdhci_reset(host, SDHCI_RESET_CMD);
	287	sdhci_reset(host, SDHCI_RESET_DATA);
	288	if (stat & SDHCI_INT_TIMEOUT)
915ffa52	289	return -ETIMEDOUT;
af62a557	290	else
915ffa52	291	return -ECOMM;
af62a557 LW	292	}
	293
	294	static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
	295	{
93bfd616	296	struct sdhci_host *host = mmc->priv;
6dffdbc3	297	unsigned int div, clk = 0, timeout, reg;
af62a557	298
79667b7b WY	299	/* Wait max 20 ms */
	300	timeout = 200;
	301	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
	302	(SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT)) {
	303	if (timeout == 0) {
	304	printf("%s: Timeout to wait cmd & data inhibit\n",
	305	__func__);
	306	return -1;
	307	}
	308
	309	timeout--;
	310	udelay(100);
	311	}
	312
	313	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1d405e20	314	reg &= ~(SDHCI_CLOCK_CARD_EN \| SDHCI_CLOCK_INT_EN);
79667b7b	315	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
af62a557 LW	316
	317	if (clock == 0)
	318	return 0;
	319
113e5dfc	320	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
6dffdbc3 WY	321	/*
	322	* Check if the Host Controller supports Programmable Clock
	323	* Mode.
	324	*/
	325	if (host->clk_mul) {
	326	for (div = 1; div <= 1024; div++) {
	327	if ((mmc->cfg->f_max * host->clk_mul / div)
	328	<= clock)
af62a557 LW	329	break;
af62a557 LW	330	}
6dffdbc3 WY	331
	332	/*
	333	* Set Programmable Clock Mode in the Clock
	334	* Control register.
	335	*/
	336	clk = SDHCI_PROG_CLOCK_MODE;
	337	div--;
	338	} else {
	339	/* Version 3.00 divisors must be a multiple of 2. */
	340	if (mmc->cfg->f_max <= clock) {
	341	div = 1;
	342	} else {
	343	for (div = 2;
	344	div < SDHCI_MAX_DIV_SPEC_300;
	345	div += 2) {
	346	if ((mmc->cfg->f_max / div) <= clock)
	347	break;
	348	}
	349	}
	350	div >>= 1;
af62a557 LW	351	}
	352	} else {
	353	/* Version 2.00 divisors must be a power of 2. */
	354	for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
93bfd616	355	if ((mmc->cfg->f_max / div) <= clock)
af62a557 LW	356	break;
af62a557 LW	357	}
6dffdbc3	358	div >>= 1;
af62a557	359	}
af62a557	360
b09ed6e4 JC	361	if (host->set_clock)
	362	host->set_clock(host->index, div);
	363
6dffdbc3	364	clk \|= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
af62a557 LW	365	clk \|= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
	366	<< SDHCI_DIVIDER_HI_SHIFT;
	367	clk \|= SDHCI_CLOCK_INT_EN;
	368	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	369
	370	/* Wait max 20 ms */
	371	timeout = 20;
	372	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	373	& SDHCI_CLOCK_INT_STABLE)) {
	374	if (timeout == 0) {
30e6d979 DR	375	printf("%s: Internal clock never stabilised.\n",
30e6d979 DR	376	__func__);
af62a557 LW	377	return -1;
	378	}
	379	timeout--;
	380	udelay(1000);
	381	}
	382
	383	clk \|= SDHCI_CLOCK_CARD_EN;
	384	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	385	return 0;
	386	}
	387
	388	static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
	389	{
	390	u8 pwr = 0;
	391
	392	if (power != (unsigned short)-1) {
	393	switch (1 << power) {
	394	case MMC_VDD_165_195:
	395	pwr = SDHCI_POWER_180;
	396	break;
	397	case MMC_VDD_29_30:
	398	case MMC_VDD_30_31:
	399	pwr = SDHCI_POWER_300;
	400	break;
	401	case MMC_VDD_32_33:
	402	case MMC_VDD_33_34:
	403	pwr = SDHCI_POWER_330;
	404	break;
	405	}
	406	}
	407
	408	if (pwr == 0) {
	409	sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
	410	return;
	411	}
	412
688c2d14 MC	413	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
	414	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	415
af62a557 LW	416	pwr \|= SDHCI_POWER_ON;
	417
	418	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	419	}
	420
ef1e4eda SG	421	#ifdef CONFIG_DM_MMC_OPS
	422	static int sdhci_set_ios(struct udevice *dev)
	423	{
	424	struct mmc *mmc = mmc_get_mmc_dev(dev);
	425	#else
6588c78b	426	static void sdhci_set_ios(struct mmc *mmc)
af62a557	427	{
ef1e4eda	428	#endif
af62a557	429	u32 ctrl;
93bfd616	430	struct sdhci_host *host = mmc->priv;
af62a557	431
236bfecf JC	432	if (host->set_control_reg)
	433	host->set_control_reg(host);
	434
af62a557 LW	435	if (mmc->clock != host->clock)
	436	sdhci_set_clock(mmc, mmc->clock);
	437
	438	/* Set bus width */
	439	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	440	if (mmc->bus_width == 8) {
	441	ctrl &= ~SDHCI_CTRL_4BITBUS;
113e5dfc JC	442	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
113e5dfc JC	443	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	444	ctrl \|= SDHCI_CTRL_8BITBUS;
af62a557 LW	445	} else {
f88a429f MR	446	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
f88a429f MR	447	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	448	ctrl &= ~SDHCI_CTRL_8BITBUS;
	449	if (mmc->bus_width == 4)
	450	ctrl \|= SDHCI_CTRL_4BITBUS;
	451	else
	452	ctrl &= ~SDHCI_CTRL_4BITBUS;
	453	}
	454
	455	if (mmc->clock > 26000000)
	456	ctrl \|= SDHCI_CTRL_HISPD;
	457	else
	458	ctrl &= ~SDHCI_CTRL_HISPD;
	459
236bfecf JC	460	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
	461	ctrl &= ~SDHCI_CTRL_HISPD;
	462
af62a557	463	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
ef1e4eda SG	464	#ifdef CONFIG_DM_MMC_OPS
	465	return 0;
	466	#endif
af62a557 LW	467	}
af62a557 LW	468
6588c78b	469	static int sdhci_init(struct mmc *mmc)
af62a557	470	{
93bfd616	471	struct sdhci_host *host = mmc->priv;
af62a557	472
8d549b61 MY	473	sdhci_reset(host, SDHCI_RESET_ALL);
8d549b61 MY	474
af62a557 LW	475	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
	476	aligned_buffer = memalign(8, 512*1024);
	477	if (!aligned_buffer) {
30e6d979 DR	478	printf("%s: Aligned buffer alloc failed!!!\n",
30e6d979 DR	479	__func__);
af62a557 LW	480	return -1;
	481	}
	482	}
	483
93bfd616	484	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
470dcc75 JH	485
470dcc75 JH	486	if (host->quirks & SDHCI_QUIRK_NO_CD) {
102142c9 AP	487	#if defined(CONFIG_PIC32_SDHCI)
	488	/* PIC32 SDHCI CD errata:
	489	* - set CD_TEST and clear CD_TEST_INS bit
	490	*/
	491	sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
	492	#else
470dcc75 JH	493	unsigned int status;
470dcc75 JH	494
e113fe3c	495	sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS \| SDHCI_CTRL_CD_TEST,
470dcc75 JH	496	SDHCI_HOST_CONTROL);
	497
	498	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
	499	while ((!(status & SDHCI_CARD_PRESENT)) \|\|
	500	(!(status & SDHCI_CARD_STATE_STABLE)) \|\|
	501	(!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
	502	status = sdhci_readl(host, SDHCI_PRESENT_STATE);
102142c9	503	#endif
470dcc75 JH	504	}
470dcc75 JH	505
ce0c1bc1	506	/* Enable only interrupts served by the SD controller */
30e6d979 DR	507	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK,
30e6d979 DR	508	SDHCI_INT_ENABLE);
ce0c1bc1 ŁM	509	/* Mask all sdhci interrupt sources */
ce0c1bc1 ŁM	510	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
af62a557	511
af62a557 LW	512	return 0;
	513	}
	514
ef1e4eda SG	515	#ifdef CONFIG_DM_MMC_OPS
	516	int sdhci_probe(struct udevice *dev)
	517	{
	518	struct mmc *mmc = mmc_get_mmc_dev(dev);
	519
	520	return sdhci_init(mmc);
	521	}
ab769f22	522
ef1e4eda SG	523	const struct dm_mmc_ops sdhci_ops = {
	524	.send_cmd = sdhci_send_command,
	525	.set_ios = sdhci_set_ios,
	526	};
	527	#else
ab769f22 PA	528	static const struct mmc_ops sdhci_ops = {
	529	.send_cmd = sdhci_send_command,
	530	.set_ios = sdhci_set_ios,
	531	.init = sdhci_init,
	532	};
ef1e4eda	533	#endif
ab769f22	534
14bed52d JC	535	int sdhci_setup_cfg(struct mmc_config cfg, struct sdhci_host host,
14bed52d JC	536	u32 max_clk, u32 min_clk)
af62a557	537	{
6dffdbc3	538	u32 caps, caps_1;
14bed52d JC	539
14bed52d JC	540	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
15bd0995 MY	541
	542	#ifdef CONFIG_MMC_SDMA
	543	if (!(caps & SDHCI_CAN_DO_SDMA)) {
	544	printf("%s: Your controller doesn't support SDMA!!\n",
	545	__func__);
	546	return -EINVAL;
	547	}
	548	#endif
895549a2 JC	549	if (host->quirks & SDHCI_QUIRK_REG32_RW)
	550	host->version =
	551	sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
	552	else
	553	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
14bed52d JC	554
14bed52d JC	555	cfg->name = host->name;
2a809093 SG	556	#ifndef CONFIG_DM_MMC_OPS
2a809093 SG	557	cfg->ops = &sdhci_ops;
af62a557	558	#endif
af62a557	559	if (max_clk)
2a809093	560	cfg->f_max = max_clk;
af62a557	561	else {
14bed52d	562	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
2a809093 SG	563	cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
2a809093 SG	564	SDHCI_CLOCK_BASE_SHIFT;
af62a557	565	else
2a809093 SG	566	cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
	567	SDHCI_CLOCK_BASE_SHIFT;
	568	cfg->f_max *= 1000000;
af62a557	569	}
6c67954c MY	570	if (cfg->f_max == 0) {
	571	printf("%s: Hardware doesn't specify base clock frequency\n",
	572	__func__);
2a809093	573	return -EINVAL;
6c67954c	574	}
af62a557	575	if (min_clk)
2a809093	576	cfg->f_min = min_clk;
af62a557	577	else {
14bed52d	578	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
2a809093	579	cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
af62a557	580	else
2a809093	581	cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
af62a557	582	}
2a809093	583	cfg->voltages = 0;
af62a557	584	if (caps & SDHCI_CAN_VDD_330)
2a809093	585	cfg->voltages \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
af62a557	586	if (caps & SDHCI_CAN_VDD_300)
2a809093	587	cfg->voltages \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
af62a557	588	if (caps & SDHCI_CAN_VDD_180)
2a809093	589	cfg->voltages \|= MMC_VDD_165_195;
236bfecf	590
3137e645 MY	591	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
	592	cfg->voltages \|= host->voltages;
	593
2a809093	594	cfg->host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT;
14bed52d	595	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
1695b29a	596	if (caps & SDHCI_CAN_DO_8BIT)
2a809093	597	cfg->host_caps \|= MMC_MODE_8BIT;
1695b29a	598	}
42979002	599
14bed52d JC	600	if (host->host_caps)
14bed52d JC	601	cfg->host_caps \|= host->host_caps;
42979002	602
ef1e4eda	603
2a809093	604	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
93bfd616	605
6dffdbc3 WY	606	/*
	607	* In case of Host Controller v3.00, find out whether clock
	608	* multiplier is supported.
	609	*/
	610	caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	611	host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
	612	SDHCI_CLOCK_MUL_SHIFT;
	613
2a809093 SG	614	return 0;
	615	}
	616
ef1e4eda SG	617	#ifdef CONFIG_BLK
	618	int sdhci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg)
	619	{
	620	return mmc_bind(dev, mmc, cfg);
	621	}
	622	#else
2a809093 SG	623	int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
2a809093 SG	624	{
6c67954c MY	625	int ret;
6c67954c MY	626
6c67954c MY	627	ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
	628	if (ret)
	629	return ret;
2a809093	630
93bfd616 PA	631	host->mmc = mmc_create(&host->cfg, host);
	632	if (host->mmc == NULL) {
	633	printf("%s: mmc create fail!\n", __func__);
	634	return -1;
	635	}
af62a557 LW	636
	637	return 0;
	638	}
ef1e4eda	639	#endif